Page 1
DATA SH EET
DISCRETE SEMICONDUCTORS
BF1202; BF1202R; BF1202WR
N-channel dual-gate PoLo
MOS-FETs
Product specification
Supersedes data of 2000 Mar 29
2010 Sep 16
Page 2
NXP Semiconductors Product specification
handbook, 2 columns
Top view
MSB014
12
34
Fig.1 Simplified outline
(SOT143B).
BF1202 marking code: LD*
handbook, 2 columns
Top view MSB035
12
43
Fig.2 Simplified outline
(SOT143R).
BF1202R marking code: LE*
Top view
MSB842
21
43
Fig.3 Simplified outline
(SOT343R).
BF1202WR marking code: LE*
N-channel dual-gate PoLo MOS-FETs BF1202; BF1202R; BF1202WR
FEATURES
Short channel transistor with high
forward transfer admittance to input
capacitance ratio
Low noise gain controlled amplifier
Partly internal self-biasing circuit to
ensure good cross-modulation
performance during AGC and go od
DC stabilization.
APPLICATIONS
VHF and UHF applications with
3 to 9 V supply voltage, such as
digital and analogue television
tuners and professional
communications equipment.
DESCRIPTION
Enhancement type N-channel
field-effect transistor with source and
substrate interconnected. Integrated
diodes between gates and source
protect against excessive input
voltage surges. The BF1202,
BF1202R and BF1202WR are
encapsulated in the SOT143B,
SOT143R and SOT343R plastic
packages respectively.
PINNING
PIN DESCRIPTION
1source
2drain
3gate2
4gate1
Marking code legend:
* = - : made in Hong Kong
* = p : made in Hong Kong
* = t : made in Malaysia
QUICK REFERENCE DATA
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V
DS
I
D
P
tot
forward transfer admittance 25 30 40 mS
y
fs
C
ig1-ss
C
rss
F noise figure f = 800 MHz 1.1 1.8 dB
X
mod
T
j
This product is supplied in anti-static packing to prevent damage caused by electrostatic discharge during transport
and handling.
2010 Sep 16 2
drain-source voltage 10 V
drain current 30 mA
total power dissipation 200 mW
input capacitance at gate 1 1.7 2.2 pF
reverse transfer capacitance f = 1 MHz 15 30 fF
cross-modulation input level for k = 1% at
100 105 dBV
40 dB AGC
operating junction temperature 150 C
CAUTION
Page 3
NXP Semiconductors Product specification
handbook, halfpage
050
(1)
(2)
Ts (°C)
P
tot
(mW)
100 200
250
0
200
150
150
100
50
MCD951
Fig.4 Power derating curve.
(1) BF1202WR.
(2) BF1202; BF1202R.
N-channel dual-gate PoLo MOS-FETs BF1202; BF1202R; BF1202WR
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
DS
I
D
I
G1
I
G2
P
tot
T
stg
T
j
Note
1. T
s
drain-source voltage 10 V
drain current 30 mA
gate 1 current 10 mA
gate 2 current 10 mA
total power dissipation
BF1202; BF1202R T
BF1202WR T
113 C; note 1 200 mW
s
119 C; note 1 200 mW
s
storage temperature 65 +150 C
operating junction temperature 150 C
is the temperature of the soldering point of the source lead.
THERMAL CHARACTERISTICS
SYMBOL PARAMETER VALUE UNIT
R
th j-s
thermal resistance from junction to soldering point
BF1202; BF1202R 185 K/W
BF1202WR 155 K/W
2010 Sep 16 3
Page 4
NXP Semiconductors Product specification
N-channel dual-gate PoLo MOS-FETs BF1202; BF1202R; BF1202WR
STATIC CHARACTERISTICS
T
=25C unless otherwise specified.
j
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
(BR)DSS
V
(BR)G1-SS
V
(BR)G2-SS
V
(F)S-G1
V
(F)S-G2
V
G1-S(th)
V
G2-S(th)
I
DSX
I
G1-SS
I
G2-SS
drain-source breakdown voltage V
gate 1-source breakdown voltage V
gate 2-source breakdown voltage V
forward source-gate 1 voltage V
forward source-gate 2 voltage V
gate 1-source threshold voltage V
gate 2-source threshold voltage V
drain-source current V
gate 1 cut-off current V
gate 2 cut-off current V
G1-S=VG2-S
G2-S=VDS
G1-S=VDS
G2-S=VDS
G1-S=VDS
=4V; VDS=5V; ID=100A0.31.0V
G2-S
=5V; VDS=5V; ID=100A0.31.2V
G1-S
=4V; VDS=5V; RG1=120k;
G2-S
=0; ID=10A10 V
=0; I
=0; I
=0; I
=0; I
=10mA 6 V
G1-S
=10mA 6 V
G2-S
=10mA 0.5 1.5 V
S-G1
=10mA 0.5 1.5 V
S-G2
816mA
note 1
G2-S=VDS
G1-S=VDS
=0; V
=0; V
=5V 50 nA
G1-S
=4V 20 nA
G2-S
Note
1. R
connects G1to VGG=5V.
G1
DYNAMIC CHARACTERISTICS
Common source; T
=25C; V
amb
=4V; VDS=5V; ID= 12 mA; unless otherwise specified.
G2-S
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
forward transfer admittance pulsed; Tj=25C 253040mS
y
fs
C
ig1-ss
C
ig2-ss
C
oss
C
rss
F noise figure f = 10.7 MHz; G
G
tr
X
mod
input capacitance at gate 1 f = 1 MHz 1.7 2.2 pF
input capacitance at gate 2 f = 1 MHz 1 pF
output capacitance f = 1 MHz 0.85 pF
reverse transfer capacitance f = 1 MHz 15 30 fF
=20mS; BS=0 911dB
S
f=400MHz; Y
f=800MHz; Y
S=YSopt
S=YSopt
power gain f = 200 MHz; GS=2mS; BS=B
G
= 0.5 mS; BL=B
L
f=400MHz; G
=1mS; BL=B
G
L
f=800MHz; G
G
=1mS; BL=B
L
Lopt
=2mS; BS=B
S
Lopt
= 3.3 mS; BS=B
S
Lopt
Sopt
Sopt
Sopt
0.9 1.5 dB
1.1 1.8 dB
;
34.5 dB
;
30.5 dB
;
26.5 dB
cross-modulation input level for k = 1%; fw=50MHz;
=60MHz; note1
f
unw
at 0 dB AGC 90 dBV
at 10 dB AGC 92 dBV
at 40 dB AGC 100 105 dBV
Note
1. Measured in Fig.21 test circuit.
2010 Sep 16 4
Page 5
NXP Semiconductors Product specification
handbook, halfpage
02
20
0
4
8
12
16
0.4 0.8 1.2 1.6
V
G1-S
(V)
I
D
(mA)
MCD952
V
G2-S
= 4 V
2.5 V
3.5 V
3 V
2 V
1.5 V
1 V
Fig.5 Transfer characteristics; typical values.
VDS=5V.
Tj=25C.
handbook, halfpage
010
24
0
8
16
2
VDS (V)
I
D
(mA)
648
MCD953
V
G1-S
= 1.5 V
1.4 V
1.2 V
1.3 V
1.1 V
1 V
0.9 V
Fig.6 Output characteristics; typical values.
V
G2-S
=4V.
Tj=25C.
handbook, halfpage
0 2.5
100
0
20
40
60
80
0.5 1 1.5 2
V
G1-S
(V)
I
G1
(μA)
MCD954
V
G2-S
= 4 V
3.5 V
3 V
2.5 V
2 V
1.5 V
1 V
Fig.7 Gate 1 current as a function of gate 1
voltage; typical values.
VDS=5V.
T
j
=25C.
VDS=5V.
T
j
=25C.
handbook, halfpage
0
ID (mA)
420
40
30
10
0
20
81216
MCD955
y
fs
(mS)
3.5 V
2.5 V
3 V
2 V
V
G2-S
= 4 V
Fig.8 Forward transfer admittance as a function
of drain current; typical values.
VDS=5V.
T
j
=25C.
N-channel dual-gate PoLo MOS-FETs BF1202; BF1202R; BF1202WR
2010 Sep 16 5
Page 6
NXP Semiconductors Product specification
handbook, halfpage
050
20
0
4
8
12
16
10 20 30 40
IG1 (μA)
I
D
(mA)
MCD956
Fig.9 Drain current as a function of gate 1 current;
typical values.
VDS=5V; V
G2-S
=4V.
Tj=25C.
handbook, halfpage
0
VGG (V)
15
16
12
4
0
8
23 4
MCD957
I
D
(mA)
Fig.10 Drain current as a function of gate 1 supply
voltage (= V
GG
); typical values.
VDS=5V; V
G2-S
=4V; Tj=25C.
RG1=120k (connected to VGG); see Fig.21.
handbook, halfpage
0246
VGG = VDS (V)
I
D
(mA)
20
0
16
12
8
4
MCD958
R
G1
= 68 kΩ
82 kΩ
100 kΩ
120 kΩ
150 kΩ
220 kΩ
180 kΩ
Fig.11 Drain current as a function of gate 1 (= VGG)
and drain supply voltage; typical values.
V
G2-S
=4V; Tj=25C.
R
G1
connected to VGG; see Fig.21.
handbook, halfpage
0246
16
12
4
0
8
MCD959
V
G2-S
(V)
I
D
(mA)
4.5 V
4 V
3 V
V
GG
= 5 V
3.5 V
VDS=5V; Tj=25C.
RG1=120k (connected to VGG); see Fig.21.
Fig.12 Drain current as a function of gate 2
voltage; typical values.
N-channel dual-gate PoLo MOS-FETs BF1202; BF1202R; BF1202WR
2010 Sep 16 6
Page 7
NXP Semiconductors Product specification
handbook, halfpage
0246
40
30
10
0
20
MCD960
V
G2-S
(V)
I
G1
(μA)
4 V
3.5 V
3 V
4.5 V
V
GG
= 5 V
Fig.13 Gate 1 current as a function of gate 2
voltage; typical values.
VDS=5V; Tj=25C.
RG1=120k (connected to VGG); see Fig.21.
handbook, halfpage
012 4
0
−50
−10
3
V
AGC
(V)
gain
reduction
(dB)
−20
−30
−40
MCD961
Fig.14 Typic al gain reduction as a function of the
AGC voltage; see Fig.21.
VDS=5V; VGG=5V; RG1= 120 k;
f = 50 MHz; T
amb
=25C.
handbook, halfpage
0
gain reduction (dB)
10 50
120
110
90
80
100
20 30 40
MCD962
V
unw
(dBμV)
Fig.15 Unwanted voltage for 1% cross-modulation
as a function of gain reduction; typical
values; Fig.21.
VDS=5V; VGG=5V; RG1= 120 k;
f= 50 MHz; f
unw
=60MHz; T
amb
=25C.
handbook, halfpage
0
gain reduction (dB)
10 50
16
12
4
0
8
20 30 40
MCD963
I
D
(mA)
Fig.16 Drain current as a function of gain
reduction; typical values; see Fig.21.
VDS=5V; VGG=5V; RG1= 120 k;
f = 50 MHz; T
amb
=25C.
N-channel dual-gate PoLo MOS-FETs BF1202; BF1202R; BF1202WR
2010 Sep 16 7
Page 8
NXP Semiconductors Product specification
handbook, halfpage
MCD964
10
f (GHz)
Y
is
(mS)
10
2
10
3
10
2
10
1
10
−1
b
is
g
is
Fig.17 Input admittance as a function of frequency;
typical values.
VDS=5V; VG2=4V.
ID=12mA; T
amb
=25C.
handbook, halfpage
MCD965
10
f (MHz)
10
2
10
3
10
3
10
2
10
1
−10
3
−10
2
−10
−1
y
rs
(μS)
ϕ
rs
(deg)
ϕ
rs
y
rs
Fig.18 Reverse transfer admittance and phase as
a function of frequency; typical values.
VDS=5V; VG2=4V.
ID=12mA; T
amb
=25C.
handbook, halfpage
10
2
10
1
−10
2
−10
−1
MCD966
10 10
2
10
3
f (MHz)
y
fs
(mS)
ϕ
fs
(deg)
y
fs
ϕ
fs
Fig.19 Forwa rd transfer admittance and phase as
a function of frequency; typical values.
VDS=5V; VG2=4V.
I
D
=12mA; T
amb
=25C.
handbook, halfpage
MCD967
10
b
os
f (MHz)
Y
os
(mS)
10
2
10
3
10
1
10
−2
10
−1
g
os
Fig.20 Output admittance as a function of
frequency; typical values.
VDS=5V; VG2=4V.
I
D
=12mA; T
amb
=25C.
N-channel dual-gate PoLo MOS-FETs BF1202; BF1202R; BF1202WR
2010 Sep 16 8
Page 9
NXP Semiconductors Product specification
handbook, full pagewidth
DUT
C1
4.7 nF
R1
10 kΩ
MGS315
C4
4.7 nF
L1
≈2.2 μH
C3
4.7 nF
R
L
50 Ω
V
GG
V
AGC
V
DS
R
GEN
50 Ω
V
I
R2
50 Ω
4.7 nF
C2
R
G1
Fig.21 Cross-modulation test set-up.
N-channel dual-gate PoLo MOS-FETs BF1202; BF1202R; BF1202WR
Table 1 Scattering parameters: VDS=5V; V
(MHz)
100 0.988 6.52 3.017 172.5 0.0009 88.0 0.995 3.01
1000 0.870 59.34 2.518 110.5 0.0038 72.4 0.970 27.90
Table 2 Noise data: V
f
s
MAGNITUDE
(ratio)
11
ANGLE
(deg)
G2-S
s
MAGNITUDE
(ratio)
=4V; ID=12mA; T
21
ANGLE
MAGNITUDE
(deg)
amb
(ratio)
=25C
s
12
ANGLE
(deg)
s
22
MAGNITUDE
(ratio)
ANGLE
(deg)
50 0.988 3.26 2.989 176.2 0.0005 92.6 0.995 1.50
200 0.984 12.99 2.990 165.0 0.0018 82.5 0.994 5.95
300 0.977 19.39 2.949 157.6 0.0027 78.2 0.992 8.86
400 0.965 25.65 2.913 150.3 0.0036 75.4 0.990 11.79
500 0.951 31.76 2.853 143.2 0.0039 71.8 0.988 14.65
600 0.936 37.68 2.793 136.3 0.0042 69.9 0.986 17.41
700 0.919 43.42 2.727 129.5 0.0044 68.9 0.984 20.10
800 0.903 48.94 2.664 123.0 0.0043 68.5 0.980 22.69
900 0.887 54.25 2.593 116.7 0.0041 70.7 0.975 25.27
f
(MHz)
=5V; V
DS
=4V; ID=12mA; T
G2-S
F
min
(dB)
=25C
amb
opt
(ratio) (deg)
R
()
n
400 0.9 0.805 28.5 50
800 1.1 0.725 47.2 40
2010 Sep 16 9
Page 10
NXP Semiconductors Product specification
UNIT
A
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC JEDEC JEITA
mm
1.1
0.9
A
1
max
0.1
b
1
0.88
0.78
c
0.15
0.09
D
3.0
2.8
E
1.4
1.2
H
E
ywvQ
2.5
2.1
0.45
0.15
0.55
0.45
e
1.9
e
1
1.7
L
p
0.1 0.10.2
b
p
0.48
0.38
DIMENSIONS (mm are the original dimensions)
SOT143B
04-11-16
06-03-16
0 1 2 mm
scale
Plastic surface-mounted package; 4 leads SOT143B
D
H
E
E
A
B
v M
A
X
A
A
1
L
p
Q
detail X
c
y
w M
e
1
e
B
21
34
b
1
b
p
N-channel dual-gate PoLo MOS-FETs BF1202; BF1202R; BF1202WR
PACKAGE OUTLINES
2010 Sep 16 10
Page 11
NXP Semiconductors Product specification
UNIT
A
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC JEDEC JEITA
mm
1.1
0.9
A
1
max
0.1
b
1
0.88
0.78
c
0.15
0.09
D
3.0
2.8
E
1.4
1.2
H
E
ywvQ
2.5
2.1
0.55
0.25
0.45
0.25
e
1.9
e
1
1.7
L
p
0.1 0.10.2
b
p
0.48
0.38
DIMENSIONS (mm are the original dimensions)
SOT143R SC-61AA
04-11-16
06-03-16
0 1 2 mm
scale
Plastic surface-mounted package; reverse pinning; 4 leads SOT143R
D
H
E
E
A
B
v M
A
X
A
A
1
L
p
Q
detail X
c
y
w M
e
1
e
B
12
43
b
1
b
p
N-channel dual-gate PoLo MOS-FETs BF1202; BF1202R; BF1202WR
2010 Sep 16 11
Page 12
NXP Semiconductors Product specification
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC JEDEC EIAJ
SOT343R
D
A
A
1
L
p
Q
detail X
c
H
E
E
v M
A
AB
0 1 2 mm
scale
X
21
43
Plastic surface-mounted package; reverse pinning; 4 leads SOT343R
w M
B
97-05-21
06-03-16
b
p
UNIT
A
1
max
b
p
cD
E
b
1
HEL
p
Qwv
mm
0.1
1.1
0.8
0.4
0.3
0.25
0.10
0.7
0.5
2.2
1.8
1.35
1.15
e
2.2
2.0
1.3
e
1
0.2y0.10.21.15
DIMENSIONS (mm are the original dimensions)
0.45
0.15
0.23
0.13
e
1
A
e
y
b
1
N-channel dual-gate PoLo MOS-FETs BF1202; BF1202R; BF1202WR
2010 Sep 16 12
Page 13
NXP Semiconductors Product specification
N-channel dual-gate PoLo MOS-FETs BF1202; BF1202R; BF1202WR
DATA SHEET STATUS
DOCUMENT
STATUS
Objective data sheet D evelopment This document contains data from the objective specification for product
Preliminary data sheet Qualification This document contains data from the preliminary specification.
Product data sheet Production This document contains the product specification.
Notes
1. Please consult the most recently issued document before initiating or completing a design.
2. The product status of device(s) desc ribed in this document may have changed since this document was published
and may differ in case of multiple devices. The latest product status information is available on the Internet at
URL http://www.nxp.com.
DISCLAIMERS
Limited warranty and liability Information in this
document is believed to be accurate and reliable.
However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to
the accuracy or completeness of such information and
shall have no liability for the consequences of use of such
information.
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indirect, incidental, punitive, special or consequential
damages (including - without limitation - lost profits, lost
savings, business interruption, costs related to the
removal or replacement of any products or rework
charges) whether or not such damages are based on tort
(including negligence), warranty, breach of contract or any
other legal theory.
Notwithstanding any damages that customer might incur
for any reason whatsoever, NXP Semiconductors’
aggregate and cumulative liability towards customer for
the products described herein shall be limited in
accordance with the Terms and conditions of commercial
sale of NXP Semiconductors.
Right to make changes NXP Semiconductors
reserves the right to make changes to information
published in this document, including without limitation
specifications and product descriptions, at any time and
without notice. This document supersedes and replaces all
information supplied prior to the publication hereof.
Suitability for use NXP Semiconductors products are
not designed, authorized or warranted to be su itable for
use in life support, life-critical or safety-critical systems or
equipment, nor in applications where failure or malfunction
of an NXP Semiconductors product can reasonably be
expected to result in personal injury, death or severe
(1)
PRODUCT
STATUS
(2)
DEFINITION
development.
property or environmental damage. NXP Semiconductors
accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or
applications and therefore such inc l usion and/or use is at
the customer’s own risk.
Applications Applications that ar e described herein for
any of these products are for illustrative purposes only.
NXP Semiconductors makes no representation or
warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of
their applications and products using NXP
Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or
customer product design. It is customer’s sole
responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the
customer’s applications and products planned, as well as
for the planned application and use of customer’s third
party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the ris ks
associated with their applications and products.
NXP Semiconductors does not acce pt a ny lia bil ity rela ted
to any default, damage, costs or problem which is based
on any weakness or default in the cu stomer’s applicat ions
or products, or the application or use by customer’s third
party customer(s). Customer is responsible for doing all
necessary testing for the customer’s applications and
products using NXP Semiconductors products in order to
avoid a default of the applications and the products or of
the application or use by customer’s third party
customer(s). NXP does not accept any liability in this
respect.
2010 Sep 16 13
Page 14
NXP Semiconductors Product specification
N-channel dual-gate PoLo MOS-FETs BF1202; BF1202R; BF1202WR
Limiting values Stress above one or more limiting
values (as defined in the Absolute Maximum Ratings
System of IEC 60134) will cause permanent damage to
the device. Limiting values are stress ratings only and
(proper) operation of the device at these or any other
conditions above those given in the Rec ommended
operating conditions section (if present) or the
Characteristics sections of this document is not warranted.
Constant or repeated exposure to limiting values will
permanently and irreversibly affect the quality and
reliability of the device.
Terms and conditions of commercial sale NXP
Semiconductors products are sold subject to the general
terms and conditions of commercial sale, as published at
http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In cas e an
individual agreement is concluded only the terms and
conditions of the respective agreement shall apply. NXP
Semiconductors hereby expressly objects to applying the
customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license Nothing in this document
may be interpreted or construed as an offer to sell products
that is open for acceptance or the grant, conveyance or
implication of any license under any copyrights, patents or
other industrial or intellectual property rights .
Export control This document as well as the item(s)
described herein may be subject to export control
regulations. Export might require a prior authorization from
national authorities.
Quick reference data The Quick reference data is an
extract of the product data given in t he Limiting values and
Characteristics sections of this document, and as such is
not complete, exhaustive or legally binding.
Non-automotive qualified products Unless this data
sheet expressly states that this specific NXP
Semiconductors product is automotive qualified, the
product is not suitable for automotive use. It is neither
qualified nor tested in accordance with auto motive testing
or application requirements. NXP Semiconductors accepts
no liability for inclusion and/or use of non-automotive
qualified products in automotive equipment or
applications.
In the event that customer uses the product for design-in
and use in automotive applications to automotive
specifications and standards, customer (a) shall use the
product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and
specifications, and (b) whenever customer uses the
product for automotive applications beyond NXP
Semiconductors’ specifications such use shall be solely at
customer’s own risk, and (c) customer fully indemnifies
NXP Semiconductors for any liability, damages or failed
product claims resulting from cus tom er d esign and use o f
the product for automotive applications beyond NXP
Semiconductors’ standard warranty and NXP
Semiconductors’ product specifications.
2010 Sep 16 14
Page 15
NXP Semiconductors
provides High Performance Mixed Signal and Standard Product
solutions that leverage its leading RF, Analog, Power Management,
Interface, Security and Digital Processing expertise
Customer notification
This data sheet was changed to reflect the new company name NXP Semiconductors, including new legal
definitions and disclaimers. No changes were made to the technical content, except for the marking codes
and the package outline drawings which were updated to the latest version.
Contact information
For additional information please visit: http://www.nxp.com
For sales offices addresses send e-mail to: [email protected]
© NXP B.V. 2010
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or cont ra ct, is b elieve d t o b e a ccur ate a nd re liable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property righ ts.
Printed in The Netherlands R77/03/pp15 Date of release: 2010 Sep 16
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