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Philips bf1109_r_wr Datasheet

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Page 1
DATA SH EET
DISCRETE SEMICONDUCTORS
BF1109; BF1109R; BF1109WR
N-channel dual-gate MOS-FETs
Product specification Supersedes data of 1997 Sep 03
1997 Dec 08
Page 2
NXP Semiconductors Product specification
Fig.1 Simplified outline
(SOT143B).
BF1109 marking code: NFp.
handbook, 2 columns
Top view
MSB014
12
34
Fig.2 Simplified outline
(SOT143R).
BF1109R marking code: NBp.
handbook, 2 columns
Top view MSB035
12
43
Fig.3 Simplified outline
(SOT343R).
BF1109WR marking code: NB.
Top view
MSB842
21
43
N-channel dual-gate MOS-FETs

FEATURES

Short channel transistor with high
forward transfer admittance to input capacitance ratio
Low noise gain controlled amplifier
up to 1 GHz
Internal self-biasing circuit to
ensure good cross-modulation performance during AGC and go od DC stabilization.

APPLICATIONS

VHF and UHF applications with 9 V
supply voltage, such as television tuners and professional communications equipment.

DESCRIPTION

PINNING

PIN DESCRIPTION
BF1109; BF1109R;
BF1109WR
1source 2drain 3 gate 2 4 gate 1
Enhancement type N-channel field-effect transistor with source and substrate interconnected. Integrated diodes between gates and source protect against excessive input voltage surges. The BF1109, BF1109R and BF1109WR are encapsulated in the SOT143B, SOT143R and SOT343R plastic packages respectively.

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V
DS
I
D
P
tot
forward transfer admittance 30 mS
y
fs
C
ig1-ss
C
rss
drain-source voltage 11 V drain current (DC) 30 mA total power dissipation T
80 C 200 mW
amb
input capacitance at gate 1 2.2 2.7 pF
reverse transfer capacitance f = 1 MHz 25 40 fF F noise figure f = 800 MHz 1.5 2.5 dB X
mod
T
j
cross-modulation input level for k = 1% at 40 dB AGC 100 dBV
operating junction temperature 150 C
This product is supplied in anti-static packing to prevent damage caused by electrostatic discharge during transport and handling.
CAUTION
Page 3
NXP Semiconductors Product specification
Fig.4 Power derating curve.
handbook, halfpage
0 40 80 160
250
0
200
MGM243
120
150
100
50
P
tot
(mW)
T
amb
(°C)
N-channel dual-gate MOS-FETs BF1109; BF1109R; BF1109WR

LIMITING VALUES

In accordance with the Absolu te Maximum Rating System (IEC 1 34).
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
DS
I
D
I
G1
I
G2
P
tot
T
stg
T
j
Note
1. Device mounted on a printed-circuit board.
drain-source voltage 11 V
drain current (DC) 30 mA
gate 1 current 10 mA
gate 2 current 10 mA
total power dissipation T
80 C; note 1 200 mW
amb
storage temperature 65 +150 C
operating junction temperature +150 C
Page 4
NXP Semiconductors Product specification
N-channel dual-gate MOS-FETs BF1109; BF1109R; BF1109WR

THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS VALUE UNIT
R
th j-a
R
th j-s
Note
1. Device mounted on a printed-circuit board.

STATIC CHARACTERISTICS

T
=25C unless otherwise specified.
j
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
(BR)DSS
V
(BR)G1-SS
V
(BR)G2-SS
V
G2-S (th)
I
DSX
I
G1-SS
I
G2-SS
thermal resistance from junction to ambient in free air note 1 350 K/W
thermal resistance from junction to soldering point 200 K/W
drain-source breakdown voltage V
gate 1-source breakdown voltage V
gate 2-source breakdown voltage V
gate 2-source threshold voltage V
self-biasing drain current V
gate 1 cut-off current V
gate 2 cut-off current V
G1-S=VG2-S
=0; I
G2-S G1-S=VDS
=9V; VDS=9V; ID=20A0.31.2V
G1-S
=4V; VDS=9V 8 16 mA
G2-S
=9V; V
G1-S G1-S=VDS
=0; ID=10A11 V
=10A; ID=0 11 V
G1-S
=0; I
G2-S
=0; V
=10A11 V
G2-S
=0; ID=0 20 nA
=9V 20 nA
G2-S

DYNAMIC CHARACTERISTICS

Common source; T
=25C; V
amb
=4V; VDS= 9 V; self-biasing current; unless otherwise specified.
G2-S
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
y
forward transfer admittance pulsed; Tj=25C2430 mS
fs
C
ig1-ss
C
ig2-ss
C
oss
C
rss
F noise figure f = 800 MHz; Y G
p
X
mod
input capacitance at gate 1 f = 1 MHz 2.2 2.7 pF
input capacitance at gate 2 f = 1 MHz 1.5 pF
output capacitance f = 1 MHz 1.3 pF
reverse transfer capacitance f = 1 MHz 25 40 fF
S=YSopt
power gain GS=2mS; BS=B
B
L=BLopt
G
S
B
L=BLopt
; f = 200 MHz; see Fig.16
=3.3mS; BS=B
; f = 800 MHz; see Fig.17
; GL= 0.5 mS;
Sopt
; GL=1mS;
Sopt
cross-modulation input level for k = 1% at 0dB AGC;
=50MHz; f
f
w
=60MHz; seeFig.18
unw
input level for k = 1% at 40 dB AGC; f
=50MHz; f
w
=60MHz; seeFig.18
unw
1.5 2.5 dB 38 dB
20 dB
85 dBV
100 dBV
Page 5
NXP Semiconductors Product specification
Fig.5 Output characteristics; typical values.
V
G2-S
=4V.
Tj=25C.
handbook, halfpage
010
25
0
5
10
15
20
2468
MDA613
I
D
(mA)
VDS (V)
V
G1
= 1.6 V
1.3 V
1.2 V
1.1 V
1.5 V
1.4 V
1 V
Fig.6 Transfer characteristics; typical values.
VDS=9V. Tj=25C.
handbook, halfpage
0
40
20
30
10
0
0.5 2.5
MDA614
1 1.5 2
VG1 (V)
I
D
(mA)
2 V
1 V
V
G2-S
= 4 V
3.5 V
2.5 V
1.5 V
3 V
Fig.7 Forward transfer admittance as a function
of drain current; typical values.
VDS=9V. T
j
=25C.
handbook, halfpage
0 102030
40
30
10
0
20
MDA615
I
D (mA)
y
fs
(mS)
3.5 V
3 V
2.5 V
2 V
V
G2-S
= 4 V
Fig.8 Drain current as a function of gate 2
voltage; typical values.
(1) VDS=9V. (2) V
DS
=7V.
(3) V
DS
=5V.
(4) V
DS
=3V.
handbook, halfpage
0
16
8
12
4
0
15
MDA616
234
I
D
(mA)
V
G2-S
(V)
(1)
(4)
(3)
(2)
N-channel dual-gate MOS-FETs BF1109; BF1109R; BF1109WR
Page 6
NXP Semiconductors Product specification
Fig.9 Drain current as a function of drain-source
voltage; typical values.
V
G2-S
=4V.
Tj=25C.
handbook, halfpage
02 10
16
12
4
0
8
46 8
MDA617
I
D
(mA)
VDS (V)
Fig.10 Drain current as a function of gate 1 current;
typical values.
VDS=9V; V
G2-S
=4V; Tj=25C.
handbook, halfpage
−8 −6 −40
MDA618
−2
16
8
12
4
0
I
D
(mA)
IG1 (μA)
VDS=9V; V
G2nom
=4V; I
Dnom
=12mA; fw=50MHz;
f
unw
=60MHz; T
amb
=25C.
Fig.11 Unwanted voltage for 1% cross-modulation
as a function of gain reduction; typical values (see Fig.18).
handbook, halfpage
020
V
unw
(dBμV)
gain reduction (dB)
40 60
120
110
90
80
100
MDA619
N-channel dual-gate MOS-FETs BF1109; BF1109R; BF1109WR
Page 7
NXP Semiconductors Product specification
Fig.12 Input admittance as a function of frequency;
typical values.
VDS=9V; V
G2-S
=4V.
ID=12mA; T
amb
=25C.
handbook, halfpage
MDA620
10
2
10
−2
10
10
2
10
3
10
−1
1
10
f (MHz)
y
is
(mS)
g
is
b
is
Fig.13 Reverse transfer admittance and phase as
a function of frequency; typical values.
VDS=9V; V
G2-S
=4V.
ID=12mA; T
amb
=25C.
handbook, halfpage
MDA621
10
3
10
2
10
1
10
10
2
10
3
f (MHz)
|yrs|
(mS)
ϕ
rs
(deg)
−10
3
−1
−10
−10
2
ϕ
rs
|yrs|
Fig.14 Forward transfer admittance and phase as
a function of frequency; typical values.
VDS=9V; V
G2-S
=4V.
I
D
=12mA; T
amb
=25C.
handbook, halfpage
MDA622
10
2
ϕ
fs
(deg)
−10
2
−1
−10
10
1
10 10
2
10
3
f (MHz)
|yfs|
(mS)
ϕ
fs
|yfs|
Fig.15 Output admittance as a function of
frequency; typical values.
VDS=9V; V
G2-S
=4V.
I
D
=12mA; T
amb
=25C.
handbook, halfpage
MDA623
10
1
10
−1
10
−2
10
10
2
10
3
f (MHz)
y
os
(mS)
b
os
g
os
N-channel dual-gate MOS-FETs BF1109; BF1109R; BF1109WR
Page 8
NXP Semiconductors Product specification
Fig.16 Gain test circuit.
VDS=9V, GS=2mS, GL= 0.5 mS, f = 200 MHz. L1 = 45 nH, 4 turns, internal diameter = 4 mm, 0.8 mm copper wire. L2 = 160 nH, 3 turns, internal diameter = 8 mm, 0.8 mm copper wire; tapped at approximately half a turn from the cold side, to set GL=0.5mS. C1 adjusted for GS=2mS.
handbook, full pagewidth
BF1109
BF1109R
BF1109WR
MDA624
330 kΩ
47 kΩ
15 pF
5.5 pF
C1
1 nF
1 nF
1 nF
1 nF
1 nF
1 nF
V
AGC
V
DS
G1
G2
S
D
1 nF
330 kΩ
1 nF
BB405
10 pF
BB405
input 50 Ω
V
tun
input
output
50 Ω
V
tun
output
L2
L1
2 μH
Fig.17 Gain test circuit.
VDS=9V, GS=3.3mS, GL=1mS, f=800MHz. L1 = 2 cm, silvered 0.8 mm copper wire 4 mm above ground plane. L2 = 2 cm, silvered 0.8 mm copper wire 4 mm above ground plane. L3 = 11 turns 0.5 mm copper wire without spacing, internal diameter = 3 mm, L = approx. 200nH.
handbook, full pagewidth
input 50 Ω
output
50 Ω
BF1109
BF1109R
BF1109WR
MDA625
47 kΩ
0.5 to 3.5 pF
1 nF
L3
L2
L1
1 nF
1 nF
1 nF
V
AGC
V
DS
G1
G2
S
D
2 to 18 pF
4 to 40 pF
0.5 to 3.5 pF
1 nF
N-channel dual-gate MOS-FETs BF1109; BF1109R; BF1109WR
Page 9
NXP Semiconductors Product specification
Fig.18 Cross-modulation test set-up.
handbook, full pagewidth
BF1109
BF1109R
BF1109WR
MDA626
R
gen
50 Ω
50 Ω
R1 = 50 Ω
10 kΩ
G2
G1
D
S
10 nF
V
i
10 nF
4.7 nF
47 μH
4.7 nF
V
G2
V
DS
N-channel dual-gate MOS-FETs BF1109; BF1109R; BF1109WR
Table 1 Scattering parameters: VDS=9V; V
(MHz)
1000 0.852 64.3 2.457 89.6 0.004 129.7 0.9377 33.1
Table 2 Noise data: V
=4V; ID=12mA
G2-S
f
S
MAGNITUDE
(ratio)
11
ANGLE
(deg)
MAGNITUDE
(ratio)
S
21
ANGLE
MAGNITUDE
(deg)
(ratio)
S
12
ANGLE
MAGNITUDE
(deg)
(ratio)
S
22
ANGLE
(deg)
50 0.995 3.71 3.013 175.0 0.000 88.2 0.998 1.8 100 0.992 7.29 3.002 170.2 0.001 83.7 0.997 3.5 200 0.984 14.3 2.967 160.7 0.002 86.2 0.995 7.0 300 0.973 21.2 2.922 151.3 0.002 83.2 0.992 10.5 400 0.961 27.9 2.869 142.0 0.003 84.1 0.990 13.9 500 0.944 34.4 2.793 132.9 0.003 85.7 0.987 17.2 600 0.926 40.8 2.730 124.1 0.003 88.4 0.985 20.5 700 0.906 46.9 2.660 1115.3 0.003 94.6 0.983 23.7 800 0.887 52.9 2.605 106.5 0.004 107.2 0.981 26.8 900 0.868 58.8 2.527 97.8 0.004 1 1 4.9 0.977 30.0
=9V; V
DS
f
(MHz)
800 1.5 0.684 40.94 40.4
=4V; ID=12mA
G2-S
F
min
(dB)
(ratio) (deg)
opt
R
()
n
Page 10
NXP Semiconductors Product specification
UNIT
A
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC JEDEC JEITA
mm
1.1
0.9
A
1
max
0.1
b
1
0.88
0.78
c
0.15
0.09
D
3.0
2.8
E
1.4
1.2
H
E
ywvQ
2.5
2.1
0.45
0.15
0.55
0.45
e
1.9
e
1
1.7
L
p
0.1 0.10.2
b
p
0.48
0.38
DIMENSIONS (mm are the original dimensions)
SOT143B
04-11-16 06-03-16
0 1 2 mm
scale
Plastic surface-mounted package; 4 leads SOT143B
D
H
E
E
A
B
v M
A
X
A
A
1
L
p
Q
detail X
c
y
w M
e
1
e
B
21
34
b
1
b
p
N-channel dual-gate MOS-FETs BF1109; BF1109R; BF1109WR

PACKAGE OUTLINES

Page 11
NXP Semiconductors Product specification
UNIT
A
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC JEDEC JEITA
mm
1.1
0.9
A
1
max
0.1
b
1
0.88
0.78
c
0.15
0.09
D
3.0
2.8
E
1.4
1.2
H
E
ywvQ
2.5
2.1
0.55
0.25
0.45
0.25
e
1.9
e
1
1.7
L
p
0.1 0.10.2
b
p
0.48
0.38
DIMENSIONS (mm are the original dimensions)
SOT143R SC-61AA
04-11-16 06-03-16
0 1 2 mm
scale
Plastic surface-mounted package; reverse pinning; 4 leads SOT143R
D
H
E
E
A
B
v M
A
X
A
A
1
L
p
Q
detail X
c
y
w M
e
1
e
B
12
43
b
1
b
p
N-channel dual-gate MOS-FETs BF1109; BF1109R; BF1109WR
Page 12
NXP Semiconductors Product specification
REFERENCES
OUTLINE VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC JEDEC EIAJ
SOT343R
D
A
A
1
L
p
Q
detail X
c
H
E
E
v M
A
AB
0 1 2 mm
scale
X
21
43
Plastic surface-mounted package; reverse pinning; 4 leads SOT343R
w M
B
97-05-21 06-03-16
b
p
UNIT
A
1
max
b
p
cD
E
b
1
HEL
p
Qwv
mm
0.1
1.1
0.8
0.4
0.3
0.25
0.10
0.7
0.5
2.2
1.8
1.35
1.15
e
2.2
2.0
1.3
e
1
0.2y0.10.21.15
DIMENSIONS (mm are the original dimensions)
0.45
0.15
0.23
0.13
e
1
A
e
y
b
1
N-channel dual-gate MOS-FETs BF1109; BF1109R; BF1109WR
Page 13
NXP Semiconductors Product specification
N-channel dual-gate MOS-FETs BF1109; BF1109R; BF1109WR

DATA SHEET STATUS

DOCUMENT
STATUS
Objective data sheet Development T his doc ument contains data from the objective specification for product
Preliminary data sheet Qualification This document contains data from the preliminary specification. Product data sheet Production This document co ntains the pr oduct specification.
Notes
1. Please consult the most recently issued document before initiating or co mpleting a design.
2. The product status of device(s) described in this document may have changed sinc e this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
DEFINITIONS Product specification The information and data
provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.
DISCLAIMERS Limited warranty and liability Information in this
document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors.
(1)
PRODUCT STATUS
(2)
DEFINITION
development.
Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication he reof.
Suitability for use NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications wher e failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inc l usion and/or use is at the customer’s own risk.
Applications Applications that ar e described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the ris ks associated with their applications and products.
Page 14
NXP Semiconductors Product specification
N-channel dual-gate MOS-FETs BF1109; BF1109R; BF1109WR
NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applicat ions and products using NXP Semiconductors products in or de r to avoid a default of the applications and the prod ucts or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect.
Limiting values Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Rec ommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device.
Terms and conditions of commercial sale NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In cas e an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer.
Export control This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities.
Quick reference data The Quick reference data is an extract of the product data given in t he Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding.
Non-automotive qualified products Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with auto motive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from cus tom er d esign and use o f the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications.
No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights .
Page 15
NXP Semiconductors
provides High Performance Mixed Signal and Standard Product solutions that leverage its leading RF, Analog, Power Management, Interface, Security and Digital Processing expertise
Customer notification
This data sheet was changed to reflect the new company name NXP Semiconductors, including new legal definitions and disclaimers. No changes were made to the technical content, except for package outline drawings which were updated to the latest version.
Contact information
For additional information please visit: http://www.nxp.com For sales offices addresses send e-mail to: [email protected]
© NXP B.V. 2010 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contra ct, is b elieve d t o b e a ccur ate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property righ ts.
Printed in The Netherlands R77/02/pp15 Date of release: 1997 Dec 08
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