Philips bf1102_r Datasheet

DATA SH EET

DISCRETE SEMICONDUCTORS

MBD128

BF1102; BF1102R

Dual N-channel dual gate
MOS-FETs

Product specification
Supersedes data of 1999 Jul 01

2000 Apr 11

NXP Semiconductors Product specification

handbook, halfpage

MBL029

AMP1 d (1)g1 (1)

d (2)g1 (2)

AMP2

g2 (1, 2)

s (1, 2)

132

4

56

Fig.1 Simplified outline and symbol.

BF1102 marking code: W1.
BF1102R marking code: W2-.

Dual N-channel dual gate MOS-FETs BF1102; BF1102R

FEATURES

 Two low noise gain controlled amplifiers in a single

package

 Specially designed for 5 V applications
 Superior cross-modulation performance during AGC
 High forward transfer admittance
 High forward transfer admittance to input capacitance

ratio.

APPLICATIONS

Gain controlled low noise amplifier for VHF and UHF
applications such as television tuners and professional
communications equipment.

DESCRIPTION

The BF1102 and BF1102R are both two equal dual gate
MOS-FETs which have a shared source pin and a shared
gate 2 pin. Both devices have interconnected source and
substrate; an internal bias circuit enables DC stabilization
and a very good cross-modulation performance at 5 V
supply voltage; integrated diodes between the gates and
source protect against excessive input vo ltage surges.
Both devices have a SOT363 micro-miniature plastic
package.

PINNING - SOT363

DESCRIPTION

PIN

BF1102 BF1102R

1 gate 1 (1) gate 1 (1)
2 gate 2 (1 and 2) source (1 and 2)
3 drain (1) drain (1)
4 drain (2) drain (2)
5 source (1 and 2) gate 2 (1 and 2)
6 gate 1 (2) gate 1 (2)

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Per MOS-FET unless otherwise specified

V

DS

I

D

P

tot

 forward transfer admittance ID=15mA 36 43  mS

y

fs

C

ig1-s

C

rss

drain-source voltage 7V
drain current (DC) 40 mA
total power dissipation Ts 102 C; note 1 200 mW

input capacitance at gate 1 ID=15mA  2.8 3.6 pF

reverse transfer capacitance f = 1 MHz  30 50 fF
F noise figure f = 800 MHz  22.8dB
X

mod

T

j

cross-modulation input level for k = 1% at 40 dB AGC 100 dBV

operating junction temperature 150 C

Note

is the temperature at the soldering point of the source lead.

1. T

s

CAUTION

This product is supplied in anti-static packing to prevent damage caused by electrostatic discharge during transport
and handling.

2000 Apr 11 2

NXP Semiconductors Product specification

handbook, halfpage

0 50 100 200

250

0

200

MGS359

150

150

100

50

Ts (°C)

P

tot

(mW)

Fig.2 Power derating curve.

Dual N-channel dual gate MOS-FETs BF1102; BF1102R

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 60134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

Per MOS-FET unless otherwise specified

V

DS

I

D

I

G1

I

G2

P

tot

T

stg

T

j

THERMAL CHARACTERISTICS

SYMBOL PARAMETER VALUE UNIT

R

th j-s

drain-source voltage  7V
drain current (DC)  40 mA
gate 1 current 10 mA
gate 2 current 10 mA
total power dissipation Ts 102 C  200 mW
storage temperature 65 +150 C
operating junction temperature  150 C

thermal resistance from junction to soldering point 240 K/W

2000 Apr 11 3

NXP Semiconductors Product specification

Dual N-channel dual gate MOS-FETs BF1102; BF1102R

STATIC CHARACTERISTICS

T

=25C unless otherwise specified.

j

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

Per MOS-FET unless otherwise specified

V

(BR)DSS

V

(BR)G1-SS

V

(BR)G2-SS

V

(F)S-G1

V

(F)S-G2

V

G1-S(th)

V

G2-S(th)

I

DSX

I

G1-S

I

G2-S

drain-source breakdown voltage V

G1-S=VG2-S

gate 1-source breakdown voltage VGS=VDS=0; I

gate 2-source breakdown voltage VGS=VDS=0; I

forward source-gate 1 voltage V

forward source-gate 2 voltage V

G2-S=VDS
G1-S=VDS

gate 1-source threshold voltage VDS=5V; V

gate 2-source threshold voltage VDS=5V; V

drain-source current V

gate 1 cut-off current V

gate 2 cut-off current V

=4V; VDS=5V; RG= 120 k; note 1 12 20 mA

G2-S

=5V; V

G1-S

=5V; V

G2-S

=0; ID=10A7 V

=10mA 6 15 V

G1-S

=5mA 6 15 V

G2-S

=0; I
=0; I

G2-S
G1-S

G2-S=VDS
G1-S=VDS

=10mA 0.5 1.5 V

S-G1

=10mA 0.5 1.5 V

S-G2

=4V; ID=100A0.31V
=4V; ID=100A0.31.2V

=0  50 nA
=0  20 nA

Note

1. R

connects gate 1 to VGG=5V.

G1

DYNAMIC CHARACTERISTICS

Common source; T

=25C; V

amb

=4V; VDS=5V; ID= 15 mA; unless otherwise specified.

G2-S

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Per MOS-FET unless otherwise specified (note 1)

 forward transfer admittance Tj=25C 364350mS

y

fs

C

ig1-ss

C

ig2-ss

C

oss

C

rss

F noise figure f = 800 MHz; Y
X

mod

input capacitance at gate 1 f = 1 MHz 2 2.8 3.6 pF

input capacitance at gate 2 f = 1 MHz; (note 2) 7pF

output capacitance f = 1 MHz  1.6 2.5 pF

reverse transfer capacitance f = 1 MHz  30 50 fF

 22.8dB

cross-modulation fw=50MHz; f

S=YSopt

=60MHz; (note3)

unw

input level for k = 1% at 0 dB AGC 85 dBV
input level for k = 1% at 40 dB AGC 100 dBV

Notes

1. Not used MOS-FET: V

=0; VDS=0.

G1-S

2. Gate 2 capacitance of both MOS-FETs.

3. Measured in test circuit of Fig.20.

2000 Apr 11 4

NXP Semiconductors Product specification

handbook, halfpage

0

30

20

10

0

0.80.4 2.42.01.61.2

MGS360

V

G1-S

(V)

2.5 V

2 V

1.5 V

1 V

3.5 V
3 V

V

G2-S

= 4 V

I

D

(mA)

Fig.3 Transfer characteristics; typical values.

VDS=5V.
Tj=25C.

handbook, halfpage

010

30

10

0

20

MGS361

2468

VDS (V)

I

D

(mA)

1.4 V

1.3 V

1.2 V

1.1 V

1 V

V

G1-S

= 1.5 V

Fig.4 Output characteristics; typical values.

V

G2-S

=4V.

Tj=25C.

handbook, halfpage

0

160

80

120

40

0

0.5 2.5

MGS362

1 1.5 2

I

G1

(μA)

V

G1-S

(V)

2.5 V

2 V

3.5 V

3 V

V

G2-S

= 4 V

Fig.5 Gate 1 current as a function of gate 1

voltage; typical values.

VDS=5V.
Tj=25C.

handbook, halfpage

010 30

50

0

40

MGS363

20

30

20

10

ID (mA)

|yfs|

(mS)

3.5 V

3 V

V

G2-S

= 4 V

2.5 V

2 V

Fig.6 Forward transfer admittance as a function

of drain current; typical values.

VDS=5V.
Tj=25C.

Dual N-channel dual gate MOS-FETs BF1102; BF1102R

ALL GRAPHS FOR ONE MOS-FET

2000 Apr 11 5

NXP Semiconductors Product specification

handbook, halfpage

020 60

25

0

5

20

15

10

MGS364

40

I

D

(mA)

IG1 (μA)

Fig.7 Drain current as a function of gate 1 current;

typical values.

VDS=5V; V

G2-S

=4V; Tj=25C.

handbook, halfpage

0

15

10

5

0

1

MGS365

23 54

I

D

(mA)

VGG (V)

Fig.8 Drain current as a function of gate 1 supply

voltage (= V

GG

); typical values.

VDS=5V; V

G2-S

=4V; Tj=25C.

RG1=120k (connected to VGG); see Fig.20.

handbook, halfpage

010

30

0

10

20

MGS366

2468

I

D

(mA)

VGG = VDS (V)

RG1 = 47 kΩ

68 kΩ

82 kΩ
100 kΩ

120 kΩ
150 kΩ
180 kΩ

220 kΩ

Fig.9 Drain current as a function of gate 1 (= VGG)

and drain supply voltage; typical values.

V

G2-S

=4V; Tj=25C.

R

G1

connected to VGG; see Fig.20.

handbook, halfpage

02 6

20

0

16

MGS367

4

12

8

4

V

G2-S

(V)

I

D

(mA)

4.5 V
4 V

3.5 V
3 V

V

G1-S

= 5 V

VDS=5V; Tj=25C.
R

G1

=120k (connected to VGG); see Fig.20.

Fig.10 Drain current as a function of gate 2

voltage; typical values.

Dual N-channel dual gate MOS-FETs BF1102; BF1102R

2000 Apr 11 6

NXP Semiconductors Product specification

handbook, halfpage

0

40

20

30

10

0

MGS368

264

I

G1

(μA)

V

G2-S

(V)

4.5 V
4 V

3.5 V
3 V

V

G1-S

= 5 V

Fig.11 Gate 1 current as a function of gate 2

voltage; typical values.

VDS=5V; Tj=25C.
RG1=120k (connected to VGG); see Fig.20.

handbook, halfpage

012 4

0

−50

−10

3

V

AGC

(V)

gain

reduction

(dB)

−20

−30

−40

MCD968

Fig.12 Typic al gain reduction as a function of the

AGC voltage; see Fig.20.

VDS=5V; VGG= 5 V; f = 50 MHz; T

amb

=25C;

RG1=120k (connected to VGG); see Fig.20.

handbook, halfpage

020 60

120

110

90

80

100

40

MGS369

V

unw

(dBμV)

gain reduction (dB)

Fig.13 Unwanted voltage for 1% cross-modulation

as a function of gain reduction;
typical values.

VDS=5V; VGG=5V; fw=50MHz; f

unw

=60MHz; T

amb

=25C;

RG1=120k (connected to VGG); see Fig.20.

handbook, halfpage

050

20

0

4

8

12

16

10 20 30 40

gain reduction (dB)

I

D

(mA)

MCD969

Fig.14 Drain current as a function of gain

reduction; typical values.

VDS=5V; VGG= 5 V; f = 50 MHz; T

amb

=25C;

RG1=120k (connected to VGG); see Fig.20.

Dual N-channel dual gate MOS-FETs BF1102; BF1102R

2000 Apr 11 7

NXP Semiconductors Product specification

handbook, halfpage

MGS370

10

2

10

1

10

−1

10 10

2

10

3

f (MHz)

y

is

(mS)

b

is

g

is

Fig.15 Input admittance as a function of frequency;

typical values.

VDS=5V; VG2=4V.
ID=15mA; T

amb

=25C.

handbook, halfpage

MCD970

10

f (MHz)

10

2

10

3

10

3

10

2

10

1

−10

3

−10

2

−10

−1

ϕ

rs

(deg)

ϕ

rs

y

rs

(mS)

y

rs

Fig.16 Reverse transfer admittance and phase as

a function of frequency; typical values.

VDS=5V; VG2=4V.
ID=15mA; T

amb

=25C.

handbook, halfpage

MGS372

10

2

−ϕ

fs

(deg)

10

2

1

10

10

1

10 10

2

10

3

f (MHz)

|yfs|

(mS)

ϕ

fs

|yfs|

Fig.17 Forwa rd transfer admittance and phase as

a function of frequency; typical values.

VDS=5V; VG2=4V.
I

D

=15mA; T

amb

=25C.

handbook, halfpage

10

10

−1

1

MCD971

10 10

2

10

3

f (MHz)

y

os

(mS)

g

os

b

os

Fig.18 Output admittance as a function of

frequency; typical values.

VDS=5V; VG2=4V.
ID=15mA; T

amb

=25C.

Dual N-channel dual gate MOS-FETs BF1102; BF1102R

2000 Apr 11 8

NXP Semiconductors Product specification

handbook, halfpage

0

f (MHz)

200 1000

0

−20

−60

−80

−40

400 600 800

MCD972

crosstalk

level

(dB)

Fig.19 Crosstalk as a function of frequency:

Output level of non-active amplifier related
to output level of active amplifier; typical
values.

Active amplifier: VDS=5V; VG2=4V; ID=15mA.
Non-active amplifier: VDS=V

G1-S

=0V.
Source and load impedances: 50 (both amplifiers).
T

amb

=25C.

handbook, full pagewidth

DUT

C1

4.7 nF

R1

10 kΩ

MGS315

C4

4.7 nF

L1

≈2.2 μH

C3

4.7 nF

R

L

50 Ω

V

GG

V

AGC

V

DS

R

GEN
50 Ω

V

I

R2

50 Ω

4.7 nF

C2

R

G1

Fig.20 Cross-modulation test set-up (for one MOS-FET).

Dual N-channel dual gate MOS-FETs BF1102; BF1102R

2000 Apr 11 9

NXP Semiconductors Product specification

Dual N-channel dual gate MOS-FETs BF1102; BF1102R

Table 1 Scattering parameters: VDS=5V; V

s

f

(MHz)

MAGNITUDE

(ratio)

11

ANGLE

(deg)

MAGNITUDE

(ratio)

=4V; ID=15mA; T

G2-S

s

21

ANGLE

(deg)

=25C

amb

s

MAGNITUDE

(ratio)

12

ANGLE

(deg)

s

22

MAGNITUDE

(ratio)

ANGLE

(deg)

50 0.987 5.6 4.069 173.5 0.001 95.4 0.986 3.0

100 0.981 11.1 4.042 167.0 0.002 81.3 0.983 6.0

200 0.961 21.9 3.926 154.4 0.005 75.8 0.976 12.0
300 0.933 32.1 3.778 142.4 0.006 69.6 0.960 17.7
400 0.899 42.0 3.593 130.6 0.007 65.6 0.945 23.2
500 0.867 51.1 3.412 119.6 0.007 64.4 0.928 29.1
600 0.834 59.9 3.216 109.2 0.007 67.5 0.914 34.1
700 0.805 67.9 3.010 99.0 0.006 78.7 0.901 39.8
800 0.779 75.7 2.804 89.2 0.007 92.7 0.886 45.1
900 0.758 82.1 2.656 80.3 0.007 120.7 0.889 49.7

1000 0.740 89.0 2.509 69.9 0.009 125.5 0.890 55.7

Table 2 Noise data: V

f

(MHz)

=5V; V

DS

=4V; ID=15mA; T

G2-S

F

min

(dB)

=25C

amb



opt

(ratio) (deg)

R

()

n

800 2 0.621 61.61 25.85

2000 Apr 11 10

NXP Semiconductors Product specification

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC JEITA

SOT363 SC-88

wBM

b

p

D

e

1

e

pin 1
index

A

A

1

L

p

Q

detail X

H

E

E

v M

A

AB

y

0 1 2 mm

scale

c

X

132

456

Plastic surface-mounted package; 6 leads SOT363

UNIT

A

1

max

b

p

cD

E

e

1

H

E

L

p

Qywv

mm

0.1

0.30

0.20

2.2

1.8

0.25

0.10

1.35

1.15

0.65

e

1.3

2.2

2.0

0.2 0.10.2

DIMENSIONS (mm are the original dimensions)

0.45

0.15

0.25

0.15

A

1.1

0.8

04-11-08
06-03-16

Dual N-channel dual gate MOS-FETs BF1102; BF1102R

PACKAGE OUTLINE

2000 Apr 11 11

NXP Semiconductors Product specification

Dual N-channel dual gate MOS-FETs BF1102; BF1102R

DATA SHEET STATUS

DOCUMENT

STATUS

Objective data sheet Development This document co ntains data from the objective s pecification for product

Preliminary data sheet Qualification This document contains data from the preliminary specification.
Product data sheet Production This document contains the prod uc t specification.

Notes

1. Please consult the most recently issued document before initiating or co mpleting a design.

2. The product status of device(s) described in this document may have changed since this document was published
and may differ in case of multiple devices. The latest product status information is available on the Internet at
URL http://www.nxp.com.

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provided in a Product data sheet shall define the
specification of the product as agreed between NXP
Semiconductors and its customer, unless NXP
Semiconductors and customer have explicitly agreed
otherwise in writing. In no event however, shall an
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product is deemed to offer functions and qualities beyond
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(1)

PRODUCT

STATUS

(2)

DEFINITION

development.

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reserves the right to make changes to information
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NXP Semiconductors makes no representation or
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Customers are responsible for the design and operation of
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Semiconductors product is suitable and fit for the
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party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the ris ks
associated with their applications and products.

2000 Apr 11 12

NXP Semiconductors Product specification

Dual N-channel dual gate MOS-FETs BF1102; BF1102R

NXP Semiconductors does not accept any liability related
to any default, damage, costs or problem which is based
on any weakness or default in the customer’s applications
or products, or the application or use by customer’s third
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values (as defined in the Absolute Maximum Ratings
System of IEC 60134) will cause permanent damage to
the device. Limiting values are stress ratings only and
(proper) operation of the device at these or any other
conditions above those given in the Rec ommended
operating conditions section (if present) or the
Characteristics sections of this document is not warranted.
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Quick reference data  The Quick reference data is an
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Characteristics sections of this document, and as such is
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2000 Apr 11 13

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definitions and disclaimers. No changes were made to the technical content, except for package outline
drawings which were updated to the latest version.

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Printed in The Netherlands R77/03/pp14 Date of release: 2000 Apr 11