Philips BF1102 Datasheet
DISCRETE SEMICONDUCTORS
MBD128
DATA SHEET
BF1102
Dual N-channel dual gate MOS-FET
Preliminary specification 1999 Jul 08
Philips Semiconductors Preliminary specification
Dual N-channel dual gate MOS-FET BF1102
FEATURES
• Two low noise gain controlled amplifiers in a single
package
• Specially designed for 5 V applications
• Superior cross-modulation performance during AGC
• High forward transfer admittance
• High forward transfer admittance to input capacitance
ratio.
APPLICATIONS
• Gain controlled low noise amplifier for VHF and UHF
applications such as television tuners and professional
communications equipment.
DESCRIPTION
The BF1102 is a combination of two equal dual gate
MOS-FETs with shared source and gate 2 leads.
The source and substrate are interconnected. An internal
bias circuit enables DC stabilization and a very good
cross-modulation performance at 5 V supply voltage.
Integrated diodes between the gates and source protect
against excessive input voltage surges. The transistor has
a SOT363 micro-miniature plastic package.
PINNING - SOT363
PIN DESCRIPTION
1 gate 1 (1)
2 gate 2 (1,2)
3drain(1)
4drain(2)
5 source (1,2)
6 gate 1 (2)
handbook, halfpage
56
4
132
Marking code: W1.
Fig.1 Simplified outline and symbol.
g2 (1, 2)
AMP2
s (1, 2)
AMP1 d (1)g1 (1)
d (2)g1 (2)
MBL029
QUICK REFERENCE DATA
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Per MOS-FET unless otherwise specified
V
DS
I
D
P
tot
y
forward transfer admittance ID=15mA − 43 − mS
fs
C
ig1-s
C
rss
drain-source voltage −−7V
drain current (DC) −−40 mA
total power dissipation Ts≤ 102 °C; note 1 −−200 mW
input capacitance at gate 1 ID=15mA − 2.8 − pF
reverse transfer capacitance f = 1 MHz − 30 − fF
F noise figure f = 800 MHz −−2.8 dB
X
mod
T
j
cross-modulation input level for k = 1% at 40 dB AGC 100 −−dBµV
operating junction temperature −−150 °C
Note
is the temperature at the soldering point of the source lead.
1. T
s
CAUTION
This product is supplied in anti-static packing to prevent damage caused by electrostatic discharge during transport
and handling. For further information, refer to Philips specs.: SNW-EQ-608, SNW-FQ-302A and SNW-FQ-302B.
1999 Jul 08 2
Philips Semiconductors Preliminary specification
Fig.2 Power derating curve.
handbook, halfpage
0 50 100 200
250
0
200
MGS359
150
150
100
50
Ts (°C)
P
tot
(mW)
Dual N-channel dual gate MOS-FET BF1102
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
Per MOS-FET unless otherwise specified
V
DS
I
D
I
G1
I
G2
P
tot
T
stg
T
j
THERMAL CHARACTERISTICS
SYMBOL PARAMETER VALUE UNIT
R
th j-s
drain-source voltage − 7V
drain current (DC) − 40 mA
gate 1 current −±10 mA
gate 2 current −±10 mA
total power dissipation Ts≤ 102 °C − 200 mW
storage temperature −65 +150 °C
operating junction temperature − +150 °C
thermal resistance from junction to soldering point 240 K/W
1999 Jul 08 3
Philips Semiconductors Preliminary specification
Dual N-channel dual gate MOS-FET BF1102
STATIC CHARACTERISTICS
T
=25°C unless otherwise specified.
j
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
Per MOS-FET unless otherwise specified
V
(BR)DSS
V
(BR)G1-SS
V
(BR)G2-SS
V
(F)S-G1
V
(F)S-G2
V
G1-S(th)
V
G2-S(th)
I
DSX
I
G1-S
I
G2-S
drain-source breakdown voltage V
G1-S=VG2-S
=0; ID=10µA7− V
gate-source breakdown voltage VGS=VDS=0; I
gate-source breakdown voltage VGS=VDS=0; I
forward source-gate voltage V
forward source-gate voltage V
G2-S=VDS
G1-S=VDS
gate-source threshold voltage VDS=5V; V
gate-source threshold voltage VDS=5V; V
drain-source current V
gate cut-off current V
gate cut-off current V
G2-S
G1-S
G2-S
=0; I
=0; I
G2-S
G1-S
=4V; VDS=5V; RG= 120 kΩ; note 1 12 20 mA
=5V; V
=5V; V
G2-S=VDS
G1-S=VDS
=10mA 6 15 V
G1-S
=5mA 6 15 V
G2-S
= −10 mA 0.5 1.5 V
S-G1
= −10 mA 0.5 1.5 V
S-G2
=4V; ID=20µA0.31V
=4V; ID=20µA0.31.2V
=0 − 50 nA
=0 − 20 nA
Notes
1. R
connects gate 1 to VGG=5V.
G1
DYNAMIC CHARACTERISTICS
Common source; T
=25°C; V
amb
=4V; VDS=5V; ID= 15 mA; unless otherwise specified.
G2-S
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Per MOS-FET unless otherwise specified (note 1)
y
forward transfer admittance Tj=25°C 364350mS
fs
C
ig1-ss
C
ig2-ss
C
oss
C
rss
F noise figure f = 800 MHz; Y
X
mod
input capacitance at gate 1 f = 1 MHz 2 2.8 3.6 pF
input capacitance at gate 2 f = 1 MHz −−7pF
output capacitance f = 1 MHz − 1.6 2.5 pF
reverse transfer capacitance f = 1 MHz − 30 50 fF
S=YSopt
cross-modulation input level for k = 1% at 0 dB AGC;
=50MHz; f
f
w
=60MHz; (note2)
unw
input level for k = 1% at 40 dB AGC;
f
=50MHz; f
w
=60MHz; (note2)
unw
− 22.8dB
85 −−dBµV
100 −−dBµV
Notes
1. Not used MOS-FET: V
=0; VDS=0.
G1-S
2. Measured in test circuit of Fig.17.
1999 Jul 08 4
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