Philips bf1101_r_wr Datasheet

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Page 1

DATA SH EET

DISCRETE SEMICONDUCTORS

BF1101; BF1101R; BF1101WR

N-channel dual-gate MOS-FETs

Product specification Supersedes data of 1999 Feb 01

1999 May 14

Page 2

NXP Semiconductors Product specification

Fig.1 Simplified outline

(SOT143B).

BF1101 marking code: NDp.

handbook, 2 columns

Top view

MSB014

Fig.2 Simplified outline

(SOT143R).

BF1101R marking code: NCp.

handbook, 2 columns

Top view MSB035

Fig.3 Simplified outline

(SOT343R).

BF1101WR marking code: NC.

Top view

MSB842

N-channel dual-gate MOS-FETs

FEATURES

 Short channel transistor with high

forward transfer admittance to input capacitance ratio

 Low noise gain controlled amplifier

up to 1 GHz

 Partly internal self-biasing circuit to

ensure good cross-modulation performance during AGC and go od DC stabilization.

APPLICATIONS

 VHF and UHF applications with

3 to 7 V supply voltage, such as television tuners and professional communications equipment.

DESCRIPTION

PINNING

PIN DESCRIPTION

BF1101; BF1101R;

BF1101WR

1source 2drain 3 gate 2 4 gate 1

Enhancement type N-channel field-effect transistor with source and substrate interconnected. Integrated diodes between gates and source protect against excessive input voltage surges. The BF1101, BF1101R and BF1101WR are encapsulated in the SOT143B, SOT143R and SOT343R plastic packages respectively.

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

tot

 forward transfer admittance 25 30  mS

y

ig1-ss

rss

drain-source voltage 7V drain current 30 mA total power dissipation 200 mW

input capacitance at ga te1  2.2 2.7 pF

reverse transfer capacit a nce f = 1 MHz  25 35 fF F noise figure f = 800 MHz  1.7 2.5 dB X

mod

cross-modulation input level for k = 1% at

100 dBV

40 dB AGC

operating junction temperature 150 C

This product is supplied in anti-static packing to prevent damage caused by electrostatic discharge during transport and handling.

1999 May 14 2

CAUTION

Page 3

NXP Semiconductors Product specification

Fig.4 Power derating curve.

handbook, halfpage

0 50 100 200

250

200

MGL615

150

100

tot

(mW)

Ts (°C)

N-channel dual-gate MOS-FETs BF1101; BF1101R; BF1101WR

LIMITING VALUES

In accordance with the Absolu te Maximum Rating System (IEC 1 34).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

tot

stg

Note

1. T

THERMAL CHARACTERISTICS

drain-source voltage  7V drain current  30 mA gate 1 current 10 mA gate 2 current 10 mA total power dissipation Ts 110 C; note 1  200 mW storage temperature 65 +150 C operating junction temperature  +150 C

is the temperature of the soldering point of the source lead.

SYMBOL PARAMETER VALUE UNIT

th j-s

thermal resistance from junction to soldering point 200 K/W

1999 May 14 3

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NXP Semiconductors Product specification

N-channel dual-gate MOS-FETs BF1101; BF1101R; BF1101WR

STATIC CHARACTERISTICS

=25C unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

(BR)DSS

(BR)G1-SS

(BR)G2-SS

(F)S-G1

(F)S-G2

G1-S (th)

G2-S (th)

DSX

G1-SS

G2-SS

drain-source breakdown voltage V gate 1-source breakdown voltage V gate 2-source breakdown voltage V forward source-gate 1 voltage V forward source-gate 2 voltage V gate 1-source threshold voltage V gate 2-source threshold voltage V drain-source current V

gate 1 cut-off current V gate 2 cut-off current V

G1-S=VG2-S G2-S=VDS G1-S=VDS G2-S=VDS G1-S=VDS

=4V; VDS=5V; ID=100A0.31.0V

G2-S

=5V; VDS=5V; ID=100A0.31.2V

G1-S

=4V; VDS=5V; RG1=120k;

G2-S

=0; ID=10A7 V =0; I =0; I =0; I =0; I

=10mA 7 16 V

G1-S

=10mA 7 16 V

G2-S

=10mA 0.5 1.5 V

S-G1

=10mA 0.5 1.5 V

S-G2

816mA

note 1

G2-S=VDS G1-S=VDS

=0; V =0; V

=5V  50 nA

G1-S

=4V  20 nA

G2-S

Note

1. R

connects G1 to VGG= 5 V; see Fig.21.

DYNAMIC CHARACTERISTICS

Common source; T

=25C; V

amb

=4V; VDS=5V; ID= 12 m A; unless otherwise specified.

G2-S

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

 forward transfer admittance pulsed; Tj=25C 253040mS

y

ig1-ss

ig2-ss

oss

rss

F noise figure f = 800 MHz; Y X

mod

input capacitance at gate 1 f = 1 MHz  2.2 2.7 pF input capacitance at gate 2 f = 1 MHz  1.6  pF output capacitance f = 1 MHz  1.2  pF reverse transfer capacitance f = 1 MHz  25 35 fF

S=YSopt

cross-modulation input level for k = 1% at 0 dB AGC;

=50MHz; f

=60MHz; note1

unw

input level for k = 1% at 40 dB AGC; f

=50MHz; f

=60MHz; note1

unw

 1.7 2.5 dB 85 dBV

100 dBV

Note

1. Measured in test circuit of Fig.21.

1999 May 14 4

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NXP Semiconductors Product specification

Fig.5 Transfer characteristics; typical values.

VDS=5V. Tj=25C.

handbook, halfpage

0.4

MGS299

0.8 1.2 1.6 2

(mA)

G1-S

(V)

3.5 V

3 V

2.5 V

2 V

1 V

1.5 V

G2-S

= 4 V

Fig.6 Output characteristics; typical values.

G2-S

=4V.

Tj=25C.

handbook, halfpage

MGS300

468

(mA)

(V)

1.5 V

1.4 V

1.3 V

1.2 V

1.1 V 1 V

G1-S

= 1.6 V

Fig.7 Gate 1 current as a function of gate 1

voltage; typical values.

VDS=5V. T

=25C.

handbook, halfpage

100

0.5

MGS301

1 1.5 2 2.5

(μA)

G1-S

(V)

3.5 V

3 V

2.5 V

2 V

G2-S

= 4 V

Fig.8 Forward transfer admittance as a

function of drain current; typical values.

VDS=5V. T

=25C.

handbook, halfpage

81641220

MGS302

ID (mA)

(mS)

3 V

2.5 V

2 V

G2-S

= 4 V

3.5 V

N-channel dual-gate MOS-FETs BF1101; BF1101R; BF1101WR

1999 May 14 5

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NXP Semiconductors Product specification

Fig.9 Drain current as a function of gate 1 current;

typical values.

VDS=5V. V

G2-S

=4V.

Tj=25C.

handbook, halfpage

MGS303

20 30 40 50

(mA)

(μA)

Fig.10 Drain c ur ren t as a function of gate 1

supply voltage (= V

); typical values.

VDS=5V; V

G2-S

=4V; Tj=25C.

RG1=120k (connected to VGG); see Fig.21.

handbook, halfpage

MGS304

23 54

(mA)

VGG (V)

Fig.11 Drain current as a function of gate 1 (= VGG)

and drain supply voltage; typical values.

G2-S

=4V; Tj=25C.

connected to VGG; see Fig.21.

handbook, halfpage

2 468

(mA)

= VDS (V)

= 47 kΩ

68 kΩ

82 kΩ

100 kΩ 120 kΩ 150 kΩ

180 kΩ 220 kΩ

MGS305

VDS=5V; Tj=25C. RG1=120k (connected to VGG); see Fig.21.

Fig.12 Drain current as a function of gate 2 voltage;

typical values.

handbook, halfpage

MGS306

(mA)

G2-S

(V)

4.5 V 4 V

3.5 V 3 V

VGG = 5 V

N-channel dual-gate MOS-FETs BF1101; BF1101R; BF1101WR

1999 May 14 6

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NXP Semiconductors Product specification

Fig.13 Gate 1 current as a function of gate 2

voltage; typical values.

VDS=5V; Tj=25C. RG1=120k (connected to VGG); see Fig.21.

handbook, halfpage

MGS307

264

(μA)

G2-S

(V)

4.5 V

4 V

3.5 V 3 V

VGG = 5 V

Fig.14 Typical gain reduction as a function of

the AGC voltage; see Fig.21.

handbook, halfpage

−30

−20

−10

−40

−50

MGS308

234

gain

reduction

(dB)

AGC

(V)

(2) (1)(3)

VDS=5V; VGG= 5 V; f = 50 MHz; T

amb

=25C.

(1) RG1=68k. (2) RG1=120k.(3)RG1= 180 k.

Fig.15 Unwanted voltage for 1% cross-modulation

as a function of gain reduction; typical values; see Fig.21.

handbook, halfpage

120

100

110

MGS309

20 30 40 50

unw

(dBμV)

gain reduction (dB)

(2)

(3)

(1)

VDS=5V; VGG= 5 V; f = 50 MHz; f

unw

=60MHz; T

amb

=25C.

(1) RG1=68k. (2) RG1=120k.(3)RG1= 180 k.

Fig.16 Drain current as a function of gain reduction;

typical values; see Fig.21.

handbook, halfpage

MGS310

20 30 40 50

(mA)

gain reduction (dB)

(2)

(3)

(1)

VDS=5V; VGG= 5 V; f = 50 MHz; T

amb

=25C.

(1) RG1=68k. (2) RG1=120k.(3)RG1= 180 k.

N-channel dual-gate MOS-FETs BF1101; BF1101R; BF1101WR

1999 May 14 7

Page 8

NXP Semiconductors Product specification

Fig.17 Input admittance as a function of frequency;

typical values.

VDS=5V; VG2=4V. ID=12mA; T

amb

=25C.

handbook, halfpage

MGS311

−1

10 10

f (MHz)

(mS)

Fig.18 Reverse transfer admittance and phase as

a function of frequency; typical values.

VDS=5V; VG2=4V. ID=12mA; T

amb

=25C.

handbook, halfpage

MGS312

(deg)

−10

−1

−10

10 10

f (MHz)

|yrs| (mS)

|yrs|

Fig.19 Forward transfer admittance and phase as

a function of frequency; typical values.

VDS=5V; VG2=4V. ID=12mA; T

amb

=25C.

handbook, halfpage

MGS313

(deg)

−10

−1

−10

10 10

f (MHz)

|yfs|

(mS)

|yfs|

Fig.20 Output admittance as a function of

frequency; typical values.

VDS=5V; VG2=4V. ID=12mA; T

amb

=25C.

handbook, halfpage

MGS314

−1

10 10

f (MHz)

(mS)

N-channel dual-gate MOS-FETs BF1101; BF1101R; BF1101WR

1999 May 14 8

Page 9

NXP Semiconductors Product specification

Fig.21 Cross-modulation test set-up.

handbook, full pagewidth

DUT

4.7 nF

10 kΩ

MGS315

4.7 nF

≈2.2 μH

4.7 nF

50 Ω

AGC

GEN 50 Ω

50 Ω

4.7 nF

N-channel dual-gate MOS-FETs BF1101; BF1101R; BF1101WR

Table 1 Scattering parameters: VDS=5V; V

(MHz)

1000 0.832 70.3 2.214 94.2 0.006 110.4 0.946 39.6

Table 2 Noise data: V

MAGNITUDE

(ratio)

ANGLE

(deg)

G2-S

MAGNITUDE

(ratio)

=4V; ID=12mA; T

ANGLE

MAGNITUDE

(deg)

amb

(ratio)

=25C

ANGLE

(deg)

MAGNITUDE

(ratio)

ANGLE

(deg)

50 0.987 4.1 2.922 175.0 0.001 87.6 0.990 2.2 100 0.985 8.1 2.908 170.3 0.001 86.1 0.989 4.3 200 0.976 16.1 2.875 160.8 0.003 83.3 0.985 8.5 300 0.963 23.9 2.820 157.6 0.004 80.4 0.982 12.6 400 0.949 31.6 2.762 142.6 0.005 78.2 0.977 16.8 500 0.933 38.8 2.665 134.1 0.005 77.8 0.972 20.8 600 0.916 45.7 2.591 125.7 0.005 78.9 0.967 24.7 700 0.897 52.2 2.498 117.7 0.006 81.8 0.961 28.5 800 0.877 58.4 2.410 109.6 0.005 89.1 0.957 32.2 900 0.856 64.5 2.318 101.6 0.006 97.1 0.950 35.8

=5V; V

G2-S

(MHz)

800 1.5 0.715 58.3 37.85

=4V; ID=12mA; T

min

(dB)

=25C

amb



opt

(ratio) (deg)

()

1999 May 14 9

Page 10

NXP Semiconductors Product specification

UNIT

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC JEITA

1.1

0.9

max

0.1

0.88

0.78

0.15

0.09

3.0

2.8

1.4

1.2

ywvQ

2.5

2.1

0.45

0.15

0.55

0.45

1.9

1.7

0.1 0.10.2

0.48

0.38

DIMENSIONS (mm are the original dimensions)

SOT143B

04-11-16 06-03-16

0 1 2 mm

scale

Plastic surface-mounted package; 4 leads SOT143B

v M

detail X

w M

N-channel dual-gate MOS-FETs BF1101; BF1101R; BF1101WR

PACKAGE OUTLINES

1999 May 14 10

Page 11

NXP Semiconductors Product specification

UNIT

REFERENCES

OUTLINE VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC JEITA

1.1

0.9

max

0.1

0.88

0.78

0.15

0.09

3.0

2.8

1.4

1.2

ywvQ

2.5

2.1

0.55

0.25

0.45

0.25

1.9

1.7

0.1 0.10.2

0.48

0.38

DIMENSIONS (mm are the original dimensions)

SOT143R SC-61AA

04-11-16 06-03-16

0 1 2 mm

scale

Plastic surface-mounted package; reverse pinning; 4 leads SOT143R

v M

detail X

w M

N-channel dual-gate MOS-FETs BF1101; BF1101R; BF1101WR

1999 May 14 11

Page 12

NXP Semiconductors Product specification

REFERENCES

OUTLINE VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC EIAJ

SOT343R

detail X

v M

0 1 2 mm

scale

Plastic surface-mounted package; reverse pinning; 4 leads SOT343R

w M

97-05-21 06-03-16

UNIT

max

HEL

Qwv

0.1

1.1

0.8

0.4

0.3

0.25

0.10

0.7

0.5

2.2

1.8

1.35

1.15

2.2

2.0

1.3

0.2y0.10.21.15

DIMENSIONS (mm are the original dimensions)

0.45

0.15

0.23

0.13

N-channel dual-gate MOS-FETs BF1101; BF1101R; BF1101WR

1999 May 14 12

Page 13

NXP Semiconductors Product specification

N-channel dual-gate MOS-FETs BF1101; BF1101R; BF1101WR

DATA SHEET STATUS

DOCUMENT

STATUS

Objective data sheet D evelopment This document contains data from the objective specification for product

Preliminary data sheet Qualification This document contains data from the preliminary specification. Product data sheet Production This document contains the product specification.

Notes

1. Please consult the most recently issued document before initiating or completing a design.

2. The product status of device(s) desc ribed in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

DEFINITIONS Product specification  The information and data

provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.

DISCLAIMERS Limited warranty and liability  Information in this

document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information.

In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors.

(1)

PRODUCT STATUS

(2)

DEFINITION

development.

Right to make changes  NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication he reof.

Suitability for use  NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications wher e failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inc l usion and/or use is at the customer’s own risk.

Applications  Applications that ar e described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.

Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the ris ks associated with their applications and products.

1999 May 14 13

Page 14

NXP Semiconductors Product specification

N-channel dual-gate MOS-FETs BF1101; BF1101R; BF1101WR

NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applicat ions and products using NXP Semiconductors products in or de r to avoid a default of the applications and the prod ucts or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect.

Limiting values  Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Rec ommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device.

Terms and conditions of commercial sale  NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In cas e an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer.

Export control  This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities.

Quick reference data  The Quick reference data is an extract of the product data given in t he Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding.

Non-automotive qualified products  Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with auto motive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from cus tom er d esign and use o f the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications.

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1999 May 14 14

Page 15

NXP Semiconductors

provides High Performance Mixed Signal and Standard Product solutions that leverage its leading RF, Analog, Power Management, Interface, Security and Digital Processing expertise

Customer notification

This data sheet was changed to reflect the new company name NXP Semiconductors, including new legal definitions and disclaimers. No changes were made to the technical content, except for package outline drawings which were updated to the latest version.

Contact information

For additional information please visit: http://www.nxp.com For sales offices addresses send e-mail to: [email protected]

The information presented in this document does not form part of any quotation or contra ct, is b elieve d t o b e a ccur ate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property righ ts.

Printed in The Netherlands R77/02/pp15 Date of release: 1999May 14