Philips bf1100wr Datasheet

DATA SH EET

DISCRETE SEMICONDUCTORS

BF1100WR

Dual-gate MOS-FET

Product specification 1995 Apr 25

NXP Semiconductors Product specification

Fig.1 Simplified outline (SOT343R) and symbol.

Marking code: MF.

handbook, halfpage

MAM192

s,b

d

g

1

g

2

Top view

21

34

Dual-gate MOS-FET BF1100WR

FEATURES

 Specially designed for use at 9 to 12 V supply voltage  Short channel transistor with high forward transfer

admittance to input capacitance ratio

 Low noise gain controlled amplifier up to 1 GHz  Superior cross-modulation performance during AGC.

APPLICATIONS

 VHF and UHF applications such as television tuners and

professional communications equipment.

DESCRIPTION

Enhancement type field-effect transistor in a plastic microminiature SOT343R package. The transistor consists of an amplifier MOS-FET with source and substrate interconnected and an internal bias circuit to ensure good cross-modulation performance during AGC.

CAUTION

The device is supplied in an antistatic package. The gate-source input must be protected against static discharge during transport or handlin g.

PINNING

PIN SYMBOL DESCRIPTION

1s, bsource 2 d drain 3g 4g

gate 2

2

gate 1

1

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

DS

I

D

P

tot

T

j

 forward transfer admittance 24 28 33 mS

y

fs

C

ig1-s

C

rs

drain-source voltage 14 V drain current 30 mA total power dissipation 280 mW operating junction temperature 150 C

input capacitance at gate 1  2.2 2.6 pF reverse transfer capacitance f = 1 MHz  25 35 fF

F noise figure f = 800 MHz  2  dB

1995 Apr 25 2

NXP Semiconductors Product specification

Fig.2 Power derating curve.

handbook, halfpage

0 50 100 200

300

0

MLD180

150

200

100

P

tot

(mW)

T ( C)

amb

o

Fig.3 Forward transfer admittance as a fun ction

of junction temperature; typical values.

50 0 50 150

40

0

MLD156

100

30

20

10

Y

fs

(mS)

T ( C)

j

o

Dual-gate MOS-FET BF1100WR

LIMITING VALUES

In accordance with the Absolu te Maximum Rating System (IEC 134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

DS

I

D

I

G1

I

G2

P

tot

T

stg

T

j

Note

1. Device mounted on a printed-circuit board.

drain-source voltage  14 V drain current  30 mA gate 1 current 10 mA gate 2 current 10 mA total power dissipation se e Fig.2; up to T

=50C; note 1  280 mW

amb

storage temperature 65 +150 C operating junction temperature  +150 C

1995 Apr 25 3

NXP Semiconductors Product specification

Dual-gate MOS-FET BF1100WR

THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS VALUE UNIT

R

th j-a

R

th j-s

Notes

1. Device mounted on a printed-circuit board.

2. T

is the temperature at the soldering point of the source lead.

s

STATIC CHARACTERISTICS

=25C; unless otherwise specified.

T

j

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

(BR)G1-SS

V

(BR)G2-SS

V

(F)S-G1

V

(F)S-G2

V

G1-S(th)

V

G2-S(th)

I

DSX

I

G1-SS

I

G2-SS

thermal resistance from junction to ambient note 1 350 K/W thermal resistance from junction to soldering point Ts=91C; note 2 210 K/W

gate 1-source br eakdown voltage V gate 2-source br eakdown voltage V forward source-gate 1 voltage V forward source-gate 2 voltage V gate 1-source th reshold voltage V

gate 2-source th reshold voltage V

drain-source current V

gate 1 cut-off current V gate 2 cut-off current V

G2-S=VDS G1-S=VDS G2-S=VDS G1-S=VDS G2-S

I

=20A

D

V

G2-S

=20A

I

D

G1-S

I

=20A

D

V

G1-S

=20A

I

D

G2-S

=180k; note 1

R

G1

V

G2-S

=250k; note 2

R

G1 G2-S=VDS G1-S=VDS

=0; I =0; I =0; I =0; I

=1mA 13.2 20 V

G1-S

=1mA 13.2 20 V

G2-S

=10mA 0.5 1.5 V

S-G1

=10mA 0.5 1.5 V

S-G2

=4V; VDS=9V;

=4V; VDS=12V;

=4V; VDS=9V;

=4V; VDS=12V;

=4V; VDS=9V;

=4V; VDS=12V;

=0; V =0; V

=12V  50 nA

G1-S

=12V  50 nA

G2-S

0.3 1 V

0.3 1.2 V

813mA

Notes

1. R

2. R

connects gate 1 to VGG=9V; seeFig.26.

G1

connects gate 1 to VGG=12V; seeFig.26.

G1

1995 Apr 25 4

NXP Semiconductors Product specification

Fig.4 Gain reduction as a function of the AGC

voltage; typical values.

f=50MHz. Tj=25C.

handbook, halfpage

0

10

20

30

40

50

01234

V (V)

AGC

gain

reduction

(dB)

MLD157

(1) RG=250k to VGG=12V. (2) RG=180k to VGG=9V. fw=50MHz; f

unw

=60MHz; T

amb

=25C.

Fig.5 Unwanted voltage for 1% cross-modulation

as a function of gain reduction; typical values; see Fig. 26.

handbook, halfpage

80

90

100

110

120

0

(1)

(2)

10 20 30 40 50

V

unw

(dBμV)

gain reduction (dB)

MLD158

Dual-gate MOS-FET BF1100WR

DYNAMIC CHARACTERISTICS

Common source; T

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

y

 forward transfer admittance pulsed; Tj=25C

fs

C

ig1-s

ig2-s

os

rs

input capacitance at gate 1 f = 1 MHz

input capacitance at gate 2 f = 1 MHz

drain-source capacitance f = 1 MHz

reverse transfer capacitance f = 1 MHz

F noise figure f = 800 MHz; G

=25C; V

amb

=4V; ID= 10 mA; unless otherwise specified.

G2-S

=9V 242833mS

V

DS

= 12 V 24 28 33 mS

V

DS

V

=9V  2.2 2.6 pF

DS

=12V  2.2 2.6 pF

V

DS

=9V  1.6  pF

V

DS

=12V  1.4  pF

V

DS

V

=9V  1.4 1.8 pF

DS

=12V  1.1 1.5 pF

V

DS

=9V  25 35 fF

V

DS

=12V  25 35 fF

V

DS

S=GSopt

; BS=B VDS=9V  22.8dB V

=12V  22.8dB

DS

Sopt

1995 Apr 25 5

NXP Semiconductors Product specification

Fig.6 Output characteristics; typical values.

V

G2-S

=4V.

Tj=25C.

handbook, halfpage

0

20

16

4

8

12

0

416

MLD159

812

I

D

(mA)

V (V)

DS

1.3 V

1.2 V

1.1 V

1.0 V

0.9 V

V = 1.4 V

G1 S

Fig.7 Transfer characteristics; typical values.

VDS=9to12V. Tj=25C.

handbook, halfpage

0

20

16

4

8

12

0

0.4 2.0

MLD160

0.8 1.2 1.6

I

D

(mA)

V (V)

G1 S

V = 4 V

2.5 V 2 V

1.5 V

1 V

G2 S

3 V

Fig.8 Gate 1 current as a function of gate 1

voltage; typical values.

VDS=9to12V. T

j

=25C.

handbook, halfpage

0123

250

200

150

50

0

100

MLD161

I

G1

(μA)

V (V)

G1 S

3 V

2.5 V

2 V

3.5 V

V = 4 V

G2 S

Fig.9 Forward transfer admittance as a function

of drain current; typical values.

VDS=9to12V. T

j

=25C.

handbook, halfpage

0

40

20

30

10

0

10 20 30

MLD162

y

fs

(mS)

I (mA)

D

3 V

2.5 V

2 V

V = 4 V

G2 S

3.5 V

Dual-gate MOS-FET BF1100WR

1995 Apr 25 6

NXP Semiconductors Product specification

Fig.10 Drain current as a function of gate 1 current;

typical values.

VDS= 9 to12 V. V

G2-S

=4V.

Tj=25C.

handbook, halfpage

02040 8060

16

12

4

0

8

MLD163

I (μA)

G1

I

D

(mA)

Fig.11 Drain current as a function of gate 1 supply

voltage (= V

GG

) and drain supply voltage;

typical values; see Fig.26.

V

G2-S

=4V. RG1 connected to VGG. Tj=25C.

handbook, halfpage

0

20

15

10

5

0

48 16

MLD164

12

V = V (V)

GG DS

I

D

(mA)

R = 100 kΩ

G1

147 kΩ

180 kΩ

205 kΩ 249 kΩ 301 kΩ

402 kΩ

511 kΩ

Fig.12 Drain current as a function of gate 1 voltage

(= V

GG

); typical values; see Fig.26.

VDS=9V; V

G2-S

=4V.

RG1=180kconnected to VGG); Tj=25C.

handbook, halfpage

024 1086

12

4

0

8

MLD165

V (V)

GG

I

D

(mA)

VDS=12V; V

G2-S

=4V.

RG1=250k (connected to VGG); Tj=25C.

Fig.13 Drain current as a function of gate 1 voltage

(= V

GG

); typical values; see Fig.26.

handbook, halfpage

04812

12

4

0

8

MLD166

V (V)

GG

I

D

(mA)

Dual-gate MOS-FET BF1100WR

1995 Apr 25 7

NXP Semiconductors Product specification

Fig.14 Gate 1 current as a function of gate 2 voltage;

typical values.

VDS=9V. RG1=180k (connected to VGG); Tj=25C.

handbook, halfpage

0246

50

40

30

10

0

20

MLD167

I

G1

(μA)

V (V)

G2 S

8 V 7 V

6 V 5 V 4 V

V = 9 V

GG

Fig.15 Gate 1 current as a function of gate 2 voltage;

typical values.

VDS=12V. RG1=250k (connected to VGG); Tj=25C.

handbook, halfpage

0246

50

40

30

10

0

20

MLD168

I

G1

(μA)

V (V)

G2 S

11 V 10 V

9 V 8 V 7 V

V = 12 V

GG

Fig.16 Drain current as a function of the gate 2

voltage; typical values; see Fig.26.

VDS=9V. RG1=180k (connected to VGG); Tj=25C.

handbook, halfpage

0246

0

16

MLD169

12

8

4

I

D

(mA)

8 V 7 V 6 V

5 V 4 V

V = 9 V

GG

V (V)

G2 S

VDS=12V. RG1=250k (connected to VGG); Tj=25C.

Fig.17 Drain current as a function of the gate 2

voltage; typical values; see Fig.26.

handbook, halfpage

0246

0

16

MLD170

12

8

4

I

D

(mA)

11 V 10 V 9 V

8 V 7 V

V = 12 V

GG

V (V)

G2 S

Dual-gate MOS-FET BF1100WR

1995 Apr 25 8

NXP Semiconductors Product specification

Fig.18 Input admittance as a function of

frequency; typical values.

VDS=9V; VG2=4V. ID=10mA; T

amb

=25C.

handbook, halfpage

10

3

MLD181

10

2

10

1

10

2

10

1

y

is

(mS)

f (MHz)

b

is

g

is

VDS=9V; VG2=4V. ID=10mA; T

amb

=25C.

Fig.19 Reverse transfer admittance and phase as

a function of frequency; typical values.

10

3

MLD182

10

2

10

3

10

2

10

1

y

rs

10

3

10

1

2

rs

(μS)

f (MHz)

rs

y

rs

(deg)

ϕ

Fig.20 Forward transfer admittance and phase as

a function of frequency; typical values.

VDS=9V; VG2=4V. ID=10mA; T

amb

=25C.

10

3

MLD183

10

2

10

1

10

2

10

1

10

2

y

fs

(mS)

y

fs

f (MHz)

fs

(deg)

ϕ

Fig.21 Output admittance as a function of

frequency; typical values.

VDS=9V; VG2=4V. ID=10mA; T

amb

=25C.

handbook, halfpage

10

3

MLD184

10

2

10

1

10

1

10

2

y

os

(mS)

f (MHz)

b

os

g

os

Dual-gate MOS-FET BF1100WR

1995 Apr 25 9

NXP Semiconductors Product specification

Fig.22 Input admittance as a function of

frequency; typical values.

VDS=12V; VG2=4V. ID=10mA; T

amb

=25C.

handbook, halfpage

10

3

MLD185

10

2

10

1

10

2

10

1

y

is

(mS)

f (MHz)

b

is

g

is

VDS=12V; VG2=4V. ID=10mA; T

amb

=25C.

Fig.23 Reverse transfer admittance and phase as

a function of frequency; typical values.

10

3

MLD186

10

2

10

3

10

2

10

1

y

rs

10

3

10

1

2

rs

(μS)

f (MHz)

rs

y

rs

(deg)

ϕ

Fig.24 Forward transfer admittance and phase as

a function of frequency; typical values.

VDS=12V; VG2=4V. I

D

=10mA; T

amb

=25C.

10

3

MLD187

10

2

10

1

10

2

10

1

10

2

y

fs

(mS)

y

fs

f (MHz)

fs

(deg)

ϕ

Fig.25 Output admittance as a function of

frequency; typical values.

VDS=12V; VG2=4V. ID=10mA; T

amb

=25C.

handbook, halfpage

10

3

MLD188

10

2

10

1

10

1

10

2

y

os

(mS)

f (MHz)

b

os

g

os

Dual-gate MOS-FET BF1100WR

1995 Apr 25 10

NXP Semiconductors Product specification

Fig.26 Cross-modulation test circuit.

handbook, full pagewidth

DUT

V

AGC

C1

4.7 nF

R1

10 kΩ

MGC420

C4

4.7 nF

L1

450 nH

C3 12 pF

R

L

50 Ω

≈

V

GG

V

DS

R

GEN

50

V

I

R2

50

4.7 nF

C2

R

G

Ω

For VGG=VDS=9V, RG=180 k. For VGG=VDS=12V, RG=250 k.

Dual-gate MOS-FET BF1100WR

1995 Apr 25 11

NXP Semiconductors Product specification

Dual-gate MOS-FET BF1100WR

Table 1 Scattering parameters: VDS=9V; V

s

f

(MHz)

MAGNITUDE

(ratio)

11

ANGLE

(deg)

MAGNITUDE

(ratio)

=4V; ID=10mA

G2-S

s

21

ANGLE

(deg)

s

12

MAGNITUDE

(ratio)

ANGLE

(deg)

s

22

MAGNITUDE

(ratio)

ANGLE

(deg)

50 0.985 3.9 2.618 175.1 0.001 137.9 1.000 1.9 100 0.981 7.3 2.602 170.5 0.001 80.4 0.999 4.0 200 0.975 14.4 2.577 160.7 0.002 74.0 0.995 7.6 300 0.965 21.6 2.555 151.6 0.002 79.3 0.994 11.3 400 0.947 28.3 2.513 141.8 0.003 80.5 0.992 15.0 500 0.927 34.9 2.449 133.4 0.003 82.8 0.988 18.5 600 0.913 41.7 2.339 124.6 0.003 78.9 0.984 22.0 700 0.890 47.9 2.361 115.4 0.003 80.6 0.982 25.3 800 0.869 54.0 2.302 106.4 0.003 93.9 0.979 28.8 900 0.845 59.7 2.228 97.6 0.003 104.8 0.976 32.1

1000 0.823 65.4 2.167 89.6 0.003 129.3 0.974 35.5

Table 2 Noise data: V

f

(MHz)

=9V; V

DS

=4V; ID=10mA

G2-S

F

min

(dB)



opt

(ratio) (deg)

r

n

800 2.00 0.67 43.9 0.89

Table 3 Scattering parameters: V

s

f

(MHz)

MAGNITUDE

(ratio)

11

ANGLE

(deg)

=12V; V

DS

MAGNITUDE

(ratio)

=4V; ID=10mA

G2-S

s

21

ANGLE

(deg)

s

12

MAGNITUDE

(ratio)

ANGLE

(deg)

s

22

MAGNITUDE

(ratio)

ANGLE

(deg)

50 0.985 3.7 2.576 175.3 0.000 125.0 1.000 1.6 100 0.980 7.4 2.563 170.9 0.001 111.2 1.000 3.3 200 0.973 14.6 2.541 161.6 0.002 83.0 0.997 6.4 300 0.962 21.5 2.519 152.9 0.002 85.2 0.996 9.3 400 0.946 28.5 2.479 143.5 0.003 79.4 0.995 12.4 500 0.929 35.0 2.419 135.5 0.003 78.2 0.991 15.3 600 0.912 41.6 2.373 127.2 0.003 80.0 0.989 18.1 700 0.895 47.8 2.336 118.7 0.003 83.4 0.987 20.9 800 0.868 53.8 2.284 110.0 0.003 91.3 0.985 23.7 900 0.845 59.8 2.213 101.6 0.003 95.9 0.983 26.5

1000 0.823 65.7 2.160 94.1 0.003 112.2 0.981 29.3

Table 4 Noise data: V

f

(MHz)

=12V; V

DS

=4V; ID=10mA

G2-S

F

min

(dB)



opt

(ratio) (deg)

r

n

800 2.00 0.66 43.3 0.97

1995 Apr 25 12

NXP Semiconductors Product specification

REFERENCES

OUTLINE VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC EIAJ

SOT343R

D

A

1

L

p

Q

detail X

c

H

E

v M

A

AB

0 1 2 mm

scale

X

21

43

Plastic surface-mounted package; reverse pinning; 4 leads SOT343R

w M

B

97-05-21 06-03-16

b

p

UNIT

A

1

max

b

p

cD

E

b

1

H

E

L

p

Qwv

mm

0.1

1.1

0.8

0.4

0.3

0.25

0.10

0.7

0.5

2.2

1.8

1.35

1.15

e

2.2

2.0

1.3

e

1

0.2y0.10.21.15

DIMENSIONS (mm are the original dimensions)

0.45

0.15

0.23

0.13

e

1

A

e

y

b

1

Dual-gate MOS-FET BF1100WR

PACKAGE OUTLINE

1995 Apr 25 13

NXP Semiconductors Product specification

Dual-gate MOS-FET BF1100WR

DATA SHEET STATUS

DOCUMENT

STATUS

Objective data sheet Development This document contains data from the objective specification for product

Preliminary data sheet Qualification This document contains data from the preliminary specification. Product data sheet Production This document contains the prod uct specification.

Notes

1. Please consult the most recently issued document before initiating or co mpleting a design.

2. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

DEFINITIONS Product specification  The information and data

provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.

DISCLAIMERS Limited warranty and liability  Information in this

document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information.

In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors.

(1)

PRODUCT STATUS

(2)

DEFINITION

development.

Right to make changes  NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication he reof.

Suitability for use  NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications wher e failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inc l usion and/or use is at the customer’s own risk.

Applications  Applications that ar e described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.

Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the ris ks associated with their applications and products.

1995 Apr 25 14

NXP Semiconductors Product specification

Dual-gate MOS-FET BF1100WR

NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applicat ions and products using NXP Semiconductors products in or de r to avoid a default of the applications and the prod ucts or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect.

Limiting values  Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Rec ommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device.

Terms and conditions of commercial sale  NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In cas e an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer.

Export control  This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities.

Quick reference data  The Quick reference data is an extract of the product data given in t he Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding.

Non-automotive qualified products  Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with auto motive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from cus tom er d esign and use o f the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications.

No offer to sell or license  Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights .

1995 Apr 25 15

NXP Semiconductors

provides High Performance Mixed Signal and Standard Product solutions that leverage its leading RF, Analog, Power Management, Interface, Security and Digital Processing expertise

Customer notification

This data sheet was changed to reflect the new company name NXP Semiconductors, including new legal definitions and disclaimers. No changes were made to the technical content, except for package outline drawings which were updated to the latest version.

Contact information

For additional information please visit: http://www.nxp.com For sales offices addresses send e-mail to: [email protected]

The information presented in this document does not form part of any quotation or contract, is b elieve d t o b e a ccur ate a nd re liable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.

Printed in The Netherlands R77/01/pp16 Date of release: 1995 Apr 25