Philips bf1100_n Datasheet

BF1100; BF1100R

Dual-gate MOS-FETs

Rev. 02 — 13 November 2007 Product data sheet

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NXP Semiconductors

NXP Semiconductors Product specification

Rev. 02 - 13 November 2007

2 of 15

Dual-gate MOS-FETs BF1100; BF1100R

FEATURES

• Specially designed for use at 9 to 12 V supply voltage

• Short channel transistor with high forward transfer

admittance to input capacitance ratio

• Low noise gain controlled amplifier up to 1 GHz

• Superior cross-modulation performance during AGC.

APPLICATIONS

• VHF and UHF applications such as television tuners and
professional communications equipment.

DESCRIPTION

Enhancement type field-effect transistor in a plastic
microminiature SOT143 or SOT143R package. The
transistor consists of an amplifier MOS-FET with source

handbook, halfpage

43

d

and substrate interconnected and an internal bias circuit to
ensure good cross-modulation performance during AGC.

CAUTION

The device is supplied in an antistatic package. The
gate-source input must be protected against static
discharge during transport or handling.

PINNING

PIN SYMBOL DESCRIPTION

1 s, b source
2 d drain
3g
4g

handbook, halfpage

34

gate 2

2

gate 1

1

d

g

2

g

1

21

Top view

BF1100 marking code: %MY.

MAM124

Fig.1 Simplified outline (SOT143) and symbol.

s,b

12

Top view

BF1100R marking code: %MZ.

MAM125 - 1

Fig.2 Simplified outline (SOT143R) and symbol.

g

2

g

1

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

DS

I

D

P

tot

T

j

 forward transfer admittance 24 28 33 mS

y

fs

C

ig1-s

C

rs

drain-source voltage −−14 V
drain current −−30 mA
total power dissipation −−200 mW
operating junction temperature −−150 °C

input capacitance at gate 1 − 2.2 2.6 pF
reverse transfer capacitance f=1MHz − 25 35 fF

F noise figure f = 800 MHz − 2 − dB

s,b

NXP Semiconductors Product specification

Rev. 02 - 13 November 2007

3 of 15

Dual-gate MOS-FETs BF1100; BF1100R

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

DS

I

D

I

G1

I

G2

P

tot

T

stg

T

j

Note

1. Device mounted on a printed-circuit board.

drain-source voltage − 14 V
drain current − 30 mA
gate 1 current −±10 mA
gate 2 current −±10 mA
total power dissipation see Fig.3

BF1100 up to T
BF1100R up to T

=50°C; note 1 − 200 mW

amb

=40°C; note 1 − 200 mW

amb

storage temperature −65 +150 °C
operating junction temperature − +150 °C

250

handbook, halfpage

P

tot

(mW)

200

150

100

50

0

0 50 100 200

BF1100R BF1100

150

T ( C)

amb

Fig.3 Power derating curves.

MLD155

o

100

MLD156

o

T ( C)

j

40

Y

fs

(mS)

30

20

10

0

50 0 50 150

Fig.4 Forward transfer admittance as a function

of junction temperature; typical values.

NXP Semiconductors Product specification

Rev. 02 - 13 November 2007

4 of 15

Dual-gate MOS-FETs BF1100; BF1100R

THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS VALUE UNIT

R

th j-a

R

th j-s

Notes

1. Device mounted on a printed-circuit board.

is the temperature at the soldering point of the source lead.

2. T

s

STATIC CHARACTERISTICS

=25°C; unless otherwise specified.

T

j

thermal resistance from junction to ambient note 1

BF1100 500 K/W
BF1100R 550 K/W

thermal resistance from junction to soldering point note 2

BF1100 T
BF1100R T

=92°C 290 K/W

s

=78°C 360 K/W

s

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

(BR)G1-SS

V

(BR)G2-SS

V

(F)S-G1

V

(F)S-G2

V

G1-S(th)

gate 1-source breakdown voltage V
gate 2-source breakdown voltage V
forward source-gate 1 voltage V
forward source-gate 2 voltage V
gate 1-source threshold voltage V

G2-S=VDS
G1-S=VDS
G2-S=VDS
G1-S=VDS
G2-S

= 0; I
= 0; I
= 0; I
= 0; I

=4V; VDS=9V;

= 1 mA 13.2 20 V

G1-S

= 1 mA 13.2 20 V

G2-S

= 10 mA 0.5 1.5 V

S-G1

= 10 mA 0.5 1.5 V

S-G2

0.3 1 V

ID=20µA

=4V; VDS=12V;

V

G2-S

0.3 1 V

ID=20µA

V

G2-S(th)

gate 2-source threshold voltage V

=4V; VDS=9V;

G1-S

0.3 1.2 V

ID=20µA

=4V; VDS=12V;

V

G1-S

0.3 1.2 V

ID=20µA

I

DSX

drain-source current V

=4V; VDS=9V;

G2-S

813mA

RG1= 180 kΩ; note 1

I

G1-SS

I

G2-SS

gate 1 cut-off current V
gate 2 cut-off current V

V

=4V; VDS=12V;

G2-S

= 250 kΩ; note 2

R

G1
G2-S=VDS
G1-S=VDS

= 0; V
= 0; V

=12V − 50 nA

G1-S

=12V − 50 nA

G2-S

813mA

Notes

1. R

connects gate 1 to VGG= 9 V; see Fig.27.

G1

2. RG1 connects gate 1 to VGG= 12 V; see Fig.27.

NXP Semiconductors Product specification

Rev. 02 - 13 November 2007

5 of 15

Dual-gate MOS-FETs BF1100; BF1100R

DYNAMIC CHARACTERISTICS

Common source; T

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

y

 forward transfer admittance pulsed; Tj=25°C

fs

C

C

C

C

ig1-s

ig2-s

os

rs

input capacitance at gate 1 f = 1 MHz

input capacitance at gate 2 f = 1 MHz

drain-source capacitance f = 1 MHz

reverse transfer capacitance f = 1 MHz

F noise figure f = 800 MHz; G

=25°C; V

amb

= 4 V; ID= 10 mA; unless otherwise specified.

G2-S

= 9 V 24 28 33 mS

V

DS

= 12 V 24 28 33 mS

V

DS

=9V − 2.2 2.6 pF

V

DS

=12V − 2.2 2.6 pF

V

DS

=9V − 1.6 − pF

V

DS

=12V − 1.4 − pF

V

DS

=9V − 1.4 1.8 pF

V

DS

=12V − 1.1 1.5 pF

V

DS

=9V − 25 35 fF

V

DS

=12V − 25 35 fF

V

DS

S=GSopt

; BS=B

VDS=9V − 2 2.8 dB

=12V − 2 2.8 dB

V

DS

Sopt

0

handbook, halfpage

gain

reduction

(dB)

10

20

30

40

50

01234

f =50 MHz.
Tj=25°C.

V (V)

AGC

Fig.5 Gain reduction as a function of the AGC

voltage; typical values.

MLD157

120

handbook, halfpage

V

unw

(dBµV)

110

100

90

80

0

10 20 30 40 50

(1) RG= 250 kΩ to VGG=12V
(2) RG= 180 kΩ to VGG=9V
fw= 50 MHz; f

= 60 MHz; T

unw

amb

gain reduction (dB)

=25°C.

MLD158

(1)

(2)

Fig.6 Unwanted voltage for 1% cross-modulation

as a function of gain reduction; typical
values; see Fig.27.

NXP Semiconductors Product specification

Rev. 02 - 13 November 2007

6 of 15

Dual-gate MOS-FETs BF1100; BF1100R

20

handbook, halfpage

I

D

(mA)

16

12

8

4

0

V

=4V.

G2-S

Tj=25°C.

0

V = 1.4 V

G1 S

1.3 V

1.2 V

1.1 V

1.0 V

0.9 V

416

812

Fig.7 Output characteristics; typical values.

MLD159

V (V)

DS

20

handbook, halfpage

I

D

(mA)

16

12

8

4

0

0

VDS= 9 to 12 V.
Tj=25°C.

0.4 2.0

V = 4 V

G2 S

0.8 1.2 1.6

3 V

Fig.8 Transfer characteristics; typical values.

MLD160

2.5 V
2 V

1.5 V

1 V

V (V)

G1 S

250

handbook, halfpage

I

G1

(µA)

200

150

100

50

0

0123

VDS= 9 to 12 V.
Tj=25°C.

V = 4 V

G2 S

3.5 V

3 V

2.5 V

2 V

Fig.9 Gate 1 current as a function of gate 1

voltage; typical values.

MLD161

V (V)

G1 S

40

handbook, halfpage

y

fs

(mS)

30

20

10

0

0

VDS= 9 to 12 V.
Tj=25°C.

10 20 30

V = 4 V

G2 S

3.5 V

3 V

2.5 V

2 V

I (mA)

D

Fig.10 Forward transfer admittance as a function

of drain current; typical values.

MLD162

NXP Semiconductors Product specification

Rev. 02 - 13 November 2007

7 of 15

Dual-gate MOS-FETs BF1100; BF1100R

16

handbook, halfpage

I

D

(mA)

12

8

4

0

02040 8060

VDS= 9 to 12 V.
V

=4V.

G2-S

Tj=25°C.

MLD163

I (µA)

G1

Fig.11 Drain current as a function of gate 1 current;

typical values.

20

handbook, halfpage

I

D

(mA)

15

10

5

0

0

V

=4V.

G2-S

RG1 connected to VGG.
Tj=25°C.

R = 100 kΩ

G1

48 16

V = V (V)

GG DS

MLD164

147 kΩ

180 kΩ

205 kΩ
249 kΩ
301 kΩ

402 kΩ

511 kΩ

12

Fig.12 Drain current as a function of gate 1 supply

voltage (= VGG) and drain supply voltage;
typical values; see Fig.27.

12

handbook, halfpage

I

D

(mA)

8

4

0

024 1086

VDS= 9 V; V
RG1= 180 kΩ (connected to VGG); Tj=25°C.

G2-S

=4V.

MLD165

V (V)

GG

Fig.13 Drain current as a function of gate 1 voltage

(= VGG); typical values; see Fig.27.

12

handbook, halfpage

I

D

(mA)

8

4

0

04812

VDS= 12 V; V
RG1= 250 kΩ (connected to VGG); Tj=25°C.

G2-S

=4V.

MLD166

V (V)

GG

Fig.14 Drain current as a function of gate 1 voltage;

(= VGG); typical values; see Fig.27.

NXP Semiconductors Product specification

Rev. 02 - 13 November 2007

8 of 15

Dual-gate MOS-FETs BF1100; BF1100R

50

handbook, halfpage

I

G1

(µA)

40

30

20

10

0

0246

VDS=9V.
RG1= 180 kΩ (connected to VGG).
Tj=25°C.

MLD167

V = 9 V

GG

8 V
7 V

6 V
5 V
4 V

V (V)

G2 S

Fig.15 Gate 1 current as a function of gate 2 voltage;

typical values.

50

handbook, halfpage

I

G1

(µA)

40

30

20

10

0

0246

VDS=12V.
RG1= 250 kΩ (connected to VGG).
Tj=25°C.

MLD168

V = 12 V

GG

11 V
10 V

9 V
8 V
7 V

V (V)

G2 S

Fig.16 Gate 1 current as a function of gate 2 voltage;

typical values.

16

handbook, halfpage

I

D

(mA)

12

8

4

0

0246

VDS=9V.
RG1= 180 kΩ (connected to VGG).
Tj=25°C.

V = 9 V

GG

V (V)

G2 S

Fig.17 Drain current as a function of the gate 2

voltage; typical values; see Fig.27.

MLD169

8 V
7 V
6 V

5 V
4 V

16

handbook, halfpage

I

D

(mA)

12

8

4

0

0246

VDS=12V.
RG1= 250 kΩ (connected to VGG).
Tj=25°C.

V = 12 V

GG

V (V)

G2 S

Fig.18 Drain current as a function of the gate 2

voltage; typical values; see Fig.27.

MLD170

11 V
10 V

9 V
8 V
7 V

NXP Semiconductors Product specification

Rev. 02 - 13 November 2007

9 of 15

Dual-gate MOS-FETs BF1100; BF1100R

2

10

handbook, halfpage

y

is

(mS)

10

1

1

10

10

VDS= 9 V; VG2=4V.
ID= 10 mA; T

amb

Fig.19 Input admittance as a function of

b

is

g

is

2

10

f (MHz)

=25°C.

frequency; typical values.

MLD172

f (MHz)

MLD173

3

10

ϕ

rs

(deg)

2

10

10

1

3

10

3

10

y

rs

(µS)

ϕ

2

10

rs

y

rs

10

3

10

1

10

2

10

VDS= 9 V; VG2=4V.
ID= 10 mA; T

amb

=25°C.

Fig.20 Reverse transfer admittance and phase as

a function of frequency; typical values.

MLD174

3

10

y

(mS)

2

10

fs

10

1

10

y

fs

ϕ

fs

2

10

f (MHz)

VDS= 9 V; VG2=4V.
ID= 10 mA; T

amb

=25°C.

Fig.21 Forward transfer admittance and phase as

a function of frequency; typical values.

10

ϕ

(deg)

10

1

2

fs

10

handbook, halfpage

y

os

(mS)

b

os

MLD175

1

1

10

g

os

2

10

10

2

10

f (MHz)

3

10

VDS= 9 V; VG2=4V.
ID=10 mA; T

amb

=25°C.

Fig.22 Output admittance as a function of

frequency; typical values.

NXP Semiconductors Product specification

Rev. 02 - 13 November 2007

10 of 15

Dual-gate MOS-FETs BF1100; BF1100R

2

10

handbook, halfpage

y

is

(mS)

10

1

1

10

10

VDS= 12 V; VG2=4V.
ID= 10 mA; T

amb

Fig.23 Input admittance as a function of

b

is

g

is

2

10

f (MHz)

=25°C.

frequency; typical values.

MLD176

f (MHz)

MLD177

3

10

ϕ

rs

(deg)

2

10

10

1

3

10

3

10

y

rs

(µS)

ϕ

2

10

rs

y

rs

10

3

10

1

10

2

10

VDS= 12 V; VG2=4V.
ID= 10 mA; T

amb

=25°C.

Fig.24 Reverse transfer admittance and phase as

a function of frequency; typical values.

MLD178

3

10

y

fs

(mS)

2

10

y

fs

10

1

10

ϕ

fs

2

10

f (MHz)

VDS= 12 V; VG2=4V.
ID= 10 mA; T

amb

=25°C.

Fig.25 Forward transfer admittance and phase as

a function of frequency; typical values.

10

ϕ

(deg)

10

1

f (MHz)

MLD179

3

10

2

fs

10

handbook, halfpage

y

os

(mS)

1

1

10

2

10

10

b

os

g

os

2

10

VDS= 12 V; VG2=4V.
ID= 10 mA; T

amb

=25°C.

Fig.26 Output admittance as a function of

frequency; typical values.

NXP Semiconductors Product specification

Rev. 02 - 13 November 2007

11 of 15

Dual-gate MOS-FETs BF1100; BF1100R

V

R1

10 kΩ

AGC

C1

handbook, full pagewidth

For VGG=VDS= 9 V, RG= 180 kΩ.
For VGG=VDS= 12 V, RG= 250 kΩ.

R

GEN

50

4.7 nF

C2

4.7 nF

R2

50

Ω

V

I

Ω

R

G

V

GG

DUT

V

DS

C3 12 pF

L1

450 nH

≈

C4

4.7 nF

R

50 Ω

MGC420

L

Fig.27 Cross-modulation test set-up.

NXP Semiconductors Product specification

Rev. 02 - 13 November 2007

12 of 15

Dual-gate MOS-FETs BF1100; BF1100R

Table 1 Scattering parameters: VDS= 9 V; V

s

f

(MHz)

MAGNITUDE

(ratio)

11

ANGLE

(deg)

MAGNITUDE

(ratio)

= 4 V; ID=10mA

G2-S

s

21

ANGLE

(deg)

s

MAGNITUDE

(ratio)

12

ANGLE

(deg)

s

22

MAGNITUDE

(ratio)

ANGLE

(deg)

50 0.986 −3.6 2.528 174.4 0.001 63.7 1.000 −2.0
100 0.983 −7.4 2.531 169.8 0.001 80.7 1.000 −4.2
200 0.974 −14.7 2.490 159.5 0.002 81.0 0.996 −8.1
300 0.960 −21.8 2.446 149.8 0.002 80.3 0.994 −11.9
400 0.953 −28.7 2.412 139.8 0.003 76.3 0.992 −15.7
500 0.933 −35.4 2.341 130.1 0.003 76.5 0.987 −19.4
600 0.915 −42.0 2.283 120.4 0.004 79.0 0.984 −23.0
700 0.895 −47.9 2.205 111.6 0.003 81.5 0.981 −26.7
800 0.880 −53.5 2.146 102.9 0.003 90.8 0.978 −30.3
900 0.864 −59.6 2.087 93.4 0.003 106.6 0.974 −33.9

1000 0.839 −65.0 1.998 84.4 0.003 135.4 0.971 −37.6

Table 2 Noise data: V

f

(MHz)

= 9 V; V

DS

= 4 V; ID=10mA

G2-S

F

min

(dB)

Γ

opt

(ratio) (deg)

r

n

800 2.00 0.67 43.9 0.89

Table 3 Scattering parameters: V

s

f

(MHz)

MAGNITUDE

(ratio)

11

ANGLE

(deg)

= 12 V; V

DS

MAGNITUDE

(ratio)

= 4 V; ID=10mA

G2-S

s

21

ANGLE

(deg)

s

MAGNITUDE

(ratio)

12

ANGLE

(deg)

s

22

MAGNITUDE

(ratio)

ANGLE

(deg)

50 0.986 −3.7 2.478 174.7 0.001 72.2 1.000 −1.6
100 0.984 −7.4 2.480 170.3 0.001 80.9 1.000 −3.5
200 0.974 −14.6 2.440 160.6 0.002 82.7 0.997 −6.6
300 0.960 −21.8 2.400 151.4 0.002 79.9 0.996 −9.7
400 0.953 −28.7 2.371 141.9 0.003 77.7 0.994 −12.8
500 0.933 −35.3 2.306 132.7 0.003 77.1 0.991 −15.8
600 0.915 −41.9 2.255 123.6 0.004 77.1 0.989 −18.7
700 0.894 −47.8 2.183 115.3 0.004 79.3 0.986 −21.7
800 0.879 −53.5 2.131 107.2 0.003 83.9 0.984 −24.6
900 0.863 −59.5 2.080 98.2 0.003 95.1 0.982 −27.5

1000 0.838 −65.0 1.999 89.7 0.003 115.8 0.980 −30.4

Table 4 Noise data: V

f

(MHz)

= 12 V; V

DS

= 4 V; ID=10mA

G2-S

F

min

(dB)

Γ

opt

(ratio) (deg)

r

n

800 2.00 0.66 43.3 0.97

NXP Semiconductors Product specification

Rev. 02 - 13 November 2007

13 of 15

Dual-gate MOS-FETs BF1100; BF1100R

PACKAGE OUTLINES

handbook, full pagewidth

Dimensions in mm.

10

max

3.0

0.150

30

max

0.090

0.1

max

10

max

o

o

0.88

0.75

0.60

o

1.1

max

2.8

1.9

43

2

1

0

0.1

TOP VIEW

0.48

1.7

0

0.1

B

A

1.4

1.2

M0.1 AB

2.5

max

0.2

MBC845

M

AB

Fig.28 SOT143.

handbook, full pagewidth

Dimensions in mm.

0.40

0.25

10

max

3.0

0.150

0.090

30

max

o

0.1

max

10

max

o

0.48

0.38

o

1.1

max

2.8

1.9

34

2

1

0.88

0.78

1.7

M0.1 B

TOP VIEW

B

A

1.4

1.2

MBC844

2.5

max

0.2

A

M

Fig.29 SOT143R.

NXP Semiconductors

Rev. 02 - 13 November 2007

14 of 15

Legal information

Data sheet status

BF1100; BF1100R

Dual-gate MOS-FETs

Document status

Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.

[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document waspublishedandmaydifferincaseofmultiple devices.Thelatest product status

information is available on the Internet at URL

[1][2]

Product status

Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall haveno liability for the consequencesof
use of such information.

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with the same product type number(s) and title. A short data sheet is intended
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sheet, which is available on request via the local NXP Semiconductors sales
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Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give anyrepresentations or
warranties, expressed or implied, as to the accuracyor completeness of such
information and shall have no liability for the consequences of use of such
information.

Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.

Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or

[3]

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Definition

malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.

Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may causepermanent
damage to the device.Limiting values are stress ratingsonly and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published

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at
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.

No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.

Trademarks

Notice: All referenced brands, product names, servicenamesandtrademarks
are the property of their respective owners.

Contact information

For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: [email protected]

NXP Semiconductors

BF1100; BF1100R

Dual-gate MOS-FETs

Revision history

Revision history

Document ID Release date Data sheet status Change notice Supersedes

BF1100_N_2 20071113 Product data sheet - BF1100_1
Modifications:
BF1100_1 19950425 Product specification - -

• Fig. 1 and 2 on page 2; Figure note changed

Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.

© NXP B.V. 2007. All rights reserved.

For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]

Date of release: 13 November 2007

Document identifier: BF1100_N_2