Philips BDL5231V Schematic

Colour Television Chassis

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Contents Page Contents Page

1. Revision List 2

2. Technical Specifications, Connections, and Chassis
Overview 2

3. Precautions, Notes, and Abbreviation List 5

4. Mechanical Instructions 9

5. Service Modes, Error Codes, and Fault Finding 13

6. Alignments 17

7. Circuit Descriptions 22

8. IC Data Sheets 24

9. Block Diagrams, Test Point Overview
Wiring Diagram 52" 37

10. Circuit Diagrams and PWB Layouts
Main Board: HDMI Input 38
Main Board: DVI Input 39
Main Board: HDMI In Sequoia 40
Main Board: Display Port Input 41
Main Board: Digital Input Port 42
Main Board: VGA Input 43
Main Board: ISP 44
Main Board: AFE Sequoia 45
Main Board: Frame Store DDR interface 46
Main Board: Panel Interface Sequoia 47
Main Board: Panel Interface 48
Main Board: I2S Audio Input 49
Main Board: Analog Audio Input 50
Main Board: Low Power Monitor 51
Main Board: Sequoia Power 52
Main Board: OCM Peripherals 53
Main Board: OCM Low Bandwidth ADC 54
Main Board: Power Sequoia 55
Main Board: Power System 56
Main Board: SMCU 57
Main Board: Board to board connect 58
Extension Board: Video input 59

©

Copyright 2009 Koninklijke Philips Electronics N.V.
All rights reserved. No part of this publication may be reproduced, stored in a
retrieval system or transmitted, in any form or by any means, electronic, mechanical,
photocopying, or otherwise without the prior permission of Philips.

Extension Board: Analog input 60
Extension Board: Analog output 61
Extension Board: Board to board connect 62
Extension Board: Audio input 63
Extension Board: Audio amplifier 64
Extension Board: Speaker switch 65
Extension Board: RS232 66
Extension Board: GP IO and power 67
Extension Board: Fan control; RTC 68
Extension Board: PC power 69
IR LED board 70

Published by MB/JH 0963 BU TV Consumer Care, the Netherlands Subject to modification EN 3122 785 18431

2009-Mar-20

EN 2 QCG1.0S LA1.

Revision List

1. Revision List

Manual xxxx xxx xxxx.0

• First release.

Manual xxxx xxx xxxx.1

• Chapter 5 added section Fault Finding

.

2. Technical Specifications, Connections, and Chassis Overview

Index of this chapter:

2.1 Technical Specifications

2.2 Directions for Use

2.3 Connection Overview

2.4 Chassis Overview

Notes:

• Data below can deviate slightly from the actual situation,
due to the different set executions

• Specifications are indicative (subject to change).

2.1 Technical Specifications

For on-line product support please use the links in. Here is
product information available, as well as getting started, user
manuals, frequently asked questions and software & drivers.

Table 2-1 Described Model Numbers:

Model Number Styling Published in

BDL5231V/00

3122 785 18430

2.2 Directions for Use

You can download this information from the following websites:

http://www.philips.com/support
http://www.p4c.philips.com

2009-Mar-20

Technical Specifications, Connections, and Chassis Overview

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2.3 Connection Overview

EN 3QCG1.0S LA 2.

Note: The following connector colour abbreviations are used

(acc. to DIN/IEC 757): Bk = Black, Bu = Blue, Gn = Green,
Gy = Grey, Rd = Red, Wh = White, and Ye = Yellow.

2.3.1 Side Connections

1 - External Control Connector (RS232-UART) Out - In

Figure 2-2 9-pin Sub-D Connector

1 -DCD Carrier Detect j
2 -RxD Receive j
3-TxD Transmit k
4 -DTR Data Terminal Ready k
5 -Gnd Ground H
6 -DSR Data Set Ready j
7 -RTS Request To Send k
8 -CTS Clear To Send j
9 -RI Ring Indicator j

2 - Mini Jack: Audio IN1 - In

Wh - Audio L 0.5 V
Rd - Audio R 0.5 V

/ 10 kΩ jq

RMS

/ 10 kΩ jq

RMS

2 - Cinch: Audio IN 2 & 3 - In

Wh - Audio L 0.5 V
Rd - Audio R 0.5 V

/ 10 kΩ jq

RMS

/ 10 kΩ jq

RMS

3 - Cinch: Audio - Out

Rd - Audio - R 0.5 V
Wh - Audio - L 0.5 V

/ 10 kΩ kq

RMS

/ 10 kΩ kq

RMS

Figure 2-1 Rear and Side I/O connections

4 - Spring Clip Speaker Connections: Audio - Out

Figure 2-3 Spring Clip Speaker Terminals

Bk - Speaker Left Gnd H
Rd - Speaker Left 5 W / 8 Ω j
Bk - Speaker Right Gnd H
Rd - Speaker Right 5 W / 8 Ω j

2.3.2 Rear Connections

5 - IEC C14 MAINS socket - In

L - Phase Power j
E - Earth Gnd H
3 - Zero Power j

6 - HDMI: Digital Video, Digital Audio - In

Figure 2-4 IEC C14 Mains socket

Figure 2-5 HDMI (type A) connector

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Technical Specifications, Connections, and Chassis Overview

1 - D2+ Data channel j
2 - Shield Gnd H
3 - D2- Data channel j
4 - D1+ Data channel j
5 - Shield Gnd H
6 - D1- Data channel j
7 - D0+ Data channel j
8 - Shield Gnd H
9 - D0- Data channel j
10 - CLK+ Data channel j
11 - Shield Gnd H
12 - CLK- Data channel j
13 - n.c.
14 - n.c.
15 - DDC_SCL DDC clock j
16 - DDC_SDA DDC data jk
17 - Ground Gnd H
18 - +5V j
19 - HPD Hot Plug Detect j
20 - Ground Gnd H

7 - DVI-D: Digital Video - In

1 8
916

17

C5

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Figure 2-6 DVI-D connector

1-D2- j
2-D2+ j
3 - Shield Gnd H
4-D4- j
5-D4+ j
6 - DDC_SCL DDC clock k
7 - DDC_SDA DDC data jk
8-n.c.
9-D1- j
10 - D1+ j
11 - Shield Gnd H
12 - D3- j
13 - D3+ j
14 - +5V j
15 - Ground Gnd H
16 - HPD Hot Plug Detect j
17 - D0- j
18 - D0+ j
19 - Shield Gnd H
20 - D5- j
21 - D5+ j
22 - Shield Gnd H
23 - CLK+ j
24 - CLK- j

8 - VGA RGB 3 & RGB IN: Video RGB - In

Figure 2-7 VGA Connector

1 - Video Red 0.7 V
2 - Video Green 0.7 V
3 - Video Blue 0.7 V
4-n.c.

/ 75 Ω j

PP

/ 75 Ω j

PP

/ 75 Ω j

PP

5 - Ground Gnd H
6 - Ground Red Gnd H
7 - Ground Green Gnd H
8 - Ground Blue Gnd H
9-+5V
10 - Ground Sync Gnd H

+5 V jk

DC

11 - n.c.
12 - DDC_SDA DDC data jk
13 - H-sync 0 - 5 V j
14 - V-sync 0 - 5 V j
15 - DDC_SCL DDC clock jk

9 - VGA RGB 3 & RGB OUT: Video RGB - Out

1 - Video Red 0.7 V
2 - Video Green 0.7 V
3 - Video Blue 0.7 V

/ 75 Ω k

PP

/ 75 Ω k

PP

/ 75 Ω k

PP

4-n.c.
5 - Ground Gnd H
6 - Ground Red Gnd H
7 - Ground Green Gnd H
8 - Ground Blue Gnd H
9-+5V

+5 V jk

DC

10 - Ground Sync Gnd H
11 - n.c.
12 - DDC_SDA DDC data jk
13 - H-sync 0 - 5 V k
14 - V-sync 0 - 5 V k
15 - DDC_SCL DDC clock jk

10 - BNC: Video YPbPr - In

Wh - Video Y 1 V
Wh - Video Pb 0.7 V
Wh - Video Pr 0.7 V

/ 75 Ω jq

PP

/ 75 Ω jq

PP

/ 75 Ω jq

PP

11 - Cinch: Composite Video CVBS - In

Ye - Video CVBS 1 V

/ 75 Ω jq

PP

11 - S-Video (Hosiden): Composite Video Y/C - In

1 - Ground Y Gnd H
2 - Ground C Gnd H
3 - Video Y 1 V
4 - Video C 0.3 V

/ 75 Ω j

PP

P / 75 Ω j

PP

2.4 Chassis Overview

Refer to chapter 9. Block Diagrams, Test Point Overview for
PWB/CBA locations.

2009-Mar-20

11 - BNC: Composite Video CVBS - In

Wh - Video CVBS 1 V

/ 75 Ω jq

PP

11 - BNC: Composite Video CVBS - Out

Wh - Video CVBS 1 V

/ 75 Ω kq

PP

Precautions, Notes, and Abbreviation List

3. Precautions, Notes, and Abbreviation List

EN 5QCG1.0S LA 3.

Index of this chapter:

3.1 Safety Instructions

3.2 Warnings

3.3 Notes

3.4 Abbreviation List

3.1 Safety Instructions

Safety regulations require the following during a repair:

• Connect the set to the Mains/AC Power via an isolation
transformer (> 800 VA).

• Replace safety components, indicated by the symbol h,
only by components identical to the original ones. Any
other component substitution (other than original type) may
increase risk of fire or electrical shock hazard. Of de set
ontploft!

Safety regulations require that after a repair, the set must be
returned in its original condition. Pay in particular attention to
the following points:

• Route the wire trees correctly and fix them with the
mounted cable clamps.

• Check the insulation of the Mains/AC Power lead for
external damage.

• Check the strain relief of the Mains/AC Power cord for
proper function.

• Check the electrical DC resistance between the Mains/AC
Power plug and the secondary side (only for sets that have
a Mains/AC Power isolated power supply):

1. Unplug the Mains/AC Power cord and connect a wire

between the two pins of the Mains/AC Power plug.

2. Set the Mains/AC Power switch to the “on” position

(keep the Mains/AC Power cord unplugged!).

3. Measure the resistance value between the pins of the

Mains/AC Power plug and the metal shielding of the
tuner or the aerial connection on the set. The reading
should be between 4.5 MΩ and 12 MΩ.

4. Switch “off” the set, and remove the wire between the

two pins of the Mains/AC Power plug.

• Check the cabinet for defects, to prevent touching of any
inner parts by the customer.

picture carrier at 475.25 MHz for PAL, or 61.25 MHz for
NTSC (channel 3).

• Where necessary, measure the waveforms and voltages

with (D) and without (E) aerial signal. Measure the
voltages in the power supply section both in normal
operation (G) and in stand-by (F). These values are
indicated by means of the appropriate symbols.

3.3.2 Schematic Notes

• All resistor values are in ohms, and the value multiplier is
often used to indicate the decimal point location (e.g. 2K2
indicates 2.2 kΩ).

• Resistor values with no multiplier may be indicated with
either an “E” or an “R” (e.g. 220E or 220R indicates 220 Ω).

• All capacitor values are given in micro-farads (μ=× 10
nano-farads (n =× 10

• Capacitor values may also use the value multiplier as the
decimal point indication (e.g. 2p2 indicates 2.2 pF).

• An “asterisk” (*) indicates component usage varies. Refer
to the diversity tables for the correct values.

• The correct component values are listed on the Philips
Spare Parts Web Portal.

3.3.3 Spare Parts

For the latest spare part overview, consult your Philips Spare
Part web portal.

3.3.4 BGA (Ball Grid Array) ICs

Introduction

For more information on how to handle BGA devices, visit this
URL: http://www.atyourservice-magazine.com
“Magazine”, then go to “Repair downloads”. Here you will find
Information on how to deal with BGA-ICs.

BGA Temperature Profiles

For BGA-ICs, you must use the correct temperature-profile.
Where applicable and available, this profile is added to the IC
Data Sheet information section in this manual.

-9

), or pico-farads (p =× 10

. Select

-12

-6

),

).

3.2 Warnings

• All ICs and many other semiconductors are susceptible to

electrostatic discharges (ESD w). Careless handling
during repair can reduce life drastically. Make sure that,
during repair, you are connected with the same potential as
the mass of the set by a wristband with resistance. Keep
components and tools also at this same potential.

• Be careful during measurements in the high voltage
section.

• Never replace modules or other components while the unit
is switched “on”.

• When you align the set, use plastic rather than metal tools.
This will prevent any short circuits and the danger of a
circuit becoming unstable.

3.3 Notes

3.3.1 General

• Measure the voltages and waveforms with regard to the
chassis (= tuner) ground (H), or hot ground (I), depending
on the tested area of circuitry. The voltages and waveforms
shown in the diagrams are indicative. Measure them in the
Service Default Mode with a colour bar signal and stereo
sound (L: 3 kHz, R: 1 kHz unless stated otherwise) and

3.3.5 Lead-free Soldering

Due to lead-free technology some rules have to be respected
by the workshop during a repair:

• Use only lead-free soldering tin. If lead-free solder paste is
required, please contact the manufacturer of your soldering
equipment. In general, use of solder paste within
workshops should be avoided because paste is not easy to
store and to handle.

• Use only adequate solder tools applicable for lead-free
soldering tin. The solder tool must be able:
– To reach a solder-tip temperature of at least 400°C.
– To stabilize the adjusted temperature at the solder-tip.
– To exchange solder-tips for different applications.

• Adjust your solder tool so that a temperature of around
360°C - 380°C is reached and stabilized at the solder joint.
Heating time of the solder-joint should not exceed ~ 4 sec.
Avoid temperatures above 400°C, otherwise wear-out of
tips will increase drastically and flux-fluid will be destroyed.
To avoid wear-out of tips, switch “off” unused equipment or
reduce heat.

• Mix of lead-free soldering tin/parts with leaded soldering
tin/parts is possible but PHILIPS recommends strongly to
avoid mixed regimes. If this cannot be avoided, carefully
clear the solder-joint from old tin and re-solder with new tin.

2009-Mar-20

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PROD.NO:

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MADE IN BELGIUM

220-240V 50/60Hz

128W

AG 1A0617 000001

VHF+S+H+UHF

BJ3.0E LA

Precautions, Notes, and Abbreviation List

3.3.6 Alternative BOM identification

It should be noted that on the European Service website,
“Alternative BOM” is referred to as “Design variant”.

The third digit in the serial number (example:
AG2B0335000001) indicates the number of the alternative
B.O.M. (Bill Of Materials) that has been used for producing the
specific TV set. In general, it is possible that the same TV
model on the market is produced with e.g. two different types
of displays, coming from two different suppliers. This will then
result in sets which have the same CTN (Commercial Type
Number; e.g. 28PW9515/12) but which have a different B.O.M.
number.
By looking at the third digit of the serial number, one can
identify which B.O.M. is used for the TV set he is working with.
If the third digit of the serial number contains the number “1”
(example: AG1B033500001), then the TV set has been
manufactured according to B.O.M. number 1. If the third digit is
a “2” (example: AG2B0335000001), then the set has been
produced according to B.O.M. no. 2. This is important for
ordering the correct spare parts!
For the third digit, the numbers 1...9 and the characters A...Z
can be used, so in total: 9 plus 26= 35 different B.O.M.s can be
indicated by the third digit of the serial number.

Identification: The bottom line of a type plate gives a 14-digit
serial number. Digits 1 and 2 refer to the production centre (e.g.
AG is Bruges), digit 3 refers to the B.O.M. code, digit 4 refers
to the Service version change code, digits 5 and 6 refer to the
production year, and digits 7 and 8 refer to production week (in
example below it is 2006 week 17). The 6 last digits contain the
serial number.

Figure 3-1 Serial number (example)

3.3.7 Board Level Repair (BLR) or Component Level Repair (CLR)

If a board is defective, consult your repair procedure to decide
if the board has to be exchanged or if it should be repaired on
component level.
If your repair procedure says the board should be exchanged
completely, do not solder on the defective board. Otherwise, it
cannot be returned to the O.E.M. supplier for back charging!

3.3.8 Practical Service Precautions

• It makes sense to avoid exposure to electrical shock.

While some sources are expected to have a possible
dangerous impact, others of quite high potential are of
limited current and are sometimes held in less regard.

• Always respect voltages. While some may not be

dangerous in themselves, they can cause unexpected
reactions that are best avoided. Before reaching into a
powered TV set, it is best to test the high voltage insulation.
It is easy to do, and is a good service precaution.

2009-Mar-20

3.4 Abbreviation List

0/6/12 SCART switch control signal on A/V

board. 0 = loop through (AUX to TV),
6 = play 16 : 9 format, 12 = play 4 : 3

format
2DNR Spatial (2D) Noise Reduction
3DNR Temporal (3D) Noise Reduction
AARA Automatic Aspect Ratio Adaptation:

algorithm that adapts aspect ratio to

remove horizontal black bars; keeps

the original aspect ratio
ACI Automatic Channel Installation:

algorithm that installs TV channels

directly from a cable network by

means of a predefined TXT page
ADC Analogue to Digital Converter
AFC Automatic Frequency Control: control

signal used to tune to the correct

frequency
AGC Automatic Gain Control: algorithm that

controls the video input of the feature

box
AM Amplitude Modulation
ANR Automatic Noise Reduction: one of the

algorithms of Auto TV
AP Asia Pacific
AR Aspect Ratio: 4 by 3 or 16 by 9
ASF Auto Screen Fit: algorithm that adapts

aspect ratio to remove horizontal black

bars without discarding video

information
ATSC Advanced Television Systems

Committee, the digital TV standard in

the USA
ATV See Auto TV
Auto TV A hardware and software control

system that measures picture content,

and adapts image parameters in a

dynamic way
AV External Audio Video
AVC Audio Video Controller
AVIP Audio Video Input Processor
B/G Monochrome TV system. Sound

carrier distance is 5.5 MHz
BLR Board-Level Repair
BTSC Broadcast Television Standard

Committee. Multiplex FM stereo sound

system, originating from the USA and

used e.g. in LATAM and AP-NTSC

countries
B-TXT Blue TeleteXT
C Centre channel (audio)
CEC Consumer Electronics Control bus:

remote control bus on HDMI

connections
CL Constant Level: audio output to

connect with an external amplifier
CLR Component Level Repair
COLUMBUS COlor LUMinance Baseband

Universal Sub-system
ComPair Computer aided rePair
CP Connected Planet / Copy Protection
CSM Customer Service Mode
CTI Color Transient Improvement:

manipulates steepness of chroma

transients
CVBS Composite Video Blanking and

Synchronization
DAC Digital to Analogue Converter
DBE Dynamic Bass Enhancement: extra

low frequency amplification
DDC See “E-DDC”

Precautions, Notes, and Abbreviation List

EN 7QCG1.0S LA 3.

D/K Monochrome TV system. Sound

carrier distance is 6.5 MHz
DFI Dynamic Frame Insertion
DFU Directions For Use: owner's manual
DMR Digital Media Reader: card reader
DMSD Digital Multi Standard Decoding
DNM Digital Natural Motion
DNR Digital Noise Reduction: noise

reduction feature of the set
DRAM Dynamic RAM
DRM Digital Rights Management
DSP Digital Signal Processing
DST Dealer Service Tool: special remote

control designed for service

technicians
DTCP Digital Transmission Content

Protection; A protocol for protecting

digital audio/video content that is

traversing a high speed serial bus,

such as IEEE-1394
DVB-C Digital Video Broadcast - Cable
DVB-T Digital Video Broadcast - Terrestrial
DVD Digital Versatile Disc
DVI(-d) Digital Visual Interface (d= digital only)
E-DDC Enhanced Display Data Channel

(VESA standard for communication

channel and display). Using E-DDC,

the video source can read the EDID

information form the display.
EDID Extended Display Identification Data

(VESA standard)
EEPROM Electrically Erasable and

Programmable Read Only Memory
EMI Electro Magnetic Interference
EPLD Erasable Programmable Logic Device
EU Europe
EXT EXTernal (source), entering the set by

SCART or by cinches (jacks)
FBL Fast BLanking: DC signal

accompanying RGB signals
FDS Full Dual Screen (same as FDW)
FDW Full Dual Window (same as FDS)
FLASH FLASH memory
FM Field Memory or Frequency

Modulation
FPGA Field-Programmable Gate Array
FTV Flat TeleVision
Gb/s Giga bits per second
G-TXT Green TeleteXT
H H_sync to the module
HD High Definition
HDD Hard Disk Drive
HDCP High-bandwidth Digital Content

Protection: A “key” encoded into the

HDMI/DVI signal that prevents video

data piracy. If a source is HDCP coded

and connected via HDMI/DVI without

the proper HDCP decoding, the

picture is put into a “snow vision” mode

or changed to a low resolution. For

normal content distribution the source

and the display device must be

enabled for HDCP “software key”

decoding.
HDMI High Definition Multimedia Interface
HP HeadPhone
I Monochrome TV system. Sound

2

I

C Inter IC bus

2

I

D Inter IC Data bus

2

I

S Inter IC Sound bus

carrier distance is 6.0 MHz

IF Intermediate Frequency
Interlaced Scan mode where two fields are used

to form one frame. Each field contains

half the number of the total amount of

lines. The fields are written in “pairs”,

causing line flicker.
IR Infra Red
IRQ Interrupt Request
ITU-656 The ITU Radio communication Sector

(ITU-R) is a standards body

subcommittee of the International

Telecommunication Union relating to

radio communication. ITU-656 (a.k.a.

SDI), is a digitized video format used

for broadcast grade video.

Uncompressed digital component or

digital composite signals can be used.

The SDI signal is self-synchronizing,

uses 8 bit or 10 bit data words, and has

a maximum data rate of 270 Mbit/s,

with a minimum bandwidth of 135

MHz.
ITV Institutional TeleVision; TV sets for

hotels, hospitals etc.
JOP Jaguar Output Processor
LS Last Status; The settings last chosen

by the customer and read and stored

in RAM or in the NVM. They are called

at start-up of the set to configure it

according to the customer's

preferences
LATAM Latin America
LCD Liquid Crystal Display
LED Light Emitting Diode
L/L' Monochrome TV system. Sound

carrier distance is 6.5 MHz. L' is Band

I, L is all bands except for Band I
LORE LOcal REgression approximation

noise reduction
LPL LG.Philips LCD (supplier)
LS Loudspeaker
LVDS Low Voltage Differential Signalling
Mbps Mega bits per second
M/N Monochrome TV system. Sound

carrier distance is 4.5 MHz
MIPS Microprocessor without Interlocked

Pipeline-Stages; A RISC-based

microprocessor
MOP Matrix Output Processor
MOSFET Metal Oxide Silicon Field Effect

Transistor, switching device
MPEG Motion Pictures Experts Group
MPIF Multi Platform InterFace
MUTE MUTE Line
NC Not Connected
NICAM Near Instantaneous Compounded

Audio Multiplexing. This is a digital

sound system, mainly used in Europe.
NTC Negative Temperature Coefficient,

non-linear resistor
NTSC National Television Standard

Committee. Color system mainly used

in North America and Japan. Color

carrier NTSC M/N= 3.579545 MHz,

NTSC 4.43= 4.433619 MHz (this is a

VCR norm, it is not transmitted off-air)
NVM Non-Volatile Memory: IC containing

TV related data such as alignments
O/C Open Circuit
OSD On Screen Display
OTC On screen display Teletext and

Control; also called Artistic (SAA5800)
P50 Project 50: communication protocol

between TV and peripherals
PAL Phase Alternating Line. Color system

mainly used in West Europe (color

carrier= 4.433619 MHz) and South

America (color carrier PAL M=

2009-Mar-20

EN 8 QCG1.0S LA3.

Precautions, Notes, and Abbreviation List

3.575612 MHz and PAL N= 3.582056

MHz)
PCB Printed Circuit Board (same as “PWB”)
PCM Pulse Code Modulation
PDP Plasma Display Panel
PFC Power Factor Corrector (or Pre-

conditioner)
PIP Picture In Picture
PLL Phase Locked Loop. Used for e.g.

FST tuning systems. The customer

can give directly the desired frequency
POD Point Of Deployment: a removable

CAM module, implementing the CA

system for a host (e.g. a TV-set)
POR Power On Reset, signal to reset the uP
Progressive Scan Scan mode where all scan lines are

displayed in one frame at the same

time, creating a double vertical

resolution.
PTC Positive Temperature Coefficient,

non-linear resistor
PWB Printed Wiring Board (same as “PCB”)
PWM Pulse Width Modulation
QRC Quasi Resonant Converter
QTNR Quality Temporal Noise Reduction
QVCP Quality Video Composition Processor
RAM Random Access Memory
RGB Red, Green, and Blue. The primary

color signals for TV. By mixing levels

of R, G, and B, all colors (Y/C) are

reproduced.
RC Remote Control
RC5 / RC6 Signal protocol from the remote

control receiver
RESET RESET signal
ROM Read Only Memory
RSDS Reduced Swing Differential Signalling

data interface
R-TXT Red TeleteXT
SAM Service Alignment Mode
S/C Short Circuit
SCART Syndicat des Constructeurs

d'Appareils Radiorécepteurs et

Téléviseurs
SCL Serial Clock I
SCL-F CLock Signal on Fast I
SD Standard Definition
SDA Serial Data I
SDA-F DAta Signal on Fast I

2

C

2

C bus

2

C

2

C bus
SDI Serial Digital Interface, see “ITU-656”
SDRAM Synchronous DRAM
SECAM SEequence Couleur Avec Mémoire.

Color system mainly used in France
and East Europe. Color carriers=

4.406250 MHz and 4.250000 MHz
SIF Sound Intermediate Frequency
SMPS Switched Mode Power Supply
SoC System on Chip
SOG Sync On Green
SOPS Self Oscillating Power Supply
SPI Serial Peripheral Interface bus; a 4-

wire synchronous serial data link

standard
S/PDIF Sony Philips Digital InterFace
SRAM Static RAM
SRP Service Reference Protocol
SSB Small Signal Board
STBY STand-BY
SVGA 800x600 (4:3)
SVHS Super Video Home System
SW Software
SWAN Spatial temporal Weighted Averaging

Noise reduction
SXGA 1280x1024
TFT Thin Film Transistor

THD Total Harmonic Distortion
TMDS Transmission Minimized Differential

Signalling
TXT TeleteXT
TXT-DW Dual Window with TeleteXT
UI User Interface
uP Microprocessor
UXGA 1600x1200 (4:3)
V V-sync to the module
VCR Video Cassette Recorder
VESA Video Electronics Standards

Association
VGA 640x480 (4:3)
VL Variable Level out: processed audio

output toward external amplifier
VSB Vestigial Side Band; modulation

method
WYSIWYR What You See Is What You Record:

record selection that follows main

picture and sound
WXGA 1280x768 (15:9)
XTAL Quartz crystal
XGA 1024x768 (4:3)
Y Luminance signal
Y/C Luminance (Y) and Chrominance (C)

signal
YPbPr Component video. Luminance and

scaled color difference signals (B-Y

and R-Y)
YUV Component video

2009-Mar-20

4. Mechanical Instructions

10000_018_090121.eps

090121

1

Required for sets

42"

1

Mechanical Instructions

EN 9QCG1.0S LA 4.

Index of this chapter:

4.1 Cable Dressing

4.2 Service Positions

4.3 Assy/Panel Removal

4.4 Set Re-assembly

4.1 Cable Dressing

Notes:

• Figures below can deviate slightly from the actual situation,
due to the different set executions.

• Follow the disassembly instructions in the described order.

4.2 Service Positions

When moving or laying down an LCD set, at least two people
should handle the set. Avoid any impact towards the LCD set.
For easy servicing of this set, it must be placed screen down on
Foam bars (created for Service).

4.2.1 Foam Bars

The foam bars (order code 3122 785 90580 for two pieces) can
be used for all types and sizes of Flat TVs. See Figure 4-2
details. Sets with a display of 42" and larger, require four foam
bars [1]. Ensure that the foam bars are always supporting the
cabinet and never only the display. Caution: Failure to follow
these guidelines can seriously damage the display!
By laying the TV face down on the (ESD protective) foam bars,
a stable situation is created to perform measurements and
alignments. By placing a mirror under the TV, you can monitor
the screen.

4.3 Assy/Panel Removal

4.3.1 Stands

Figure 4-1 Cable dressing

for

18430_100_090206.eps

090206

For this set separately orderable stands are available. Remove
the stands before opening the set.

Figure 4-2 Foam bars

2009-Mar-20

EN 10 QCG1.0S LA4.

Mechanical Instructions

4.3.2 Rear Cover

Warning: Disconnect the mains power cord before you open

the set.

1. Place the set in the service position, see Service Positions

2. Remove the fixing screws from the handles and remove
the handles.

3. Remove all screws from the rear cover.

4. Lift the rear cover from the cabinet.

4.3.3 Front Cover

Before removing the front cover the rear cover should already
be removed.

1. Put the set with the back down on a flat table.

2. Remove all screws that secure the front cover.

3. Gently lift the cover from the set.

4.3.4 Temperature Sensor Panel

1. Place the set in the service position, see Service Positions

2. Disconnect the connector from the panel.

3. Remove the fixation screws and take out the board.

When defective, replace the whole unit.

4.3.5 Fan

1. Place the set in the service position, see Service Positions

2. Disconnect the respective connector from the SSB.

3. Remove the fan brackets fixation screws.

4. Take out the bracket with the fan.

5. Remove the fixation screws from the fan an take the fan out
of the bracket.

When defective, replace the fan.

4.3.7 Keyboard Control Panel

1. Place the set in the service position, see Service Positions

2. Remove the fixation screws that hold the keyboard control

.

4.3.8 Power Supply Switch

4.3.9 Main Supply Panel

.

4.3.10 Speakers

.

panel.

3. Take out the panel assembly and release the connector.
When defective, replace the whole unit.

1. Place the set in the service position, see Service Positions

2. Now the clips that hold the power switch can be released
via the backside of the switch.

When defective, replace the whole unit.

1. Place the set in the service position, see Service Positions

2. Unplug connectors.

3. Remove the grounding screw and cable.

4. Remove the all other fixation screws.

5. Take the board out.

When defective, replace the whole unit.

1. Place the set in the service position, see Service Positions

2. Unplug the respective speaker connector from the SSB.

3. Release the wiring.

4. Remove the fixation screws that hold the speaker and take
it from the set.

When defective, replace the whole unit.

.

.

.

.

4.3.6 LED / IR Panel

1. Place the set in the service position, see Service Positions

2. Disconnect the connector from the rear of the panel.

3. Remove the fixation screws and take out the board.
When defective, replace the whole unit.

.

2009-Mar-20

Mechanical Instructions

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5

4 4 4 4 4 4 4 4 4 4 4

1

3

7

3

6

6

5

6

6

2

6

6

6

5

4

4

4

5

4

4

EN 11QCG1.0S LA 4.

4.3.11 Small Signal Board (SSB)

The SSB is split in two parts connected by a 60 pin connector.
The main small SSB and the bigger extension board. See

Figure 4-3

1. Do NOT forget to unplug the LVDS connector [1] from the

2. Remove the screw [2] securing and grounding the LVDS

.

SSB. Important: Be careful, as this is a very fragile
connector!

cable.

3. Unplug the other connectors [3] from the SSB.

4. Remove all screws [4] securing the SSB connectors.

5. Remove all screws [5] securing the rim and take it out.

6. Remove all other screws [6].

7. Release connector [7] that interconnects the SSB with the
extension board.

8. Lift out the SSB and the extension board separately.

When defective, replace either the SSB or extension board.

Figure 4-3 SSB removal

2009-Mar-20

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2

2

2

2

1

4

4

4

4

3

4

4

4.3.12 LCD Panel

Important: Be sure to work in a dust free environment during

the following activities. In addition, the use of (fabric) hand
gloves is advised.

Mechanical Instructions

1. First remove front cover, back cover as described earlier.

2. Place the set in the service position, see Service Positions

3. Remove the PSU as described earlier.

4. Do NOT forget to unplug the LVDS connector [1] from the
SSB. Important: Be careful, as this is a very fragile
connector!

5. Unplug the connectors from the backlight inverters [2].

6. Release connector [3] to the main power switch.

7. Release the cabling to the keyboard and the IR/LED panel.

8. Now remove all screws at the side of the surrounding rims.

9. Gently remove the rims.

10. Remove the screws [4].

11. Now gently lift the complete subframe from the LCD panel.

When defective, replace the whole unit.

4.4 Set Re-assembly

To re-assemble the whole set, execute all processes in reverse
order.

Notes:

• While re-assembling, make sure that all cables are placed
and connected in their original position. See Figure 4-1

Figure 4-4 LCD panel disassembly

.

.

2009-Mar-20

Service Modes, Error Codes, and Fault Finding

5. Service Modes, Error Codes, and Fault Finding

EN 13QCG1.0S LA 5.

Index of this chapter:

5.1 Compatibility Mode

5.2 Service Mode

5.3 Fault Finding

5.1 Compatibility Mode

This chassis does not contain specific test points, since all
defective boards should be replaced.

Perform measurements under the following conditions:

• Environmental: t

• Service signal: 100% Full White signal
This monitor saves all previously made settings, unless
separately made user settings override this. All timings must be
properly phased, sized and centred. The aspect ratio is
depending on the input signal scaled and centred. At full screen
the input timing is set to completely fill the screen, regards less
of scaling artifacts.

5.1.1 Overscan

= 25 ±2°C, RH = 65 ±10%

env

AV over scan: 5~9%
HDMI over scan: No over scan for PC input, 5~9% for video
source.
PC: No over scan

5.1.2 Display Processor performance

The display processor performance (excluding scaling
artifacts) has to be judged according to the following
definitions:

• Compatibility mode: correctly recognizes the proper
resolution and applies the correct display scaling to the
image (i.e. a 1280 × 768 signal is properly recognized).

• Properly sized/centred: The entire image (use display mate
“side tics” pattern) perfectly fits the screen. Even one pixel
off in horizontal or vertical direction, makes this test fail.

• Properly phased: The display processor automatically
computes the correct A/D response so that a Win98
shutdown or all display mate moire patterns are correctly
displayed. Most critical on the panels native mode, no
unstableness of the image may be observed.

• HD compatibility: All HD timings have to work through
YPbPr, HDMI, and RGB.

Component over scan: 5~8%

5.1.3 Compatibility

Resolution

720 × 400 85 37.9 kHz 35.500 MHz 1 920 × 1080 16 : 9 No No No Yes Yes Yes

640 × 480 60 31.5 kHz 25.175 MHz 1 920 × 1080 16 : 9 No No No Yes Yes Yes

640 × 480 72 37.9 kHz 31.500 MHz 1 920 × 1080 16 : 9 No No No Yes Yes Yes

640 × 480 75 37.5 kHz 31.500 MHz 1 920 × 1080 16 : 9 No No No Yes Yes Yes

800 × 600 56 35.1 kHz 36.000 MHz 1 920 × 1080 16 : 9 No No No Yes Yes Yes

800 × 600 60 37.9 kHz 40.000 MHz 1 920 × 1080 16 : 9 No No No Yes Yes Yes

800 × 600 72 48.1 kHz 50.000 MHz 1 920 × 1080 16 : 9 No No No Yes Yes Yes

800 × 600 75 46.9 kHz 49.500 MHz 1 920 × 1080 16 : 9 No No No Yes Yes Yes

848 × 480 60 31.0 kHz 33.750 MHz 1 920 × 1080 16 : 9 No No No Yes Yes Yes

1024× 768 60 48.4 kHz 65.000 MHz 1920 × 1 080 16 : 9 No No No Yes Yes Yes

1024× 768 70 56.5 kHz 75.000 MHz 1920 × 1 080 16 : 9 No No No Yes Yes Yes

1024× 768 75 60.0 kHz 78.750 MHz 1920 × 1 080 16 : 9 No No No Yes Yes Yes

1152× 864 75 67.5 kHz 108.000 MHz 1920 × 1 080 16 : 9 No No No Yes Yes Yes

1280× 768 60 47.4 kHz 68.250 MHz 1920 × 1 080 16 : 9 No No No Yes Yes Yes

1280× 768 60 47.8 kHz 79.500 MHz 1920 × 1080 16 : 9 No No No Yes Yes Yes

1280× 768 75 60.3 kHz 102.250 MHz 1920 × 1 080 16 : 9 No No No Yes Yes Yes

1280× 800 60 49.3 kHz 68.250 MHz 1920 × 1080 16 : 9 No No No Yes Yes Yes

1280× 800 60 49.7 kHz 79.500 MHz 1920 × 1080 16 : 9 No No No Yes Yes Yes

1280× 800 75 62.8 kHz 106.500 MHz 1 920 ×

1280× 960 60 60.0 kHz 108.000 MHz 1920 × 1 080 16 : 9 No No No Yes Yes Yes

1280× 1024 60 64.0 kHz 108.000 MHz 1 920 × 1080 16 : 9 No No No Yes Yes Yes

1280× 1024 75 80.0 kHz 135.000 MHz 1 920 × 1080 16 : 9 No No No Yes Yes Yes

1360× 768 60 47.7 kHz 85.500 MHz 1920 × 1080 16 : 9 No No No Yes Yes Yes

1366× 768 60 47.7 kHz 85.500 MHz 1920 × 1 080 16 : 9 No No No Yes Yes Yes

1400 × 1050 60 64.7 kHz 101.000 MHz 1920 × 1 080 16 : 9 No No No Yes Yes Yes

1440× 900 60 55.5 kHz 88.750 MHz 1920 × 1 080 16 : 9 No No No Yes Yes Yes

1200× 1600 60 75.0 kHz 162.000 MHz 1 920 × 1080 16 : 9 No No No Yes Yes Yes

1920× 1080 60 67.5 kHz 148.500 MHz 1920 × 1080 16 : 9 No No No Yes Yes Yes

1920× 1200 60 74.0 kHz 154.000 MHz 1 920 × 1080 16 : 9 No No No Yes Yes Yes

480i 60 60 Hz SD NTSC 1 920 × 1080 16 : 9 Yes Yes Yes No Yes No

480p 60 60 Hz ED 1 920 × 1080 16 : 9 Yes No Yes No Yes No

576i 50 50 Hz SD PAL 1920 × 1080 16 : 9 Yes Yes Yes No Yes No

576p 50 50 Hz ED 1 920 × 1080 16 : 9 Yes No Yes No Yes No

720p 50 50 Hz HD progressive 1920 × 1080 16 : 9 Yes No Yes No Yes No

720p 60 60 Hz HD progressive 1920 × 1080 16 : 9 Yes No Yes No Yes No

1080i 50 50 Hz HD interlaced 1 920 × 1080 16 : 9 Yes No Yes No Yes No

1080i 60 60 Hz HD interlaced 1 920 × 1080 16 : 9 Yes No Yes No Yes No

1080p 50 50 Hz Full HD 1920 × 1 080 16 : 9 Yes No Yes No Yes No

1080p 60 60 Hz Full HD 1920 × 1 080 16 : 9 Yes No Yes No Yes No

Refresh Rate
(Hz) Horizontal frequency Pixel Frequency

Aspect Ratio Handling

Full Screen Aspect Ratio Composite SVHS YPbPr RGB HDMI DVI

1080 16 : 9 No No No Yes Yes Yes

2009-Mar-20

EN 14 QCG1.0S LA5.

I_17540_007.eps

280108

18430_206_090317.eps

090317

Check SSB if

L56 1.2V correct?

No

Yes

No Power

Yes

Change

SSB

change I/O

board

No

Change

I/O-board

Separate I/O board

(connect SSB, PSU)

CN7 pin5 +5 Vs = 5 V

Correct ??

Yes

No

Check whether LED,

is on or not?

Separate SSB,

Check CN7 pin5

+5 Vs = 5 V

Change

SSB

No

Service Modes, Error Codes, and Fault Finding

5.2 Service Mode

5.2.1 Factory Mode

There are two ways to enter the factory mode:

1. On the set:

• Push the y button and turn on the AC power.

2. With the remote control:

• Turn on the set and provide a signal source on an input
(this to prevent to enter the power save mode). On the
remote control press “-”, “-”, “+”, “+”, “-”, “+”, “-”, “+”,
“SET”, “MENU”.

• Please note that this set does not respond on the
standard Philips remote controllers, but only responds
to the with the set supplied remote control.

5.3 Fault Finding

• When in the factory mode at the top right of the menu
an “F” is displayed.

• To exit the factory mode turn off the set.

Figure 5-1 Remote control.

2009-Mar-20

Figure 5-2 No power.

Service Modes, Error Codes, and Fault Finding

18430_207_090317.eps

090317

Change

power board

No

No

Yes

Check Power board CN8

Pin 11 3.3 V correct?

Change SSB

Check LCD panel

No picture

No backlight

18430_208_090317.eps

090317

No characters, missing colour

No

Check SSB CN8

Pin1 to 5, 12 V correct?

Change

SSB

Yes

Yes

Check LVDS cable

No

Change

LVDS cable

Check LCD panel

EN 15QCG1.0S LA 5.

Figure 5-3 No picture, No backlight.

Figure 5-4 No characters, missing colour.

2009-Mar-20

EN 16 QCG1.0S LA5.

18430_209_090317.eps

090317

Check input on CN6 if

pin 13 H-sync and pin 14 V-sync

are correct?

Yes

Check PC

No

Check correctness of the VGA cable

No

VGA continuosly shows no signal

Change

VGA cable

Yes

Change

SSB

18430_210_090317.eps

090317

Change

video cable

Yes

Check whether the video

cable is correct

Change I/O

board

Video-mode continuously

shows no signal

!

No

Service Modes, Error Codes, and Fault Finding

Figure 5-5 VGA continuously shows no signal.

Figure 5-6 Video-mode continuously shows no signal.

2009-Mar-20

6. Alignments

Alignments

EN 17QCG1.0S LA 6.

Index of this chapter:

6.1 General Alignment Conditions

6.2 Hardware Alignments

6.3 Software Alignments

6.4 Option Settings

6.5 Software upgrade

6.1 General Alignment Conditions

Perform all electrical adjustments under the following
conditions:

• Power supply voltage (depends on region):
– AP-NTSC: 120 V
– AP-PAL-multi: 120 - 230 V
– EU: 230 V

AC

– LATAM-NTSC: 120 - 230 V
– US: 120 V

AC

or 230 VAC / 50 Hz (± 10%).

AC

/ 50 Hz (± 10%).

AC

/ 50 Hz (± 10%).

/ 50 Hz (± 10%).

AC

/ 60 Hz (± 10%).

• Connect the set to the mains via an isolation transformer
with low internal resistance.

• Allow the set to warm up for approximately 25 minutes.

• Measure voltages and waveforms in relation to correct
ground (e.g. measure audio signals in relation to
AUDIO_GND).
Caution: It is not allowed to use heatsinks as ground.

• Test probe: R

> 10 MΩ, Ci < 20 pF.

i

• Use an isolated trimmer/screwdriver to perform
alignments.

6.2 Hardware Alignments

This chassis does not contain any hardware alignments.

6.3 Software Alignments

Refer to Figure 6-1 for details.
Put the set in the Factory mode see section Factory Mode
“F” [1] in the picture menu indicates the set is in factory mode.
Use the navigation keys to browse through the menu. Note that
even when in Factory mode, no icon for the Factory Setting
defaults is shown.

Setting Range Default value

Sharpness 0 to 100 50

Black level 0 to 100 50

Noise reduction - OFF

Tint 0 to 100 50

Color 0 to 100 50

Color temperature 9300 K

Color control Submenu -

Light sensor - OFF

Picture reset Submenu -

Color control

Setting Range Default value

User R 0 to 255 128

User G 0 to 255 128

User B 0 to 255 128

Picture reset

Setting Range Default value

Picture reset Yes/No No

6.3.2 Screen defaults

Setting Range Default value

H position 0 to 100 50

V position 0 to 100 50

Clock 0 to 100 20

Clock phase 0 to 100 0

Zoom mode Full, Real, Custom, Normal Full

Custom zoom Submenu -

Screen reset Submenu -

. The

Custom zoom

Setting Range Default value

Zoom 0-100 0

H zoom 0-100 0

V zoom 0-100 0

H position 0-100 50

1

V position 0-100 50

Figure 6-1 Factory Mode Indication

6.3.1 Picture defaults

Setting Range Default value

Brightness 0 to 100 70

Contrast 0 to 100 50

18430_201_090212.eps

090212

Screen reset

Setting Range Default value

Screen reset Yes/No No

6.3.3 Audio defaults

Setting Range Default value

Balance 0 to 100 50

Treble 0 to 100 50

Bass 0 to 100 50

Speaker Internal/External Internal

Audio reset Submenu -

Audio reset

Setting Range Default value

Audio reset Yes/No No

2009-Mar-20

EN 18 QCG1.0S LA6.

Alignments

6.3.4 PIP defaults

Setting Range Default value

PIP size Small, Middle, Large Small

PIP audio Main, Sub Main

PIP reset Submenu -

PIP reset

Setting Range Default value

PIP reset Yes/No No

6.3.5 Configuration 1 defaults

Setting Range Default value

Auto adjust Submenu -

Power save Submenu -

Language en, de, ru, cn, pl, fr, it, es, tr English

Panel saving Submenu -

Color system - N/A

Configuration reset

Factory reset Submenu -

Auto adjust

Setting Range Default value

Auto adjust - N/A

Power save

Setting Range Default value

RGB On/Off Off

Video On/Off Off

Panel saving

Setting Range Default value

Cooling fan Auto, On Auto

Brightness On/Off Off

Pixel Shift On/10-900 Off

Configuration reset

Setting Range Default value

Configuration reset Yes/No No

Factory reset

Setting Range Default value

Factory reset Yes/No No

6.3.6 Configuration 2 defaults

Setting Range Default value

OSD turn off 0 to 120 50

Information
OSD

Sleep timer 1 to 24 hrs. / Off Off

OSD H
position

OSD V
position

Flip OSD On/Off Off

Monitor information

Submenu -

1 to 10 sec / Off 10 sec

0 to 100 50

0 to 100 50

Submenu -

Monitor information

Setting Range Default value

Model name - Type number

Serial no - Serial number

Operating hours - Operating hours

SW version - Software version

6.3.7 Advanced option defaults

Setting Range Default value

Input
resolution

Black level
expansion

Gamma
selection

Scan mode - Overscan

Scan
conversion

Film mode - Auto

IR control Submenu -

Keyboard control

Tiling Submenu -

Heat status Submenu -

Date and time Submenu -

Schedule Submenu -

Monitor ID Submenu -

DDC/CI On/off On

Smart power Off/Medium/High Off

Advanced
option reset

IR control

Setting Range Default value

IR control Normal,

Keyboard control

Setting Range Default value

Keyboard control Lock/

Tiling

Setting Range Default value

H monitors 1-5 1

V monitors 1-5 1

Position 1-25 1

Frame comp. No/Yes No

Enable No/Yes No

Heat status

Setting Range Default value

Cooling fan 1 On/Off -

V monitors 1-5 -

Temperature sensor 1 - -

Temperature sensor 2 - -

Auto Auto

--

Native, 2.2, 2.4, S gamma Native

- Progressive

Submenu -

Submenu -

Normal
Primary,
Secondary,
Lock

Unlock
Unlock

2009-Mar-20

Alignments

EN 19QCG1.0S LA 6.

Date and time

Setting Range Default value

Year 2000/2099 2000

Month 01-12 01

Day 01-31 01

Hour 00-23 00

Minute 00-59 00

Daylight saving time On/off Off

Schedule

Setting Range Default value

Schedule setting by user - -

Monitor ID

Setting Range Default value

Monitor ID - 1

DDC/CI

Setting Range Default value

DDC/CI On/Off On

Smart power

Setting Range Default value

Smart power Medium/

High/Off

Advanced option reset

Setting Range Default value

Advanced option reset Yes/No No

6.3.8 Factory Setting defaults

Remark: The entry for the factory setting is not visible, but is

located below the Advanced option menu. This menu is only
available when the set is in factory mode.

Setting Range Default value

Burn in On/off (see note 1) Off

Hours running Submenu -

Factory reset Submenu -

ADC adjust Submenu -

Brightness Submenu -

Color
temperature

Input timing Submenu -

Baud rate 2400, 4800, 9600, 19200,

EDID write
protect

ISP mode On/Off Off

OSD display On/off On

Frame lock On/off On

DDR control Submenu N/A

Version Submenu -

SSC Submenu N/A

Note:

1. This function turns enables a monitor to burn in without an
input signal by showing the following burn in pattern cycle:
white, black, red, green, blue.

Submenu -

38400, 57600, 115200

On/off On

Off

9600

Hours running

Setting Resetable Default value

Resetable on Yes Monitor power on

time

Unresetable on No monitor power on

time

Factory reset

Setting Range Default value

Factory reset Yes/No No

ADC adjust

Setting Range Default value

D sub ADC adjust Submenu -

BNC ADC adjust Submenu -

YPbPr ADC adjust Submenu -

Video ADC adjust Submenu -

Dsub ADC adjust

Setting Range Default value

Auto setup - -

ADC R-gain 0-255 255

ADC G-gain 0-255 255

ADC B-gain 0-255 255

ADC R-offset 0-255 96

ADC G-offset 0-255 91

ADC B-offset 0-255 92

BNC ADC adjust

Setting Range Default value

Auto setup - -

ADC R-gain 0-255 255

ADC G-gain 0-255 255

ADC B-gain 0-255 255

ADC R-offset 0-255 96

ADC G-offset 0-255 91

ADC B-offset 0-255 92

YPbPr ADC adjust

Setting Range Default value

Auto setup - -

ADC R-gain 0-255 255

ADC G-gain 0-255 255

ADC B-gain 0-255 255

ADC R-offset 0-255 96

ADC G-offset 0-255 91

ADC B-offset 0-255 92

Video ADC adjust

Setting Range Default value

Auto setup - -

Y-gain 0-2048 1024

Y-offset 0-255 0

Color 0-2 048 1024

IRE 0-255 0

ADC alignment for ANALOG inputs

1. Enter the Factory mode as described in section Factory

Mode.

2. Enter the Factory Setting defaults.

3. Go to item “ADC ADJUST”.

4. Select proper input to adjust.

5. Select “AUTO SETUP” and press “SET”.

6. ADC is aligned.

2009-Mar-20

EN 20 QCG1.0S LA6.

Alignments

Brightness

Setting Range Default value

PC max brightness 0 to 255 255

PC min brightness 0 to 255 0

Video max brightness 0 to 255 255

Video min brightness 0 to 255 0

Color temperature

Setting Range Default value

Color temperature 5000K,

6500K,
7500K,
9300K,
10000K,
11000K

R-gain 0 to 255 128

G-gain 0 to 255 128

B-gain 0 to 255 128

R-offset 0 to 50 0

G-offset 0 to 50 0

B-offset 0 to 50 0

Input timing

Setting Range Default value

HDMI input Auto,

Video, PC

DVI-D input Auto,

Video, PC

PC-A input Auto,

Video, PC

11000K

Auto

Auto

Auto

DRAMCLK

Setting Range Default value

On/Off On/Off Off

Amplitude 0-127 0

Period 0-31 0

AUDDS1

Setting Range Default value

On/Off On/Off Off

Amplitude 0-3 0

Period 0-63 0

AUDDS2

Setting Range Default value

On/Off On/Off Off

Amplitude 0-3 0

Period 0-63 0

AUDDS3

Setting Range Default value

On/Off On/Off Off

Amplitude 0-255 0

Period 0-255 0

AUDDS4

Setting Range Default value

On/Off On/Off Off

Amplitude 0-255 0

Period 0-255 0

DDR control

Setting Range Default value

Write T0 0-255 0

Read T0 even 0-255 0

Read T0 odd 0-255 0

Write T1 0-255 0

Read T1 even 0-255 0

Read T1 odd 0-255 0

Write T2 0-255 0

Read T2 even 0-255 0

Read T2 odd 0-255 0

Write T3 0-255 0

Read T3 even 0-255 0

Read T3 odd 0-255 0

Version

Setting Range Default value

Version ID - -

SSC

Setting Range Default value

DRAMCLK Submenu -

AUDDS1 Submenu -

AUDDS2 Submenu -

AUDDS3 Submenu -

AUDDS4 Submenu -

DDDS Submenu -

VDDS1 Submenu -

VDDS2 Submenu -

DDDS

Setting Range Default value

On/Off On/Off On

Amplitude 0-255 3

Period 0-255 6

VDDS1

Setting Range Default value

On/Off On/Off Off

Amplitude 0-255 0

Period 0-255 0

VDDS2

Setting Range Default value

On/Off On/Off Off

Amplitude 0-255 0

Period 0-255 0

6.4 Option Settings

Not applicable.

2009-Mar-20

6.5 Software upgrade

18430_202_090213.eps

090213

18430_203_090213.eps

090213

18430_204_090213.eps

090213

18430_205_090213.eps

090213

6.5.1 Hardware

Connect the cable of RS232 with PC COM port by jump wire.

6.5.2 Software

1. Install the Serial upgrade program GProbe5.1.0.17.EXE on
a PC and run it.

2. Check “Options”, “Connection settings”, “Serial”, “Port” and
“Baud Rate”, see Figure 6-2

3. Make a directory called ISP on e.g. C-drive and copy the
files, see Figure 6-3

4. The latest Firmware file must be renamed into:
“fli326xxBx_rd2_32626_board_ext.hex”.

5. In the “Execute” field enter: “batch D:\ISP\
isp_spi_ext_Sequoia.txt”.

6. Put the set in the Factory mode, see section Factory Mode

7. Press UP on the remote control to enter Factory Setting
defaults and set the ISP MODE to ON.

8. Click the Execute button in the GProbe program, see

Figure 6-4

.

9. Erasing and programming will start, see Figure 6-5

10. Monitor will show a black screen. When ready (see GProbe
command window) the monitor will show picture again, see

Figure 6-5

.

.

.

Alignments

EN 21QCG1.0S LA 6.

Figure 6-3 File names

.

.

Figure 6-4 Gprobe Execute

Figure 6-5 Gprobe Erasing and programming

Figure 6-2 Gprobe connection setup

2009-Mar-20

EN 22 QCG1.0S LA7.

7. Circuit Descriptions

Circuit Descriptions

Index of this chapter:

7.1 ST FLI32626H Single-chip enhanced TV

7.2 Fairchild NC7SB3157 Low-Voltage SPDT Analog Switch

7.3 Microchip 24LC64

7.4 NXP PCA9555 16-bit I2C and SMBus I/O port with interrupt

7.5 Diodes Inc. AP1117 1A Low dropout positive regulator

7.6 NSC LM1881 Video Sync Separator

7.7 Pericom PI5V331 Video Mux/DeMux

7.8 JRC NJW1141 Audio Processor

7.9 ST TL062 Low power J-FET dual op-amp

7.10 YAMAHA YDA148 Audio Amplifier

7.11 Sipex SP3243 RS-232 transceiver

7.12 Intersil ISL29010 Light-to-Digital output sensor

7.1 ST FLI32626H Single-chip enhanced TV

The FLI32626H is an innovative System-on-Chip (SoC)
controller designed for flat panel display TVs, LCD TVs, and
other emerging digital display applications. The FLI32626H
handles video and computer graphics inputs in virtually any
format and resolution. The output port delivers unparalleled
image quality and supports display resolutions of up to 1080p.
It has a rich feature set and high level of integration. Its
sophisticated technologies for colour management, scaling,
video processing, and audio processing make the FLI32626H
the ideal solution for a high-quality, cost-effective, integrated
TV solution. The FLI32626H IC offers a high integration SoC
solution for advanced analog TV dual channel applications
(e.g. PIP) and for TV products that require superior video and
audio quality with extensive feature sets. The FLI32626H
includes a flexible analog and digital front-end with a wide
range of integrated components for different application needs
as well as state-of-the-art dual channel video processing based
on renowned Faroudja technologies. The FLI32626H is the
only device needed for a complete LCD TV solution chassis
supporting worldwide video and audio standards where
exceptional quality is required. For regional variations, only
connector and firmware changes are needed.

7.2 Fairchild NC7SB3157 Low-Voltage SPDT
Analog Switch

The NC7SB3157 / FSA3157 is a high-performance, single-pole
/ double-throw (SPDT) analog switch or 2:1 multiplexer / de­multiplexer bus switch. The device is fabricated with advanced
sub-micron CMOS technology to achieve high-speed enable
and disable times and low on resistance. The
break-before-make select circuitry prevents disruption of
signals on the B Port due to both switches temporarily being
enabled during select pin switching. The device is specified to
operate over the 1.65 to 5.5V VCC operating range. The
control input tolerates voltages up to 5.5V, independent of the
V

operating range.

CC

7.3 Microchip 24LC64

The Microchip Technology Inc. 24AA64/24LC64 (24XX64*) is
a 64 Kbit Electrically Erasable PROM. The device is organized
as eight blocks of 1K x 8-bit memory with a 2-wire serial
interface. Low voltage design permits operation down to 1.8V
with standby and active currents of only 1 μA and 1 mA
respectively. It has been developed for advanced, low power
applications such as personal communications or data
acquisition. The 24XX64 also has a page-write capability for up
to 32 bytes of data. Functional address lines allow up to eight
devices on the same bus, for up to 512 Kbits address space.

7.4 NXP PCA9555 16-bit I2C and SMBus I/O port
with interrupt

The PCA9555 consist of two 8-bit Configuration (Input or
Output selection); Input, Output and Polarity inversion (Active
high or Active low operation) registers. The system master can
enable the I/Os as either inputs or outputs by writing to the I/O
configuration bits. The data for each Input or Output is kept in
the corresponding Input or Output register. The polarity of the
read register can be inverted with the Polarity Inversion
Register. All registers can be read by the system master. The
PCA9555 open-drain interrupt output is activated when any
input state differs from its corresponding input port register
state and is used to indicate to the system master that an input
state has changed. The power-on reset sets the registers to
their default values and initializes the device state machine.
Three hardware pins (A0, A1, A2) vary the fixed I
and allow up to eight devices to share the same I
The fixed I
PCA9554 allowing up to eight of these devices in any
combination to share the same I

2

C address of the PCA9555 is the same as the

2

C/SMBus.

2

C address

2

C/SMBus.

7.5 Diodes Inc. AP1117 1A Low dropout positive
regulator

AP1117 is a low dropout positive adjustable or fixed-mode
regulator with 1A output current capability. The product is
voltage specifically designed to provide well-regulated supply
for low IC applications such as high-speed bus termination and
low current 3.3 V logic supply. AP1117 is also well suited for
other applications such as VGA cards. AP1117 is guaranteed
to have lower than 1.4V dropout at full load current making it
ideal to provide well-regulated outputs of 1.25 to 5.0 V with

6.4 to 18 V input supply.

7.6 NSC LM1881 Video Sync Separator

The LM1881 Video sync separator extracts timing information
including composite and vertical sync, burst/back porch timing,
and odd/even field information from standard negative going
sync NTSC, PAL* and SECAM video signals with amplitude
from 0.5to2V
providing sync separation for non-standard, faster horizontal
rate video signals. The vertical output is produced on the rising
edge of the first serration in the vertical sync period. A default
vertical output is produced after a time delay if the rising edge
mentioned above does not occur within the externally set delay
period, such as might be the case for a non-standard video
signal.

. The integrated circuit is also capable of

p-p

7.7 Pericom PI5V331 Video Mux/DeMux

Pericom Semiconductor’s PI5V331 is a true bidirectional Dual
4-channel multiplexer/demultiplexer that is recommended for
both S-Video or composite video switching applications. The
switch can be driven from a current output RAMDAC or voltage
output composite video source. Low On-resistance and wide
bandwidth make it ideal for video and other applications. Also
this device has exceptionally high current capability which is far
greater than most analog switches offered today. A single 5 V
supply is all that is required for operation. The PI5V331 offers
a high-performance, low-cost solution to switch between video
sources.

2009-Mar-20

7.8 JRC NJW1141 Audio Processor

The NJW1141 is a sound processor includes all of the
functions required to process the audio signal for TV, such as
tone control, balance, volume, mute, and AGC functions. All of
the internal status and variables are controlled by I
interface.

2

C bus

7.9 ST TL062 Low power J-FET dual op-amp

The TL062is an high speed J-FET input dual operational
amplifier. This J-FET input operational amplifiers incorporates
well matched, high voltage J-FET and bipolar transistors in a
monolithic integrated circuit. The device features high slew
rates, low input bias and offset currents, and a low offset
voltage temperature coefficient.

7.10 YAMAHA YDA148 Audio Amplifier

YDA148 (D-510) is a high-efficiency digital audio power
amplifier IC with the maximum output of 2 × 15 W. The
YDA148 has a “Pure pulse direct speaker drive circuit” that
directly drives speakers while reducing distortion of pulse
output signal and reducing noise on the signal, which realizes
the highest standard low distortion rate characteristics and low
noise characteristics among digital amplifier ICs in the same
class. In addition, supporting filterless design allows circuit
design with fewer external parts to be realized depending on
use conditions. The YDA148 features a power limit function, a
non-clip function, and DRC (dynamic range control) function
that were developed by Yamaha original digital amplifier
technology. The YDA148 has overcurrent protection for
speaker output terminals, high temperature protection, and low
supply voltage malfunction prevention.

Circuit Descriptions

EN 23QCG1.0S LA 7.

7.11 Sipex SP3243 RS-232 transceiver

The SP3243 transceivers meet the EIA/TIA-232 and ITU-T
V.28/V.24 communication protocols. Generates 5.5V RS-232
voltage levels from a single +3.0V to +5.5V power supply and
operates at a data rate of 120 kbps fully loaded. The SP3243
devices feature AUTO ON-LINE® circuitry automatically wakes
up from a 1 μA shutdown. It occurs after a RS-232 cable being
disconnected. Under this condition, the internal charge pump
and the drivers will be shut down. Otherwise, the system
automatically comes on-line.

7.12 Intersil ISL29010 Light-to-Digital output sensor

The ISL29010 is an integrated light sensor with I2C interface. It
has an internal signed15-bit integrating type ADC designed
based on the charge-balancing conversion technique. This
ADC is capable of rejecting 50 Hz and 60 Hz flicker caused by
artificial light sources. The lux range select feature allows the
user to program the lux range for optimised counts/lux. In
normal operation, power consumption is typically 250 μA.
Furthermore, a power-down mode can be controlled by
software via the I
less than 1 μA. Designed to operate on supplies from 2.5 V to

3.3 V, the ISL29010 is specified for operation over the −40°C to
+85°C ambient temperature range.

2

C interface, reducing power consumption to

2009-Mar-20

EN 24 QCG1.0S LA8.

External Memory 32-bit DDR2/DDR1

HDMI1/DVI

HDMI2/DVI

Sharpening

Filters

ACM 3D

and ACC II

24/30­bit TTL
Output

Dual
10-bit
Channel
LVDS

-

4 Channels

Output

Formatter

LVDS Tx

OSD

Controller

VBI Data

Proc.

Cross

Point

Switch

Embedded

Microprocessor

IR I/F

LBW ADC

3 x 3

Matrix

General

Purpose

Input/

Output

SPI Interface

Enhancer

3x3

Matrix

Picture

Blend

CLUTs

OSD

Blend

Memory

Controller

10-bit
Triple

ADC

DCDi Format

Conversion for

PIP

10-bit
Triple

ADC

CVBS

YC

YPbPr

RGB

RGB FB

3D

Video

Decoder

HDMI 1.3/

DVI

Digital

Input

..

.
.

19 Reconfigurable Inputs

M
U
X

M
U
X

I2S

SPDIF

..

Audio

MUX

Audio

DSP

Audio

DACs

Audio

out 1 .. 5

I2S,

DSD,

SPDIF Tx

I2S, DSD,
SPDIF out

ADC

Inputs,

I2S/

SPDIF

Rx

Audio L/R 1 .. 5,

1 x I2S,

1 x 12S/SPDIF

.
.

GPIO

Up to 30 bits TTL

Block Diagram

18430_302_090204.eps

090204

8. IC Data Sheets

IC Data Sheets

Index of this chapter:

8.1 Diagram Main Board: HDMI In Sequoia, FLI32626H (IC
UD8)

8.2 Diagram Main Board: ISP, NC7SB3157 (IC U18)

8.3 Diagram Main Board: OCM Peripherals, 24LC64 (IC U25)

8.4 Diagram Main Board: OCM Peripherals, PCA9555 (IC U29)

8.5 Diagram Main Board: Power System, AP1117ELA (IC U46)

8.6 Diagram Extension Board: Video input, MM1671 (IC U1)

8.7 Diagram Extension Board: Video input, LM1881 (IC U2)

8.8 Diagram Extension Board: Video input, PI5V331 (IC U3)

8.9 Diagram Extension Board: Audio input, NJW1141M (IC
U24)

8.10 Diagram Extension Board: Audio input, TL062 (IC U25)

8.11 Diagram Extension Board: Audio amplifier, YDA148 (IC
U27)

8.12 Diagram Extension Board: RS232, SP3243 (IC U29)

8.13 Diagram IR LED board, ISL29010 (IC U1)

8.1 Diagram Main Board: HDMI In Sequoia, FLI32626H (IC UD8)

This section shows the internal block diagrams and pin
configurations of ICs that are drawn as “black boxes” in the
electrical diagrams (with the exception of “memory” and “logic”
ICs).

2009-Mar-20

Figure 8-1 Internal block diagram

8.2 Diagram Main Board: ISP, NC7SB3157 (IC U18)

Block Diagram

Pin Configuration

18430_306_090204.eps

090204

B

1

B

0

GND

S

V

CC

A

1

2

3 4

6

5

S

V

CC

A

B

1

GND

B

0

Input (S) Function

Logic Level Low B0 Connected to A

Logic Level High B

1

Connected to A

Pin Descriptions

Pin Names Description

A, B0, B

1

Data Ports

S Control Input

IC Data Sheets

EN 25QCG1.0S LA 8.

Figure 8-2 Internal block diagram and pin configuration

2009-Mar-20

EN 26 QCG1.0S LA8.

8.3 Diagram Main Board: OCM Peripherals, 24LC64 (IC U25)

IC Data Sheets

Block Diagram

A0 A1 WPA2

I/O

CONTROL

LOGIC

I/O

SDA

V

VSS

SCL

CC

MEMORY

CONTROL

Pin Configuration

LOGIC

XDEC

HV GENERATOR

EEPROM

ARRAY

PAGE LATCHES

YDEC

SENSE AMP

R/W CONTROL

A0

A1

A2

Vss

Figure 8-3 Internal block diagram and pin configuration

1

2

3

4

24XX64

8

7

6

5

Vcc

WP

SCL

SDA

18430_300_090204.eps

090204

2009-Mar-20

IC Data Sheets

8.4 Diagram Main Board: OCM Peripherals, PCA9555 (IC U29)

Block Diagram

A0

A1

A2

2

I

C/SMBUS

CONTROL

SCL

SDA

V

DD

V

SS

INPUT

FILTER

POWER-ON

RESET

8-BIT

WRITE pulse

READ pulse

8-BIT

WRITE pulse

READ pulse

INPUT/

OUTPUT

PORTS

INPUT/

OUTPUT

PORTS

LP FILTER

EN 27QCG1.0S LA 8.

I/O1.0

I/O1.1

I/O1.2

I/O1.3

I/O1.4

I/O1.5

I/O1.6

I/O1.7

I/O0.0

I/O0.1

I/O0.2

I/O0.3

I/O0.4

I/O0.5

I/O0.6

I/O0.7

V

INT

INT

Pin Configuration

INT

A1

A2

I/O0.0

I/O0.1

I/O0.2

I/O0.3

I/O0.4

I/O0.5

I/O0.6

I/O0.7

SS

NOTE: ALL I/Os ARE SET TO INPUTS AT RESET

1

2

3

4

5

6

PCA9555

7

8

9

10

11

24

23

22

21

20

19

18

17

16

15

14

12 13

V

DD

SDA

SCL

A0

I/O1.7

I/O1.6

I/O1.5

I/O1.4

I/O1.3

I/O1.2

I/O1.1

I/O1.0V

18430_308_090205.eps

090205

Figure 8-4 Internal block diagram and pin configuration

2009-Mar-20

EN 28 QCG1.0S LA8.

Block Diagram

Pin Configuration

18430_301_090204.eps

090204

NAME I/O PIN # FUNCTION

Adj (GND) I 1

A resistor divider from this pin to the V

out

pin and ground sets the output voltage

(Ground only for Fixed-Mode).

V

out

O 2

The output of the regulator. A minimum of 10uF capacitor (0.15? ? ESR ? 20? )

must be connected from this pin to ground to insure stability.

V

in

I 3

The input pin of regulator. Typically a large storage capacitor (0.15? ? ESR ? 20? )

is connected from this pin to ground to insure that the input voltage does not sag
below the minimum dropout voltage during the load transient response. This pin

must always be 1.3V higher than V

out

in order for the device to regulate properly.

3

Thermal

Shutdown

1

2

V

out

Adj

1.25V

+

+

CURRENT

LIMIT

V

in

-

+

+

1

GND

(FIXED)

-

IC Data Sheets

8.5 Diagram Main Board: Power System, AP1117ELA (IC U46)

Figure 8-5 Internal block diagram and pin configuration

2009-Mar-20

IC Data Sheets

8.6 Diagram Extension Board: Video input, MM1671 (IC U1)

Block Diagram

CC

V

6

1

*

IN

PS

4

1

LPF

6.75MHz

GND

2

*

5

75Ω
Driver

EN 29QCG1.0S LA 8.

OUT

2

3

SAG

MM1671

MM1672

MM1673

MM1674

MM1675

MM1676

MM1677

Pin Configuration

6

1 3

(TOP VIEW)

45

2

**

bias clamp 6dB (

1 PS

2 OUT
3SAG
4IN
5GND
5V

CC

2) 9dB(*2) 12dB (*2) 16.5dB (*2)

*

reifilpma ni-tliuB 2pmalC tupnI 1

18430_305_090204 .eps

090204

Figure 8-6 Internal block diagram and pin configuration

2009-Mar-20

EN 30 QCG1.0S LA8.

Block Diagram

Pin Configuration

18430_304_090204.eps

090204

IC Data Sheets

8.7 Diagram Extension Board: Video input, LM1881 (IC U2)

Figure 8-7 Internal block diagram and pin configuration

2009-Mar-20

IC Data Sheets

Block Diagram

Pin Configuration

18430_310_090205.eps

090205

DECODER

EN

A

EN

B

IN

1

IN

0

S

4

B

S3B

S

2

B

D

A

S

1

B

S

4

A

S

3

A

S

2

A

S

1

A

D

B

Pin Description

Pin Name Description

S1A, S2A, S3A, S4A

S

1B, S2

B , S3B, S4B

Analog Video I/O (Usually Inputs)

S

0

, S

1

Select Input

EN

A

, EN

B

Enable

D

A

, DB Analog Video I/O (Usually Outputs)

GND Ground

V

CC

Power

8.8 Diagram Extension Board: Video input, PI5V331 (IC U3)

EN 31QCG1.0S LA 8.

EN

IN

4

S

3

S

2

S

1

S

D

GND

A

1

1

2

A

3

A

4

A

5

A

6

A

7

8

V

CC

16

EN

B

15

IN0

14

S4B

13

3

S

B

12

2

S

B

11

1

S

B

10

D

B

9

Figure 8-8 Internal block diagram and pin configuration

2009-Mar-20

EN 32 QCG1.0S LA8.

Block Diagram

Pin Configuration

18430_307_090204.eps

090204

Bia s

AGC

CVA
CVB
CTH
CTL

GND

Vcc

Vref

TONE

-Ha

TONE

-Hb

TONE

-La

TONE

-Lb

OUTb

SDA

SCL

SEL

SEL TONE VOL2

AGC

TONE VOL2

VOL1

VOL1

IN1a
IN2a

IN3a
IN4a

IN1b
IN2b

IN3b
IN4b

-2dB

-2dB

+4.5dB+4.5dB

MONa

MONb

OUTa

I2CBUS

11 CVB DAC Output for Bch Volume & Balance

12 CVA DAC Output for Ach Volume & Balance

lanimreT ylppuS rewoP +V61

17 Vref Reference Voltage

18 CTL Pop Noise reduction for Bass Control

19 CTH Pop Noise reduction for Treble Control

retliF CGA CGA02

tuptuO hcB bTUO12

)Bd5.4+( tuptuO ENIL hcB

bENIL22

retliF ssaB hcB bL-ENOT32

retliF elberT hcB bH-ENOT42

tcennoC oN CN52

Bch Monitor OutputMONb62

Bch Input4IN4b72

b3NI82Bch Input3

b2NI92Bch Input2

b1N

I03 Bch Input1

noitcnuF lobmyS .oN

1tupnI hcA a1NI 1

2 IN2a Ach Input2

3 IN3aAch Input3

4 IN4a Ach Input4

tuptuO rotinoM hcA aNOM 5

tcennoC oN CN 6

retliF elberT hcA aH-ENOT 7

retl

iF ssaB hcA aL-ENOT 8

)Bd5.4+( tuptuO ENIL hcA aENIL 9

tuptuO hcA aTUO 01

13 SDA SDA Data Input (I

2

)SUB C

14 SCL SCL Clock Input (I

2

)SUB C

lanimreT DNG DNG 51

16

30

29

28

27

26

25

24

23

22

21

18

19

20

17

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

IN1a

IN2a

IN3a

IN4a

IN1b

IN2b

IN3b

IN4b

MONa

MONb

TONE -Ha TONE-Hb

TONE -La

LINEa

TONE-Lb

LINEb

OUTa OUTb

CVb

CTH

CTL

SDA

SCL

GND

Vref

V+

AGC

CVa

NC

NC

16

IC Data Sheets

8.9 Diagram Extension Board: Audio input, NJW1141M (IC U24)

2009-Mar-20

Figure 8-9 Internal block diagram and pin configuration

8.10 Diagram Extension Board: Audio input, TL062 (IC U25)

Block Diagram

Pin Configuration

18430_312_090205.eps

090205

IC Data Sheets

EN 33QCG1.0S LA 8.

Figure 8-10 Internal block diagram and pin configuration

2009-Mar-20

EN 34 QCG1.0S LA8.

IC Data Sheets

8.11 Diagram Extension Board: Audio amplifier, YDA148 (IC U27)

Block Diagram

Pin Configuration

Figure 8-11 Internal block diagram and pin configuration

< 32-pin QFN Top View >

18430_313_090205.eps

090205

2009-Mar-20

8.12 Diagram Extension Board: RS232, SP3243 (IC U29)

Block Diagram

Pin Configuration

18430_311_090205.eps

090205

R4IN

1

2

3

4

25

26

27

28

5

6

7

24

23

22

SHUTDOWN

C2-

V-

R

1

IN

R

2

IN

R

3

IN

ONLINE

C2+

C1-

GND

V

CC

V+

STAT US

T

1

IN

8

9

10

11

18

19

20

21

12

13

14

17

16

15

R

5

OUT

T

1

OUT

T

2

OUT

T

3

OUT

T

3

IN

T

2

IN

R

4

OUT

R

5

IN

R

3

OUT

R

2

OUT

R

1

OUT

R

2

OUT

SP3243

C1+

SP3243

28

24

2

1

27

3

26

5KΩ

5KΩ

5KΩ

5KΩ

5KΩ

GND

C1+

C1-

C2+

C2-

V+

V-

V

CC

14

13

12

20

19

18

17

16

15

0.1

μ

F

0.1

μ

F

0.1

μ

F

+

C2

C5

C1

+

+

C3

C4

+

+

0.1

μ

F

0.1

μ

F

9

10

11

4

5

6

7

8

RS-232
OUTPUTS

RS-232
INPUTS

TTL/CMOS

INPUTS

TTL/CMOS

OUTPUTS

To μP Supervisor

Circuit

23

22

21

VCC

V

CC

25

T1IN

R

1

OUT

R1IN

T

2

OUT

R2OUT

T2IN

T

3

IN

T

3

OUT

T

1

OUT

R

2

IN

R

3

IN

R

4

IN

R

5

IN

R

2

OUT

R

3

OUT

R

4

OUT

R

5

OUT

ONLINE

SHUTDOWN

STATU S

IC Data Sheets

EN 35QCG1.0S LA 8.

Figure 8-12 Internal block diagram and pin configuration

2009-Mar-20

EN 36 QCG1.0S LA8.

Block Diagram

Pin Configuration

18430_303_090204.eps

090204

VDD

REXT GND

SDA

SCL

COMMAND

REGISTER

INTEGRATING

ADC

DATA

REGISTER

I2C

PHOTODIODE

LIGHT

3 2

5

6

1

FOSC

IREF

COUNTER

2

16

GAIN/RANGE

EXT

SHDN

INT TIME

4

A0

TIMING

PROCESS

ARRAY

DATA

MODE

(6 LD ODFN)

TOP VIEW

1

2

3

6

5

4

VDD

GND

REXT

SDA

SCL

A

0

IC Data Sheets

8.13 Diagram IR LED board, ISL29010 (IC U1)

Figure 8-13 Internal block diagram and pin configuration

2009-Mar-20

9. Block Diagrams, Test Point Overview

CN8

1. GND

2. GND

3. GND

4. +12V

5. +12V

6. +12V

7. GND

8. GND

9. GND

10. VBr1

11. BL_ON

12. VLAMP

LCD DISPLAY

LVD S INPUT

(1080p)

51P

CN5

12. BL_ON

11. VBr_1

10. GND

9. GND

8. GND

7. GND

6. GND

5. +24V

4. +24V

3. +24V

2. +24V

1. +24V

CN4

12. BL_ON

11. VBr_1

10. GND

9. GND

8. GND

7. GND

6. GND

5. +24V

4. +24V

3. +24V

2. +24V

1. +24V

CN6

1. +24V

2. +24V

3. +24V

4. +24V

5. +24V

6. GND

7. GND

8. GND

9. GND

10. GND

11. VBr1

12. BL_ON

13. GND

14.VLAMP

CN3

1. +24V

2. +24V

3. +24V

4. +24V

5. +24V

6. GND

7. GND

8. GND

9. GND

10. GND

11. VBr1

12. BL_ON

13. GND

14.VLAMP

CN1

1. L

2. N

CN7

3P

CN8

3P

CN9

4P

CN6

4P

CN9

10P

CN10

10P12

J7

14P

CN19

10P12

CN8

40P

CN17

30P

CN4

30P

CN9

12P

CN9

10P

CN10

12P

CN9

10P12

CN10

2P

CN10

2P

CN13

5P

CN14

8P

CN1

8P

CN8

5P

IR LED PANEL

KEYBOARD

MAIN SUPPLY

INVERTER INVERTER

WIRING DIAGRAM 52"

CN7

1. PWR_ON

2. ACD

3. GND

4. GND

5. +5VS

6. +5VS

7. +5V_SW

8. +5V_SW

9. +5V_SW

10. +5V_SW

11. +5V_SW

12. +5V_SW

13. GND

14. GND

INLET

EXTENTION BOARD

MAIN BOARD

FAN

TEMP
SENSOR

TEMP
SENSOR

RIGHT SPEAKER LEFT SPEAKER

18430_400_090122.eps

220109

FAN

F1 T8.0A

Wiring Diagram 52"

Block Diagrams, Test Point Overview

EN 37QCG1.0S LA 9.

2009-Mar-20

Circuit Diagrams and PWB Layouts

A

y,

10. Circuit Diagrams and PWB Layouts

Main Board: HDMI Input

5

+5V_HDMI_CONA

1

R5
0R/6/NC

3

D

21

SHELL2

23

SHELL4

HP DET

DDC DATA

DDC CLK

CE Remote

CK Shield

D0 Shield

HDMI1

D1 Shield

C

22
20

CN1
HDMI_con

SHELL3
SHELL1

D2 Shield

D1
BAT54C

2

+5V_HDMI_CONA

19
18

+5V

17

GND

16
15
14

NC

13
12

CK-

11
10

CK+

9

D0-

8
7

D0+

6

D1-

5
4

D1+

3

D2-

2
1

D2+

+5VS

DDCA_VCC

R6
0R/6

HA_CON_HOTPLUG

R11 1K/6

HA_CON_SDA
HA_CON_SCL

HA_CON_CEC
HA_CON_RXC-

HA_CON_RXC+
HA_CON_RX0-

HA_CON_RX0+
HA_CON_RX1-

HA_CON_RX1+
HA_CON_RX2-

HA_CON_RX2+

EN 38QCG1.0S LA 10.

4 3 2

+5V_HDMI_CONA

Q1

3

2N7002

1

R2

10K/6/NC

R8
0R/6

2

R13

1K/6

HA_DDC_SDA

HA_DDC_SCL

AHPD

R7

HDMI_HP_A FAST_HP_A

C2

0.1uF/6

HA_CON_SDA

HA_CON_SCL

24.9K/6

R12

42.2K/6

DDCA_VCC

R688
10K/6

D2 UDZ5V6B/NC

2 1

R689
10K/6

R20 0R/6/NC

R21 0R/6/NC

R3 0R/6

R15 NC

DDCA_VCC

R18 10K/6/NC

R22 0R/6/NC

U1

24LC02B

1

A0

2

A1

3

A2

4

VSS

U2

24LC02B/NC

1

A0

2

A1

3

A2
VSS4SDA

Q3

DTC144E/NC

DDCA_VCC

8

VCC

7

WP

6

SCL

5

SDA

C1

0.1uF/6

DDCA_VCC

8

VCC

7

WP

6

SCL

5

C3

0.1uF/6

3 2

1

R1 100R/6
R4 100R/6

DDCA_WP

R14 0R/6/NC
R16 0R/6/NC

HA_DDC_SCL

HA_DDC_SDA

R9 0R/6

R17 10K/6

32

1

Q2

DTC144E

1

MSTR0_SCL 17
MSTR0_SDA 17

R10 0R/6

DDCA_VCC

DDC_WP 3,7,17

APCCE_SW 17

B

HA_CON_CEC

HA_CON_HOTPLUG

A

C4

0.1uF/6

HA_CON_RX2+

HA_CON_RX2­HA_CON_RX1+

HA_CON_RX1­HA_CON_RX0+

HA_CON_RX0­HA_CON_RXC+

HA_CON_RXC-

R28 0R/6/NC

HA_CON_SCL
HA_CON_SDA

R30 0R/6/NC

HA_CON_CEC

CONNECTOR IC

38

NC

37

ESD_BYP

36

GND

35

1TMDS_D2+

34

1TMDS_GND

33

1TMDS_D2-

32

1TMDS_D1+

31

TMDS_GND

30

1TMDS_D1-

29

1TMDS_D0+

28

TMDS_GND

27

1TMDS_D0-

26

1TMDS_CK+

25

TMDS_GND

24

1TMDS_CK-

23

1CE_REMOTE_OUT

22

1DDC_CLK_OUT

21

1DDC_DAT_OUT

20

+5VS

R339 8.2K/6/NC

R19 0R/6/NC

R344

10K/6/NC

1HOTPLUG_DET_OUT

D35 BAT17

D36

HOTPLUG_DET_IN

IP4776CZ38

BAT17

5V_SUPPLY
LV_SUPPLY

GND

TMDS_D2+

TMDS_GND

TMDS_D2-

TMDS_D1+

TMDS_GND

TMDS_D1-

TMDS_D0+

TMDS_GND

TMDS_D0-

TMDS_CK+

TMDS_GND

TMDS_CK-

CE_REMOTE_IN

DDC_CLK_IN
DDC_DAT_IN

U3

+3.3V_SMCU

R338

27K/6

+5V_HDMI_CONA

DDCA_VCC

1

R23 0R/6

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19

HA_CEC

HA_CON_RX2+

HA_CON_RX2­HA_CON_RX1+

HA_CON_RX1­HA_CON_RX0+

HA_CON_RX0­HA_CON_RXC+

HA_CON_RXC-

R29 0R/6/NC

R31 0R/6/NC

HA_CEC 15

L1

121A40/8/NC

121A40/8

HA_CEC
HA_DDC_SCL
HA_DDC_SDA
AHPD

L2

R25 10K/6

R24 47K/6/NC

R26 10K/6

R27 47K/6/NC

+5VS

+3.3V_SMCU

FAST_HP_A

HDMI_HP_A

HA_CON_RX2+
HA_CON_RX2-

HA_CON_RX1+
HA_CON_RX1-

HA_CON_RX0+
HA_CON_RX0-

HA_CON_RXC+
HA_CON_RXC-

+5VS 3,7,15,17,18,19,20,21,22

+3.3V_SMCU 17,18,20,21,22

PROJECT NAME:

WLZR-A1

Title

HDMI1 Input

ezi

S

A4

coD

WLZSA1 ST FLI32626

January 08, 2009

FAST_HP_A 17

HDMI_HP_A 17

HA_CON_RX2+ 4
HA_CON_RX2- 4

HA_CON_RX1+ 4
HA_CON_RX1- 4

HA_CON_RX0+ 4
HA_CON_RX0- 4

HA_CON_RXC+ 4
HA_CON_RXC- 4

RrebmuN tnemu

ve

D2A

222Thursda

teehS:etaD

of

18430_500_090202.eps

090202

2009-Mar-20

Main Board: DVI Input

A

y,

5

+5VS

D

C

2

DVI_DDC5V

CN2

RED

GRN

GND

VSYNC

SYNC GND

DDC SCL

DDC SDA

HPD

1/3shield
2/4shield
0/5shield
clk shield

DAT0+

DAT0-

DAT1+

DAT1-

DAT2+

DAT2-

DAT3+

DAT3-

DAT4+

DAT4-

DAT5+

DAT5-

252526

JACK DVI

BLU

Hs

+5V

clk+

clk-

26

DVI_5V

D3BAT54C

1

3

C1
C2
C3
C4
C5

8
15
6
7
14
16

11
3
19
22

18
17
10
9
2
1
13
12
5
4
21
20
23
24

Circuit Diagrams and PWB Layouts

D7

D12

EZJZ0V800AA/NC

DVI_DDC_SCL
DVI_DDC_SDA

Q5
MMBT3904

31

2 1

R712

D13

EZJZ0V800AA/NC

D14

EZJZ0V800AA/NC

2

EZJZ0V800AA/NC

DVI_5V

R44

R47 1K/6
R49 0R/6

UDZ5V6B/NC

D10

EZJZ0V800AA/NC

0R/6

D11

EN 39QCG1.0S LA 10.

4 3 2

R34 0R/6

L6

1k/6/NC

D15

C9 47pF/6/NC

0R/6

1

D8

R48

UDZ5V6B/NC

DVI_RX0P
DVI_RX0N
DVI_RX1P
DVI_RX1N
DVI_RX2P
DVI_RX2N
DVI_RXCP
DVI_RXCN

D16

EZJZ0V800AA/NC

D17

EZJZ0V800AA/NC

R45

0R/6/NC

2

R52 10R/6
R53 10R/6
R54 10R/6
R55 10R/6
R56 10R/6
R58 10R/6
R59 10R/6
R60 10R/6

EZJZ0V800AA/NC

0R/6

C10 47pF/6/NC

1

D9
UDZ5V6B/NC

R51 4.7K/6

HB_DDC_SCL

HB_DDC_SDA

L7
0R/6

DVI_DETECT

2

HDMI_HP_B

HB_CON_RX0+
HB_CON_RX0­HB_CON_RX1+
HB_CON_RX1­HB_CON_RX2+
HB_CON_RX2­HB_CON_RXC+
HB_CON_RXC-

HB_DDC_SCL 4
HB_DDC_SDA 4

DVI_DETECT 17

HDMI_HP_B 17

HB_CON_RX0+ 4
HB_CON_RX0- 4
HB_CON_RX1+ 4
HB_CON_RX1- 4
HB_CON_RX2+ 4
HB_CON_RX2- 4
HB_CON_RXC+ 4
HB_CON_RXC- 4

R46 NC

DVI_DDC5V

U4

24LC02B

1

A0

2

A1

3

A2

4

VSS

U5

24LC02B/NC

1

A0

2

A1

3

A2

4

VSS

R50 10K/6/NC

3

R57 0R/6/NC

DVI_DDC_SDA

DVI_DDC_SCL

R61 10K/6

R62 10K/6

DVI_DDC5V

8

VCC

7

WP

6

SCL

5

SDA

C5

0.1uF/6

DVI_DDC5V

8

VCC

7

WP

6

SCL

5

SDA

C11

0.1uF/6/NC

Q6

DTC144E/NC

1

DVI_DDC5V

R32

100R/6
100R/6

R33

DVI_EDID_WP

R42 0R/6/NC
R43 0R/6/NC

DTC144E

2

1

HB_DDC_SCL

HB_DDC_SDA

DVI_DDC5V

R41
10K/6

Q4

32

1

DDC_WP 2,7,17

BPCCE_SW 17

B

+5VS

DVI_5V

+5VS 2,7,15,17,18,19,20,21,22

DVI_5V

PROJECT NAME:

A

WLZR-A1

Title

DVI Input

veRrebmuN tnemucoDeziS

A4

D

WLZSA1 ST FLI32626

January 08, 2009

tee

hS:eta

of

322Thursda

18430_501_090202.eps

D2A

090202

2009-Mar-20

Circuit Diagrams and PWB Layouts

A

y,

Main Board: HDMI In Sequoia

5

EN 40QCG1.0S LA 10.

4 3 2

1

HA_CON_RX2+2
HA_CON_RX2-2

HA_CON_RX1+2

D

HA_CON_RX1-2

HA_CON_RX0+2
HA_CON_RX0-2

HA_CON_RXC+2
HA_CON_RXC-2

HB_CON_RX2+3
HB_CON_RX2-3

3

HB_CON_RX1+
HB_CON_RX1-3

HB_CON_RX0+3
HB_CON_RX0-3

HB_CON_RXC+3
HB_CON_RXC-3

HA_CON_RXC+

HA_CON_RXC-

HB_CON_RX2+

HB_CON_RX2-

HB_CON_RX1+

HB_CON_RX1-

HB_CON_RX0+

HB_CON_RX0-

HB_CON_RXC+

HB_CON_RXC-

HA_CON_RX2+

HA_CON_RX2-

HA_CON_RX1+

HA_CON_RX1-

HA_CON_RX0+

HA_CON_RX0-

C

HB_DDC_SCL

3
3

HB_DDC_SDA

+3.3V_HDMI

HB_DDC_SCL
HB_DDC_SDA

R69

249R/6

D6

E7

E6

HDMI_SCL

B

C1

HDMI_VSS

C3

HDMI_VSS

C5

HDMI_VSS

C7

HDMI_VSS

D4

HDMI_VSS

D5

HDMI_VSS

U8D
FLI32626H

HDMI_REXT

HDMI_SDA

SEQUOIA HDMI
Input Port

A4

B4

HMDI_BRXCP

HDMI_BRXCN

A3

B3

HDMI_BRX0P

HDMI_BRX0N

A2

B2

HDMI_BRX1P

HDMI_BRX1N

A1

B1

HDMI_BRX2P

HDMI_BRX2N

A8

B8

HDMI_ARXCP

HDMI_ARXCN

A7

B7

HDMI_ARX0P

HDMI_ARX0N

HDMI_VDD_33
HDMI_VDD_33
HDMI_VDD_33
HDMI_VDD_33

HDMI_VDD_12

A6

B6

HDMI_ARX1P

HDMI_ARX1N

A5

B5

HDMI_ARX2P

HDMI_ARX2N

C2
C4
C6
D7

E5

0.1uF/6

C22

+

C18

1nF/6

12

C19

1nF/6

C23

22uF/6.3V

C20

0.1uF/6

+1.2V_HDMI

C21

0.1uF/6

12

+

22uF/6.3V

C17

+3.3V_HDMI

+1.2V_HDMI
+3.3V_HDMI

+1.2V_HDMI 19
+3.3V_HDMI 19

PROJECT NAME:

A

WLZR-A1

Title

HDMI_IN_ SEQUOIA

A4

D

eziS

mu

N tnemuco

WLZSA1 ST FLI32626

422Thursda

January 08, 2009

teehS:etaD

of

18430_502_090202.eps

v

eRreb

D2A

090202

2009-Mar-20

Circuit Diagrams and PWB Layouts

A

y,

Main Board: Display Port Input

5

EN 41QCG1.0S LA 10.

4 3 2

1

+1.2V_DPRX

CM1213-04MR/NC

D

C

22

B

CN3
TKE-850-301-011-01/NC

23

24

D3-

1

GND

2

D3+

3

D2-

4

GND

5

D2+

6

D1-

7

GND

8

D1+

9

D0-

10

GND

11

D0+

12

GND

13

GND

14

AX+

15

GND

16

AX-

17

HPD

18

RTN

19

PWR

20

21

DCC0904N017/NC

D3N

D3P
D2N

D2P
D1N

D1P
D0N

D0P

DAP

DAN
HPD

R77

0R/6/NC

TP1

L13

4

1

L14

4

1

L15

4

1
4

1

L16
DCC0904N017/NC

R71

0R/6/NC

+5V_CON_DPRX

3

2
3

DCC0904N017/NC

2

DCC0904N017/NC

3

2
3

2

R72

47K/6/NC

R70
22R/6/NC

+3.3V_I/O

D20

Vcc
Line1
NC
Line3
NC Line4

+1.2V_DPRX

Vcc
Line1
NC
Line3 NC
NC Line4

D21

CM1213-04MR/NC

DP_HP

R73

100K/6/NC

R74

100K/6/NC

C24

0.22uF/6/NC

NC

Line2

NC

GND

C29 0.22uF/6/NC

NC

Line2

GND

DAP

DAN

R75

100K/6/NC

DP_HP 17

DP Source Monitor

RN1 10R/4P2R/NC

2
1

RN2 10R/4P2R/NC

2 3
1

RN3 10R/4P2R/NC

2 3
1

RN4 10R/4P2R/NC

2
1

R78
10K/6/NC

3
4

4

4

3
4

+1.2V_DPRX

DP_DAP

C30 0.1uF/6/NC

C31 0.1uF/6/NC

R76 270R/6/NC

DP_DAP 17

B18

A18

B19

A19

B20

A20

B21

A21

B23

A23

A22

U8C

DPRX_3N

DPRX_3P

DPRX_2N

DPRX_2P

DPRX_1N

DPRX_1P

DPRX_0N

DPRX_0P

DPRX_AUXN

DPRX_AUXP

DPRXI_REXT

FLI32626H

C18

C20

DPRX_VDD12

DPRX_VDD12

SEQUOIA

DPRX_VSS

DPRX_VSS

C19

C21

+1.2V_DPRX

12

C26

1nF/6

C22

DPRX_VDD12

Display Port

DPRX_VSS

DPRX_VSS

B22

C23

1nF/6

C27

Input

0.1uF/6

C28

+

22uF/6.3V

C25

+3.3V_I/O

+1.2V_DPRX

+3.3V_I/O 6,15,16,17,19

+1.2V_DPRX 19

PROJECT NAME:

A

WLZR-A1

Title

DisplayPort Input

veRrebmuN tnemucoDeziS

A4

D

2009-Mar-20

WLZSA1 ST FLI32626

January 08, 2009

tee

522Thursda

hS:eta

of

18430_503_090202.eps

D2A

090202

Circuit Diagrams and PWB Layouts

A

y,

Main Board: Digital Input Port

+12V_SW

121A40/8/NC

+5V_SW

121A40/8/NC

D

+5VSB

121A40/8

C

B

R100 0R/6

R103 0R/6/NC

A

5

L97

L17

L18

MSTR1_SCL

CON_DIN0
CON_DIN2
CON_DIN4
CON_DIN6
CON_DIN8
CON_DIN10
CON_DIN12
CON_DIN14
CON_DIN16
CON_DIN18
CON_DIN20
CON_DIN22
CON_DIN24
CON_DIN26
CON_DIN28

SD/HD
SDOUT_TDO
SCLK_TCK
F
H

VCC_OPT

12

C32

+

100uF/16V

1 2
3
5 6
7

9 10
11 12
13
15 16
17 18
19 20
21
23
25 26
27 28
29 30
31
33
35 36
37 38
39 40
41 42
43
45 46
47 48
49 50

CON_DIN_CLK0

CON_DIN_CLK1

CN4

5152

FBL112-50S-ND/NC

4

8

14

22
24

32
34

44

RESET_O/C

R247

1
2
3
4

J10

4606-E04N

MSTR1_SDA
RESET_O/C

CON_DIN1
CON_DIN3
CON_DIN5
CON_DIN7

CON_DIN9
CON_DIN11
CON_DIN13
CON_DIN15
CON_DIN17
CON_DIN19
CON_DIN21
CON_DIN23
CON_DIN25
CON_DIN27
CON_DIN29

SMPTE_BYPASS
SDOUT_TDI

FW_EN/DIS

VCC_OPT

NC

EN 42QCG1.0S LA 10.

4 3 2

aCN4

⛤

0R/6
0R/6

0R/6

6

8

7

5

8

6

5

7

6
7
8

6
7
8

R85 0R/6
R86 0R/6

aCN4

⛤

R97 0R/6/NC
R98 0R/6/NC

R99 0R/6/NC
R101 0R/6/NC
R102 0R/6/NC
R104 0R/6/NC

/SRESET

R790R/6
R80

DIN_HREF_DE

R81
R820R/6
R83
R840R/6

45
3
27
1
45
36
2
18
4
36
27
1

0

45
3
27
18
4
36
2
18
45
3
2
1

45
3
2
1

MSTR1_SDA

MSTR1_SCL

DIN_CLK0
DIN_CLK1

DIN_VS

DIN_HS_CS

DIN_HODD

DIN_0

R4P8/R05

DIN_1
DIN_2
DIN_3

DIN_4

R4P8/R06NR

DIN_5
DIN_6
DIN_7

DIN_8

R4P8/R07NR

DIN_9

DIN_10
DIN_11

DIN_12

R4P8/R

DIN_13
DIN_14
DIN_15

DIN_16

R4P8/R09NR

DIN_17
DIN_18
DIN_19

DIN_20
DIN_21
DIN_22
DIN_23

DIN_24
DIN_25
DIN_26
DIN_27

DIN_28
DIN_29

R88 0R/6

R87 0R/6

/SRESET 17

MSTR1_SDA 17,18,22

MSTR1_SCL 17,18,22

R91 0R/6

R90 0R/6

R89 0R/6

V

R105
10K/6

R106 0R/6/NC

31

10K/6

2

Q8
MMBT3904

CON_DIN_CLK0
CON_DIN_CLK1

V
H
F

CON_DIN0
CON_DIN1
CON_DIN2
CON_DIN3
CON_DIN4
CON_DIN5
CON_DIN6
CON_DIN7
CON_DIN8
CON_DIN9
CON_DIN10
CON_DIN11
CON_DIN12
CON_DIN13
CON_DIN14
CON_DIN15
CON_DIN16
CON_DIN17
CON_DIN18
CON_DIN19
CON_DIN20
CON_DIN21
CON_DIN22
CON_DIN23

CON_DIN24
CON_DIN25
CON_DIN26
CON_DIN27

CON_DIN28
CON_DIN29

R107

ۯᆜ

NR

NR

8

RN10 0R/8P4R

RN11 0R/8P4R

ۯᆜ

SDOUT_TDO
SCLK_TCK

SD/HD
FW_EN/DIS
SDOUT_TDI
SMPTE_BYPASS

R108
0R/6

R92 2.7K/6

DIN_CLK0
DIN_CLK1
DIN_HREF_DE
DIN_VS
DIN_HS_CS
DIN_HODD

R94 2.7K/6

R93 2.7K/6

+12V_SW

+5VSB

+3.3V_I/O

DIN_0
DIN_1
DIN_2
DIN_3
DIN_4
DIN_5
DIN_6
DIN_7
DIN_8
DIN_9
DIN_10
DIN_11
DIN_12
DIN_13
DIN_14
DIN_15
DIN_16
DIN_17
DIN_18
DIN_19
DIN_20
DIN_21
DIN_22
DIN_23
DIN_24
DIN_25
DIN_26
DIN_27
DIN_28
DIN_29

R95 2.7K/6

R96 2.7K/6

MPE_JTAG_RST
MPE_JTAG_TDI
MPE_JTAG_TDO

MPE_JTAG_MODE

MPE_JTAG_CLK

+5VSB 7,8,10,19,20,21

E10
D11
B11
C11
A11
D10

C8
D8
E8
A9
B9
C9

D9
A10
B10
C10
E11
A12
B12
C12
D12
E12
A13
B13
C13
D13
E13
A14
B14
C14
D14
E14
A15
B15
C15
D15

+12V_SW 12,20,22

+3.3V_I/O 5,15,16,17,19

PROJECT NAME:

WLZR-A1

Title

Digital Input Port

e

ziS

A4

reb

muN tnemucoD

WLZSA1 ST FLI32626

January 08, 2009

DIN_0CLK
DIN_1CLK
DIN_HREF_DE
DIN_VS
DIN_HS_CS
DIN_ODD

DIN_0
DIN_1
DIN_2
DIN_3
DIN_4
DIN_5
DIN_6
DIN_7
DIN_8
DIN_9
DIN_10
DIN_11
DIN_12
DIN_13
DIN_14
DIN_15
DIN_16
DIN_17
DIN_18
DIN_19
DIN_20
DIN_21
DIN_22
DIN_23
DIN_24
DIN_25
DIN_26
DIN_27
DIN_28
DIN_29

U8F
FLI32626H

MPE_JTAG_RST 21
MPE_JTAG_TDI 21
MPE_JTAG_TDO 21
MPE_JTAG_MODE 21
MPE_JTAG_CLK 21

+5V_SW

S:etaD

1

SEQUOIA DIGITAL

INPUT PORT

+3.3V_I/O

+5V_SW 10,12,20,22

veR

D2A

622Thursda

teeh

of

18430_504_090202.eps

090202

2009-Mar-20

Main Board: VGA Input

A

y,

VGA_5V

5

R109

6.8K/6

Circuit Diagrams and PWB Layouts

VGA_CAB

VGA_CAB 17

EN 43QCG1.0S LA 10.

4 3 2

L19 0R/6

DSUB_RIN

+5VS

R144 0R/6
R682 0R/6

RED_IN

RIN-

1

RED_IN 9,22
RIN- 9,22

D

CN6

DFDS15FR092

C

B

A

17

16

+5VSB

C45

0.1uF/6

D22

UDZ5V6B

2 1

VGA_5V

1
9
2
10
3
11
4
12
5
13
6
14
7
15
8

R662 470R/6/NC

+5VS

R127
470R/6

C46

0.1uF/6

SMT17

1
2
3
4

D28

L20 0R/6

L21 0R/6

VGA_5V

1

DDC_5V

R242
10K/6

PC_SEL

R110

10K/6

2

3

D23

D26

UDZ5V6B

2 1

C39 47pF/6

D29

UDZ5V6B

D30

UDZ5V6B

2 1

C41

47pF/6

2 1

SMTVCC

R129

2.2K/6

R1306.8K/6

C33 NC

EZJZ0V800AA/NC

L22

L23

D27

UDZ5V6B

2 1

L24
L25

C42

47pF/6

ANA_AP431AWLA_SOT23_3P

2

Cathode

1

REF

32

1

D24

BAV99/NC

C40 47pF/6

DDC_WP2,3,17

U12

Anode

C34 NC

0R/6

0R/6

0R/6
0R/6

3

2

3

1

D25

BAV99/NC

R117

2.2K/6

DSUB_SCL
DSUB_SDA

Q9

DTC144E

C35 NC

R118

2.2K/6

1

C36 NC

DSUB_HIN

DSUB_VIN

R120 10K/6
R121 10K/6
R122 10K/6

R123 0R/6
R124 0R/6

32

75_1/2W

R111

C37 NC

75_1/2W

75_1/2W

R113

R112

+5VS

DDC_5V

R673 0R/6/NC
R674 0R/6/NC

8
7
6
5

C43

R114 NC

BAT54C

2

24LC02B

VCC
WP
SCL
SDA

0.1uF/6

R115 NC

R116 NC

U10

A0
A1
A2

VSS

SMTVCC

PC_SEL

3

VGA_SCL
VGA_SDA

DSUB_GIN

DSUB_BIN

R237

0R/6/NC

VGA_SCL 8,9
VGA_SDA 8,9

R119
100R/6

R125
0R/6/NC

R126
100R/6

R128
0R/6/NC

R139 0R/6
R683 0R/6

R140 0R/6
R684 0R/6

R138 0R/6
R141 0R/6
R149 0R/6

1

OE

2
3

74LVC1G126GW

1
2
3

VCC
A
GND

DSUB_HS

OE
A
GND

74LVC1G126GW

DSUB_VS

U9

Y

DSUB_SDA

DSUB_SCL

U11

VCC

Y

GRN_IN

GIN-

BLU_IN

BIN-

SMTVCC

5

4

5

4

C38

0.1uF/6

SMTVCC

GRN_IN 9,22
GIN- 9,22

BLU_IN 9,22
BIN- 9,22

PC_BB 22
PC_GB 22
PC_RB 22

DSUB_HS 9

DSUB_SDA 8
DSUB_SCL 8

C44

0.1uF/6

DSUB_VS 9

PROJECT NAME:

SMT

1

Q10

DTC144E

R131

22K/6

+5VS

VGA_5V

SMTVCC

+5V_SW

DDC_5V

+5VS 2,3,15,17,18,19,20,21,22

VGA_5V

SMTVCC 9

+5V_SW 6,10,12,20,22

DDC_5V 8

WLZR-A1

Title

VGA Input

A4

:et

aD

WLZSA1 ST FLI32626

January 08, 2009

veRrebmuN tnemucoDeziS

D2A

teehS

722Thursda

of

18430_505_090202.eps

090202

2009-Mar-20

Main Board: ISP

5

4 3 2

1

D

C

B

A

A

RXD

TX_MAIN

TXD

RX0

RX_MAIN

RX1

RX1

TX_MAIN

VGA_SCL

DSUB_SCL

TX0

TXD

DDC_5V

TX1

RX0

RX_LPM

RX1

TX1

+5VS

TX1

RX_MAIN

VGA_SDA

RXD

DSUB_SDA

+5VSB

TX_LPM

TX0

RXD1_SMCU

TXD1_SMCU

RX_LPM 15

TX_LPM 15

+5VSB 6,7,10,19,20,21

VGA_SCL 7,9

+5VS 2,3,7,15,17,18,19,20,21,22

VGA_SDA 7,9

TX_MAIN

22

RX0 17

ISP_SEL

17

RX1 17

TX0 1 7

DSUB_SDA7

DDC_5V 7

DSUB_SCL

7

RX_MAIN22

ISP_SEL

17

TX1 1 7

RXD1_SMCU 21

TXD1_SMCU 21

DDC_5V

DDC_5V

+5VSB

Title

veRrebmuN tnemucoDeziS

tee

hS:eta

D

of

WLZSA1 ST FLI32626

D2A

ISP

PROJECT NAME:

WLZR-A1

A4

822Thursda

y,

January 08, 2009

R236 0R/6

R672

10K/6

R6990R/6/NC

R245 0R/6/NC

C112

0.1uF/6/NC

U50

NC7SB3157P6X_NL

B1

1

GND

2

B0

3

A

4

VCC

5

S

6

R239 NC

U42

NC7SB3157P6X_NL

B1

1

GND

2

B0

3

A

4

VCC

5

S

6

U49

NC7SB3157P6X_NL

B1

1

GND

2

B0

3

A

4

VCC

5

S

6

C354

0.1uF/6

R698 0R/6/NC

R243 NC

R238 NC

Q37

DTC144E

1

32

C362

0.1uF/6

R240 0R/6

R680 0R/6/NC

U18

NC7SB3157P6X_NL

B1

1

GND

2

B0

3

A

4

VCC

5

S

6

L105

121A40/8

Q39

DTC144E

1

32

R241 NC

R246 0R/6/NC

R244

10K/6

R681 0R/6/NC

L106

121A40/8/NC

18430_506_090202.eps

090202

Circuit Diagrams and PWB Layouts

EN 44QCG1.0S LA 10.

2009-Mar-20

Main Board: AFE Sequoia

A

y,

ቧ

ᓮ

ش஁೯ֱڤࠐ

FLI32626H

A1
A2
A3
A4
AH

B1
B2

D

B3
B4
BH

C1
C2
C3
C4
CH

SV1
SV2
SV3

PAL

CVI_PR

D-Sub Bin

SVIDEO_C
CVI_G

D-Sub Gin

D-Sub Rin

CVBS
CVI_PB
SVIDEO_Y

C

R216 75R/6/NC

R214 75R/6/NC

R217 75R/6/NC

B

R/G/B ಛu

A

VS_IN

DSUB_HS7 HSB 22

DSUB_VS7

5

R218 75R/6/NC

R224 75R/6/NC

R706

100R/6/NC

Circuit Diagrams and PWB Layouts

NTSC

CVI_PR

D-Sub Bin

SVIDEO_C
CVI_Y

D-Sub Gin

22

D-Sub Rin

CVBS
CVI_PB
SVIDEO_YSV4

R225 75R/6/NC

A2

A4
B2
B3

SV2
SV3
SV4

7,22

R226 75R/6/NC

22

BLU_IN
BIN-7,22

GRN_IN7,22
GIN-7,22

RED_IN7,22
RIN-7,22

layout

VCC

U52

Y

5

4

R708 0R/6

DSUB_HS

DSUB_VS

1

OE

2

A

3

GND

74LVC1G126GW

R159 0R/6
R161 0R/6

R163 0R/6
R166 0R/6

A2

B2
B322

SV222
SV322
SV422

BLU_IN

BIN-

GRN_IN

GIN-

RED_IN

RIN-

R685 0R/6/NC

SMTVCC

R704 10K/6

C366

0.1uF/6

HS_IN 22

VS_IN 22
VSB 22

EN 45QCG1.0S LA 10.

4 3 2

+3.3V_ADC

12

B2
B3

SV2
SV3
SV4

R686 0R/6/NC

C76

22uF/6.3V

A2

R687 0R/6/NC

R186 20R/6

R189 57.6R/6
R190 57.6R/6

R193 20R/6
R194 20R/6

R196 57.6R/6
R198 57.6R/6

R206 57.6R/6
R207 57.6R/6

R210 20R/6
R211 20R/6
R212 20R/6
R213 57.6R/6

R227 20R/6
R229 57.6R/6

R230 20R/6
R231 57.6R/6

R233 20R/6
R234 57.6R/6

VGA_SCL7,8

VGA_SDA7,8

HS_IN

R705

100R/6/NC

C82 0.1uF/6

C84 0.1uF/6/NC

C86 0.1uF/6

C88 0.1uF/6

C90 0.1uF/6

C92 0.1uF/6

C94 0.1uF/6

C96 0.1uF/6

C98 0.1uF/6

C100 0.1uF/6

C102 0.1uF/6

C104 0.1uF/6

C105 0.1uF/6

C107 0.1uF/6

C109 0.1uF/6

C78

+

0.1uF/6

1

OE

2

A

3

GND

74LVC1G126GW

C79

0.1uF/6

C83 0.1uF/6

C85 0.1uF/6/NC

C87 0.1uF/6

C89 0.1uF/6

C91 0.1uF/6

C93 0.1uF/6

C95 0.1uF/6

C97 0.1uF/6

C99 0.1uF/6

C101 0.1uF/6

C103 0.1uF/6

C106 0.1uF/6

C108 0.1uF/6

C110 0.1uF/6

AHS

AVS

VGA_SDA

U51

VCC

Y

A1P

A3P

A_RET1

B1P

B3P

B_RET1

C1P

C3P

C_RET1

SV1P

SV3P

SV_RET

AH

BH

CH

VGA_SCL

SMTVCC

5

4

C80
1nF/6

+1.2V_ADC

C81
1nF/6

A2P

A4P

A_RET2

B2P

B4P

B_RET2

C2P

C4P

C_RET2

SV2P

SV4P

C365

0.1uF/6

L5

H2

H4

E1

J4

G1

K3

J3
F1
F3
K4
F2

J1
H1

G3
G5

K1
E2

K2

J2

G2
G4
H3

M2
M1

L2

L1

L4

L3

N1

N2

N3

N4

U8B

A1P
A2P
A3P
A4P
AN1
AN2

B1P
B2P
B3P
B4P
BN1
BN2

C1P
C2P
C3P
C4P
CN1
CN2

SV1P
SV2P
SV3P
SV4P
SN

AHSP
AHSN

BHSP
BHSN

CHSP
CHSN

AHS

AVS

VGA_SCL

VGA_SDA

ADC_AGND

E4

PROJECT NAME:

AVS

R707 0R/6

AHS

Title

D

12

C77

0.1uF/6

F5

H5

M5

J5

ADC_VDD33

ADC_VDD33

ADC_VDD33

ADC_VDD12

VOUT_1

VOUT_2

SEQUOIA Analog

Front End

ADC_AGND

ADC_AGND

ADC_DGND

F4

M3

FLI32626H

K5

M4

D3

C75

+

22uF/6.3V

+5VS

+5VSB

+3.3V_ADC

+1.2V_ADC

+5VS 2,3,7,15,17,18,19,20,21,22

+5VSB 6,7,8,10,19,20,21

+3.3V_ADC 19

+1.2V_ADC 19

R205 0R/6/NC

R228

0R/6/NC

WLZR-A1

AFE_SEQUOIA

A4

WLZSA1 ST FLI32626

January 08, 2009

tee

hS:eta

1

922Thursda

of

18430_507_090202.eps

veRrebmuN tnemucoDeziS

D2A

090202

2009-Mar-20

Circuit Diagrams and PWB Layouts

5

4

3

2

1

D

D

C C

B B

A

A

DDR_M_RAS
DDR_M_CAS

DDR_M_CKE

DDR_M_BA0

DDR_ODT

DDR_M_CS

DDR_M_A11

DDR_M_BA1

DDR_M_D2

DDR_M_D5

DDR_M_D0

DDR_M_D6

DDR_M_D1

DDR_M_D4

DDR_M_D7

DDR_M_D3

DDR_M_WE

DDR_M_A2

DDR_M_A4

DDR_M_A12

DDR_M_A10

DDR_M_A3

DDR_M_A6

DDR_M_A0

DDR_M_A5

DDR_M_A8

DDR_M_A7

DDR_M_A1

DDR_M_A9

DDR_M_DQS0-

DDR_M_DQS0+

DDR_M_DM1

DDR_M_DM0

DDR_M_DQS1+
DDR_M_DQS1-

DDR_M_CK-

DDR_M_D14

DDR_M_D12

DDR_M_D9
DDR_M_D10
DDR_M_D11

DDR_M_D8

DDR_M_D15

DDR_M_D13

DDR_M_CK+

DDR_M_DQS3+
DDR_M_DQS3-

DDR_M_DQS2+
DDR_M_DQS2-

DDR_M_D24

DDR_M_D31

DDR_M_D29

DDR_M_D25

DDR_M_D30

DDR_M_D26
DDR_M_D27
DDR_M_D28

DDR_M_D22

DDR_M_D16

DDR_M_D23

DDR_M_D20

DDR_M_D18
DDR_M_D19

DDR_M_D21

DDR_M_D17

DDR_M_DM3

DDR_M_DM2

DDR_M_A11

DDR_M_A2

DDR_M_A4

DDR_M_A12

DDR_M_A10

DDR_M_A3

DDR_M_A6

DDR_M_A0

DDR_M_A5

DDR_M_A8

DDR_M_A7

DDR_M_A1

DDR_M_A9

DDR_M_RAS
DDR_M_CAS

DDR_M_CKE

DDR_M_BA0

DDR_ODT

DDR_M_CS

DDR_M_BA1

DDR_M_WE

DDR_M_CK­DDR_M_CK+

iVDD

DDR_A2
DDR_A3

DDR_A1

DDR_A0

DDR_A6

DDR_A4
DDR_A5

DDR_A8
DDR_A9

DDR_A7

DDR_BA0

DDR_A10
DDR_A11

DDR_RAS

DDR_CAS

DDR_BA1

DDR_CS

DDR_WE

DDR_A12

DDR_CK+

DDR_CK-

DDR_CKE

DDR_CAL

DDR_D0
DDR_D1

DDR_D3

DDR_D2

DDR_D5

DDR_D4

DDR_D6
DDR_D7

DDR_DQS0+

DDR_D8

DDR_D10

DDR_DQS0-

DDR_DM0

DDR_D11

DDR_D14

DDR_D12

DDR_D9

DDR_D15

DDR_D13

DDR_DM1
DDR_DQS1+
DDR_DQS1-

DDR_D17

DDR_D16

DDR_D19

DDR_D18

DDR_D21

DDR_D20

DDR_D22
DDR_D23

DDR_D24

DDR_DQS2-

DDR_DQS2+

DDR_DM2

DDR_D26

DDR_D28

DDR_D25

DDR_D29

DDR_D27

DDR_D30

DDR_DM3

DDR_D31

DDR_DQS3-

DDR_DQS3+

Vaa

DDR_M_A2

DDR_M_A4

DDR_CAS

DDR_CKE

DDR_CS

DDR_RAS

DDR_A3

DDR_CK-

DDR_CK+

DDR_M_RAS

DDR_M_CS

DDR_M_CKE
DDR_M_WE

DDR_M_CAS

DDR_M_A3

DDR_A9

DDR_A1

DDR_A0

DDR_A4

DDR_WE

DDR_A2

DDR_A7

DDR_A6

DDR_A8

DDR_A12

DDR_A11

DDR_A10

DDR_M_A12

DDR_M_A10

DDR_M_CK-

DDR_M_CK+

DDR_BA0

DDR_BA1

DDR_M_A0
DDR_M_A6

DDR_M_A8
DDR_M_A11

DDR_M_A9

DDR_M_A5

DDR_M_BA0

DDR_M_BA1

DDR_A5

DDR_M_A1
DDR_M_A7

DDR_ODT

DDR_M_DM0

DDR_M_D3

DDR_M_D1

DDR_D24

DDR_M_D31

DDR_M_D16

DDR_D29

DDR_D11

DDR_M_DQS1­DDR_M_DQS1+

DDR_M_D14

DDR_M_D11

DDR_M_D20

DDR_M_D17

DDR_DQS0­DDR_DQS0+

DDR_D27

DDR_DQS3+

DDR_M_D15

DDR_D2

DDR_M_DQS3+
DDR_M_DQS3-

DDR_M_D28

DDR_D30

DDR_D20
DDR_D19

DDR_D22

DDR_M_DM3

DDR_M_D24

DDR_D26

DDR_M_D12

DDR_M_D22

DDR_M_D19

DDR_M_D6

DDR_M_D25

DDR_M_D30

DDR_M_D26

DDR_M_D21

DDR_D5
DDR_D7

DDR_M_D27

DDR_DM0

DDR_D0

DDR_DM3

DDR_D13

DDR_M_DQS2+

DDR_M_DQS2-

DDR_D9

DDR_D10

DDR_D14

DDR_D15

DDR_DM1

DDR_D8

DDR_D4

DDR_DQS2-

DDR_DQS2+

DDR_M_D4

DDR_M_D23

DDR_DQS3-

DDR_D3

DDR_M_DM2

DDR_DM2

DDR_M_D13

DDR_D28

DDR_M_D10

DDR_DQS1-

DDR_DQS1+

DDR_D17

DDR_D6

DDR_D23

DDR_D16

DDR_M_DM1

DDR_D1

DDR_M_D18

DDR_D25

DDR_M_D0

DDR_M_D5

DDR_D21

DDR_M_D29

DDR_M_D8

DDR_M_DQS0+

DDR_M_D7

DDR_D31

DDR_M_D9

DDR_M_DQS0­DDR_M_D2

DDR_D12

DDR_D18

+3.3V_DDR

+5VSB

+5V_SW

+3.3V_DDR 19

+5VSB 6,7,8 ,19,20,21

+5V_SW 6,12,20 ,22

+1.8V_DDR

+0.9V_DDR_VREF

+1.8V_DDR

+0.9V_DDR_VREF

+1.8V_DDR_S

+0.9V_DDR_VREF

+1.8V_DDR_S

+3.3V_DDR

+1.8V_DDR_S +1.8 V_DDR

+0.9V_DD R_VREF

+1.8V_DDR

+5V_SW

+5VSB

Title

ve

R

rebmuN tnemuco

De

ziS

t

eehS

:eta

D

of

WLZSA1 ST FLI32626

D2A

Frame Store DDR Interface

PROJECT NAME:

WLZR-A1

Custom

10 22

Thursday, January 08, 2009

RN13 22R/4P2R

1
23

4

C349

0.1uF/6

R454 4.42K/6/1%

+

C118
47uF/6.3V

C133
10nF/6

RN27 22/8P4R

18
27
36
45

C130
1nF/4

R250
294R/4/ 1%

C154
10nF/6

C140
1nF/4

C170
10uF/1206/16V

C181
1uF/6

C177
1nF/4

C123
1nF/4

RN30 22R/4P2R

1
2

3

4

L72

121A

40/8

R659 2 00/6/1%

U31
CM3202

VIN

1

NC

2

NC4GND

5

GND

6

VDDQ

8

ADJSD

7

VTT

3

GND PAD

9

C166
1nF/4

+

C151

47uF/6.3V

RN29 22R/4P2R

1
2 3

4

C141
10nF/6

+

C172

47uF/6.3V

RN16 22R/4P2R

1
23

4

RN36 22R/4P2R

1
2

3

4

C178
10nF/6

C136
10nF/6

+

C347

220uF/16V

12

C134
10uF/1206/16V

C124
1nF/4

C155
1nF/4

RN33 22/8P4R

18
27
36
45

R453 10K/6/1%

L68

121A40/8/NC

C137
10nF/6

RN26 22R/4P2R

1
2

3

4

RN18 22R/4P2R

1
23

4

C126
1nF/4

C116
1uF/6

C142
1nF/4

C171

0.1uF/4

C179
1nF/4

RN22 22R/4P2R

1
2

3

4

L70

121A40/8

C156
1nF/4

SEQUOIA Frame Store

DDR Interface

U8A

FLI32626H

DDR_D0

D20

DDR_D4

L19

DDR_D2

G22

DDR_D3

H23

DDR_D1

K20

DDR_D5

E19

DDR_D6

J20

DDR_D7

D21

DDR_DM0

H20

DDR_DQS0

G19

DDR_DQS_N

G20

DDR_D8

E22

DDR_D9

K23

DDR_D10

H21

DDR_D11

J21

DDR_D12

K22

DDR_D13

E21

DDR_D14

K21

DDR_D15

D23

DDR_DM1

J22

DDR_DQS1

F22

DDR_DQS1_N

F23

DDR_D16

V19

DDR_D17

AC21

DDR_D18

Y20

DDR_D19

AB21

DDR_D20

AC19

DDR_D21

U20

DDR_D22

AB20

DDR_D23

U19

DDR_DM2

AA20

DDR_DQS2

W19

DDR_DQS2_N

W20

DDR_D24

T23

DDR_D25

AA22

DDR_D26

Y23

DDR_D27

W22

DDR_D28

AA21

DDR_D29

U22

DDR_D30

AB23

DDR_D31

U21

DDR_DM3

Y21

DDR_DQS3

V22

DDR_DQS3_N

V23

DDR_A8

N23

DDR_A1

R23

DDR_A11

N22

DDR_A3

P19

DDR_A0

M21

DDR_BA1

P21

DDR_A6

N21

DDR_A7

T22

DDR_A4

M20

DDR_A9

P23

DDR_CKE

R20

DDR_A2

N20

DDR_A12

T21

DDR_BA0

R21

DDR_A5

P22

DDR_CAS_N

M19

DDR_RAS_N

L21

DDR_CS_N

L20

DDR_WE_N

P20

DDR_VDDQ

R22

DDR_A10

T20

DDR_ODT

J19

DDR_VDDQ

E20

DDR_VDDQ

E23

DDR_VDDQ

G21

DDR_VDDQ

G23

DDR_VDDQ

J23

DDR_VDDQ

L22

DLL_Vaa1

K19

DDR_VDDQ

U23

DDR_VDDQ

W21

DDR_VDDQ

W23

DDR_VDDQ

AA23

DDR_VDDQ

AC20

DDR_VDDQ

AC22

DDR_VDDQ

AC23

DDR_VSSO

D19

DDR_VSSO

D22

DDR_VSSO

F20

DDR_VSSO

H19

DDR_VSSO

H22

DDR_VSSO

M22

DDR_VSSO

V21

DDR_VSSO

Y19

DDR_VSSO

Y22

DDR_VSSO

AB19

DDR_VSSO

AB22

DDR_CK_N

M23

DLL_Vaa2

T19

DDR_CK

L23

DDR_VREF1

N19

DDR_VREF2

V20

DDR_VREF0

F21

DDR_CAL

R19

DDR_iVDD2

AA19

DDR_iVDD1

F19

R660
330R/6/1%

+

C139

47uF/6.3V

C160
10nF/6

L33

121A

40/8

RN40 22R/4P2R

1
23

4

C113

0.1uF/4

C131
10nF/6

RN28 22R/4P2R

1
2

3

4

C143
10nF/6

U20

EDE2516ABSE

VDD

A1

NC

A2

VSS

A3

VSSQ

A7

/UDQS

A8

VDDQ

A9

DQ14

B1

VSSQ

B2

UDM

B3

UDQS

B7

VSSQ

B8

DQ15

B9

VDDQ

C1

DQ9

C2

VDDQC3VDDQ

C7

DQ8

C8

VDDQ

C9

DQ12

D1

VSSQ

D2

DQ11

D3

DQ10

D7

VSSQ

D8

DQ13

D9

VDD

E1

NC

E2

VSS

E3

VSSQ

E7

/LDQS

E8

VDDQ

E9

DQ6

F1

VSSQ

F2

LDM

F3

LDQS

F7

VSSQ

F8

DQ7

F9

VDDQ

G1

DQ1

G2

VDDQG3VDDQ

G7

DQ0

G8

VDDQ

G9

DQ4

H1

VSSQ

H2

DQ3

H3

DQ2

H7

VSSQ

H8

DQ5

H9

VDDL

J1

VREF

J2

VSSJ3VSSDL

J7

CK

J8

VDD

J9

CKE

K2

/WE

K3

/RAS

K7

/CK

K8

ODT

K9

BA0

L2

BA1

L3

/CAS

L7

/CS

L8

A10

M2

A1

M3

A2

M7

A0

M8

VDD

M9

VSS

N1

A3

N2

A5

N3

A6

N7

A4

N8

A7

P2

A9

P3

A11

P7

A8

P8

VSS

P9

VDD

R1

A12

R2

NC

R3

NC

R7

NC

R8

RN14 22R/4P2R

1
2

3

4

C125
1nF/4

C180
10nF/6

RN34 22/8P4R

18
27
36
45

C127
10nF/6

C138

0.1uF/4

C161
10nF/6

+

C114

47uF/6.3V

L32

121A

40/8

RN17 22R/4P2R

1

2 3

4

RN35 22R/4P2R

1
23

4

C144
1nF/4

C182
1nF/4

L65

121A

40/8

C158
1nF/4

RN15 22R/4P2R

1

2

3
4

C162
1nF/4

+

C301

100uF/16V

RN39 22R/4P2R

1
2

3

4

C148
1uF/6

C173
1nF/4

+

C135
47uF/6.3V

C119
10nF/6

L34

121A40/8

C128
1nF/4

+

C159
47uF/6.3V

U39

AIC1084/TO263

ADJ/GND

1

VOUT

2

VIN

3

C145
10nF/6

RN21 22R/4P2R

1

2

3
4

RN20 22/8P4R

18
2

7

36
4

5

C167
10nF/6

C157
1nF/4

C163
10nF/6

RN25 22/8P4R

1

8

27
36
45

C348

0.1uF/6

C183

0.1uF/4

C149
1nF/4

C174
10nF/6

C120
10nF/6

RN38 22R/4P2R

1
23

4

C302

0.1uF/6

C132
1nF/4

C146
1nF/4

C117

0.1uF/4

RN23 22R/4P2R

1
23

4

RN31 22R/4P2R

1
2

3

4

C153
10nF/6

C164
1nF/4

C129
10nF/6

C168
1nF/4

R248
10K/4

RN24 22R/4P2R

1
2

3

4

C350

0.1uF/6

+

C351

47uF/6.3V

C150

0.1uF/4

C175
1nF/4

R447 0R/6

C121
10nF/6

C147
10nF/6

C115
1nF/4

U19

EDE2516ABSE

VDD

A1

NC

A2

VSS

A3

VSSQ

A7

/UDQS

A8

VDDQ

A9

DQ14

B1

VSSQ

B2

UDM

B3

UDQS

B7

VSSQ

B8

DQ15

B9

VDDQ

C1

DQ9

C2

VDDQC3VDDQ

C7

DQ8

C8

VDDQ

C9

DQ12

D1

VSSQ

D2

DQ11

D3

DQ10

D7

VSSQ

D8

DQ13

D9

VDD

E1

NC

E2

VSS

E3

VSSQ

E7

/LDQS

E8

VDDQ

E9

DQ6

F1

VSSQ

F2

LDM

F3

LDQS

F7

VSSQ

F8

DQ7

F9

VDDQ

G1

DQ1

G2

VDDQG3VDDQ

G7

DQ0

G8

VDDQ

G9

DQ4

H1

VSSQ

H2

DQ3

H3

DQ2

H7

VSSQ

H8

DQ5

H9

VDDL

J1

VREF

J2

VSSJ3VSSDL

J7

CK

J8

VDD

J9

CKE

K2

/WE

K3

/RAS

K7

/CK

K8

ODT

K9

BA0

L2

BA1

L3

/CAS

L7

/CS

L8

A10

M2

A1

M3

A2

M7

A0

M8

VDD

M9

VSS

N1

A3

N2

A5

N3

A6

N7

A4

N8

A7

P2

A9

P3

A11

P7

A8

P8

VSS

P9

VDD

R1

A12

R2

NC

R3

NC

R7

NC

R8

R249 200/4/1%

C152
10nF/6

RN12 22R/4P2R

1

2

3
4

C169
10nF/6

R251 200/4/1%

RN19 22R/4P2R

1

2 3

4

+

C300

100uF/16V

C176
10nF/6

RN32 22R/4P2R

1
2

3

4

RN37 22/8P4R

18
2

7

3

6

45

C165
10nF/6

C122
10nF/6

18430_508_090202.eps

090202

Main Board: Frame Store DDR interface

EN 46QCG1.0S LA 10.

2009-Mar-20

Circuit Diagrams and PWB Layouts

A

y,

Main Board: Panel Interface Sequoia

5

EN 47QCG1.0S LA 10.

4 3 2

+3.3V_LVDS

1

C185
1nF/6

D

U8E

C

SEQUOIA LVDS /

B

W17

AA13

LVDS_33

LVDS_33

TTL

LVDS_O_CH0P
LVDS_O_CH0N

LVDS_O_CH1P
LVDS_O_CH1N

LVDS_O_CH2P
LVDS_O_CH2N

LVDS_O_CH3P
LVDS_O_CH3N

LVDS_O_CH4P
LVDS_O_CH4N

LVDS_O_CLKP

LVDS_O_CLKN

LVDS_E_CH0P
LVDS_E_CH0N

LVDS_E_CH1P
LVDS_E_CH1N

LVDS_E_CH2P
LVDS_E_CH2N

LVDS_E_CH3P
LVDS_E_CH3N

LVDS_E_CH4P
LVDS_E_CH4N

LVDS_E_CLKP

LVDS_E_CLKN

C186

0.1uF/6

AA18
Y18

AC18
AB18

AA17
Y17

AC17
AB17

AC16
AB16

AA16
Y16

Y15
W15

AB15
AA15

AC14
AC15

AB14
AA14

AC13
AB13

Y14
W14

12

C184

+

22uF/6.3V

LVDS_O_CH0+
LVDS_O_CH0-

LVDS_O_CH1+
LVDS_O_CH1-

LVDS_O_CH2+
LVDS_O_CH2-

LVDS_O_CH3+
LVDS_O_CH3-

LVDS_O_CH4+
LVDS_O_CH4-

LVDS_O_CLK+

LVDS_O_CLK-

LVDS_E_CH0+
LVDS_E_CH0-

LVDS_E_CH1+
LVDS_E_CH1-

LVDS_E_CH2+
LVDS_E_CH2-

LVDS_E_CH3+
LVDS_E_CH3-

LVDS_E_CH4+
LVDS_E_CH4-

LVDS_E_CLK+

LVDS_E_CLK-

+3.3V_LVDS

LVDS_O_CH0+
LVDS_O_CH0-

LVDS_O_CH1+
LVDS_O_CH1-

LVDS_O_CH2+
LVDS_O_CH2-

LVDS_O_CH3+
LVDS_O_CH3-

LVDS_O_CH4+
LVDS_O_CH4-

LVDS_O_CLK+

LVDS_O_CLK-

LVDS_E_CH0+
LVDS_E_CH0-

LVDS_E_CH1+
LVDS_E_CH1-

LVDS_E_CH2+
LVDS_E_CH2-

LVDS_E_CH3+
LVDS_E_CH3-

LVDS_E_CH4+
LVDS_E_CH4-

LVDS_E_CLK+

LVDS_E_CLK-

+3.3V_LVDS 12,19

LVDS_O_CH0+ 12
LVDS_O_CH0- 12

LVDS_O_CH1+ 12
LVDS_O_CH1- 12

LVDS_O_CH2+ 12
LVDS_O_CH2- 12

LVDS_O_CH3+ 12
LVDS_O_CH3- 12

LVDS_O_CH4+ 12
LVDS_O_CH4- 12

LVDS_O_CLK+ 12
LVDS_O_CLK- 12

LVDS_E_CH0+ 12
LVDS_E_CH0- 12

LVDS_E_CH1+ 12
LVDS_E_CH1- 12

LVDS_E_CH2+ 12
LVDS_E_CH2- 12

LVDS_E_CH3+ 12
LVDS_E_CH3- 12

LVDS_E_CH4+ 12
LVDS_E_CH4- 12

LVDS_E_CLK+ 12
LVDS_E_CLK- 12

FLI32626H

LVDS_GND

LVDS_GND

W16

W18

PPWR

PBIAS

Y12

W12

PPWR

PBIAS

PPWR

PBIAS

PPWR 12

PBIAS 20

PROJECT NAME:

A

WLZR-A1

Title

Panel Interf_SEQUOIA

veRrebmuN tnemucoDeziS

A4

WLZSA1 ST FLI32626

January 08, 2009

11 22Thursda

teehS:etaD

of

18430_509_090202.eps

D2A

090202

2009-Mar-20

Circuit Diagrams and PWB Layouts

A

y,

Main Board: Panel Interface

5

D

13

C

UD_D

UD_D

LVDS_O_CH4+

LVDS_E_CH4+

4 3 2

+3.3V_LVDS

R252
NC

R259
0R/6/NC

R260 0R/6

+3.3V_LVDS

R264

NC

R266
0R/6

VBR_OUT LVDS_P39

R268

0R/6/NC

R253

NC

LVDS_O_CH4+_CONN

LVDS_O_CH3+
LVDS_O_CLK+
LVDS_O_CH2+

LVDS_O_CH1+
LVDS_O_CH0+
LVDS_E_CH3+

R265

LVDS_E_CLK+

NC

LVDS_E_CH2+
LVDS_E_CH1+
LVDS_E_CH0+

LVDS_E_CH4+_CONN

LVDS_P37

R269

0R/6/NC

R254
NC

LVDS_P7

TP2

R270
NC

1
3
5
7

9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

43 44

CN8

EIC_3950_F

EN 48QCG1.0S LA 10.

PANEL_POWER

42

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

41

40C_00R_40P

+3.3V_LVDS

NC

R271
NC

R256

NC

R255

LVDS_P6

LVDS_O_CH4-_CONN

LVDS_O_CH3­LVDS_O_CLK­LVDS_O_CH2-

LVDS_O_CH1­LVDS_O_CH0­LVDS_E_CH3-

LVDS_E_CLK­LVDS_E_CH2­LVDS_E_CH1­LVDS_E_CH0-

LVDS_E_CH4-_CONN
SELLVDS
LVDS_P40

+3.3V_LVDS

R262

NC

R272

0R/6

R257

R258

NC

0R/6/NC

R261 0R/6

R263
NC

R267
0R/6

R273
0R/6/NC

LVDS_O_CH4-

LVDS_E_CH4-

EXT_VBR

RL_L 13

LVDS_O_CH0+11
LVDS_O_CH0-11

LVDS_O_CH1+11

LVDS_O_CH1-11

LVDS_O_CH2+11
LVDS_O_CH2-11

LVDS_O_CH3+11
LVDS_O_CH3-11

LVDS_O_CH4+11

LVDS_O_CH4-11

LVDS_O_CLK+11

11

LVDS_O_CLK-

11

LVDS_E_CH0+
LVDS_E_CH0-11

LVDS_E_CH1+11

LVDS_E_CH1-11

LVDS_E_CH2+11

11

LVDS_E_CH2-

LVDS_E_CH3+11

11

LVDS_E_CH3-

11

LVDS_E_CH4+
LVDS_E_CH4-11

11

LVDS_E_CLK+
LVDS_E_CLK-11

1

LVDS_O_CH0+

LVDS_O_CH0-

LVDS_O_CH1+

LVDS_O_CH1-

LVDS_O_CH2+

LVDS_O_CH2-

LVDS_O_CH3+

LVDS_O_CH3-

LVDS_O_CH4+

LVDS_O_CH4-

LVDS_O_CLK+

LVDS_O_CLK-

LVDS_E_CH0+

LVDS_E_CH0-

LVDS_E_CH1+

LVDS_E_CH1-

LVDS_E_CH2+

LVDS_E_CH2-

LVDS_E_CH3+

LVDS_E_CH3-

LVDS_E_CH4+

LVDS_E_CH4-

LVDS_E_CLK+

LVDS_E_CLK-

+12V_SW

DCR

R647 NC

B

PWM

R649 NC

EXT_VBR

R650 NC

R653 NC

VBR_OUT

C343
NC

C344
NC

R651

NC

R652 NC

31

Q36
MMBT3904/NC

R648
NC

2

+5V_SW

+3.3V_COMMON

+5V_SW

R654
NC

PWM1 17

L35

121A40/8

L37

121A40/8/NC

C187

100uF/16V

12

+

C188

2.2nF/6

C190 0.1uF/6

R274 10K/6

C193

0.1uF/6

2
3
4 5

R276

2.2K/6

Q17

MMBT3904

81
7
6

Q16
SI9435

31

L36

121A40/8

D32

R275 2.2K/6/NC

SML-310/NC

C194

0.1uF/6

2

R278

R277

2.2K/6

1M/6

PPWR

PANEL_POWER

C191

0.1uF/6/NC

12

+

C192 0.1uF/6

C189 100uF/16V

PPWR 11

PROJECT NAME:

+12V_SW

A

+5V_SW

+3.3V_LVDS

+12V_SW 6,20,22

+5V_SW 6,10,20,22

+3.3V_LVDS 11,19

WLZR-A1

Title

Panel Interface

S

A4

:etaD

WLZSA1 ST FLI32626

January 08, 2009

veRrebmuN tnemucoDezi

D2A

of

12 22Thursda

t

S

eeh

18430_510_090202.eps

090202

2009-Mar-20

Circuit Diagrams and PWB Layouts

A

y,

Main Board: I2S Audio Input

5

D

C

AA8

AB8

Y8

AA7

EN 49QCG1.0S LA 10.

4 3 2

U8M

SEQUOIA I2S

I2S_DOUT1

I2S_DIN

I2S_WS_IN

I2S_CLK_IN

SPDIF_IN

FLI32626H

I2SB_DOUT1

I2SB_DOUT2

I2SB_WS_OUT

I2SB_CLK_OUT

SPDIF_OUT

IS2B_MCLK_OUT/IN

DCLK/I2SA_CLK_OUT

DVS/I2SA_DOUT0

DHS/I2SA_WS_OUT

DEN/I2S_A_MCLK_OUT/IN

Y9

I2S_DOUT2

AA9

I2S_WS_OUT

AC9

I2S_CLK_OUT

AB9

SPDIF_OUT

AB7

AC8

DCLK/I2S_CLK_OUT

AB12

DVS/I2S_DOUT0

AA12

DHS/I2S_WS_OUT

AC12

DEN/I2S_A_MCLK_OUT/IN

Y13

17

NVRAM_WP17

HDCP_WP

I2S_DOUT1 17

I2S_DOUT2 17

I2S_WS_OUT 17

I2S_CLK_OUT 17

R282 0R/6

R283 0R/6

R285 0R/6

R286 0R/6

NVRAM_WP

HDCP_WP

1

R280
300R/6/NC

C196

0.1uF/6/NC

UD_D 12

RL_L 12

B

+3.3V_I/O

+5VSB

+3.3V_I/O 5,6,15,16,17,19

+5VSB 6,7,8,10,19,20,21

PROJECT NAME:

A

WLZR-A1

Title

I2S Audio Input

veRrebmuN tnemucoDeziS

A4

D

WLZSA1 ST FLI32626

January 08, 2009

tee

13 22Thursda

hS:eta

of

18430_511_090202.eps

D2A

090202

2009-Mar-20

Circuit Diagrams and PWB Layouts

5

4 3 2

1

D

C

B

A

A

+3.3V_AUD

+1.2V_AUD

AUD_OUT_LS_L

AUD_OUT_LS_R

SUB_OUT

AUD_IN_L1

AUD_IN_L1
AUD_IN_R1

AUD_IN_R1

AUD_SUB_OUT

AUD_R1

AUD_L2

AUD_R2

AUD_L1

+3.3V_AUD 19

+1.2V_AUD 19

AUD_IN_L222

AUD_IN_R222

AUD_OUT_LS_L 22

AUD_OUT_LS_R 22

+3.3V_AUD

+1.2V_AUD

+3.3V_AUD

Title

veRrebmuN tnemucoDeziS

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hS:eta

D

of

WLZSA1 ST FLI32626

D2A

Analog Audio Input

PROJECT NAME:

WLZR-A1

A4

14 22Thursda

y,

January 08, 2009

LINE OUT

SUBWOOFER

+

C208

10uF/16V

C214 0.47uF/6

C204
1nF/6

D44

EZJZ0V800AA/NC

R658100K/6/NC

+

C209

10uF/16V

C216 0.47uF/6

L42

121A40/8

C345 100pF/6/NC

CN10

EIC_4500-E02N/NC

1

2

C218 0.47uF/6

R320

4.7K/6

C225 1uF/6

C206

0.1uF/6

C220 0.47uF/6

SEQUOIA Audio

CODEC

U8H

FLI32626H

AUD_L1_IN

R2

AUD_L2_IN

R4

AUD_L3_IN

T2

AUD_L4_IN

T4

AUD_L5_IN

U2

AUD_R1_IN

R1

AUD_R2_IN

R3

AUD_R3_IN

T1

AUD_R4_IN

T3

AUD_R5_IN

U1

AUD_L1_OUT

W1

AUD_R1_OUT

V2

AUD_L2_OUT

W2

AUD_R2_OUT

V3

AUD_OUT_LS_L

U4

AUD_OUT_LS_R

V1

AUD_HP_L_OUT

W4

AUD_SUB_OUT

U3

AUD_HP_R_OUT

V4

AUD_MONO_IN

P4

AUD_VREFP

P1

AUD_VREFM

P2

AUD_VREFN

P3

AUD_VDD_3.3U5AUD_VDD_3.3

W5

AUD_HPVDD_3.3.

W3

ADC_VDD_1.2

V5

AUD_GND

P5

AUD_GNDR5AUD_GND

T5

AUD_HPGND

Y2

SIF1

D2

SIF2

D1

SIF_RTN

E3

C223 1uF/6

C346 100pF/6/NC

R322
47K/6

+

C210
22uF/6.3V

12

D43

EZJZ0V800AA/NC

+

C207
22uF/6.3V

12

C203

0.1uF/6

L98 0R/6/NC

C211

0.1uF/6

R656 1K/6

JACK1/NC

PHONEJACK STEREO

3

5

4

2

1

678

C213

0.1uF/6

L99 0R/6/NC

C212

0.1uF/6

R655 1K/6

C232
1uF/6

C205

0.1uF/6

R657

100K/6/NC

18430_512_090202.eps

090202

Main Board: Analog Audio Input

EN 50QCG1.0S LA 10.

2009-Mar-20

Circuit Diagrams and PWB Layouts

5 4

3

2

1

D

C

B

A

A

XTA L

TCLK

OBUFC_CLK

+3.3V_LPM_S +1.2V_LPM_S

+3.3V_I/O

+3.3V_LPM

+1.2V_LPM

RX_LPM

TX_LPM

+5VS

UDI_LPM

IR0

UDO_LPM

CEC_LPM

TXP

TXP
RXP

RXP

HW_RESET

HA_CEC

HA_CEC

IR_LPM21

RX_LPM8

TX_LPM8

+3.3V_I/O 5,6,16,17,19

+3.3V_LPM 19,20

+1.2V_LPM 20

+5VS 2,3,7,17,18,19,20,21,22

PWRKEY_LPM21

SYSTEM_RESET

RXP

TXP

SYS_POWERON17,19,21,22

HA_CEC 2

CEC_POWERON

21

+1.2V_LPM

+3.3V_LPM

+3.3V_LPM +3.3V_LPM

+3.3V_LPM

+1.2V_LPM

+3.3V_I/O

+5VS

+5VS

+3.3V_LPM

+5VS

+5VS

Title

veRrebmuN tnemucoDezi

S

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:et

aD

of

WLZSA1 ST FLI32626

D2A

Low Power Monitor

PROJECT NAME:

WLZR-A1

A4

15 22Thursday, January 08, 2009

1

0

0

FUNCTION

1

0

TEST_

EN1

Regular mission mode with POR delayed output tied to internal Resetn

JTAG boundary scan enable. 5-additional pins become enabled for JTAG

1

Regular mission mode with POR non-delayed output tied to internal
RESETn (For ATE vectors)

SCAN is enabled here and ALTERNATE(TBD) pad is used as internal RESETn substitute

10

TEST_
EN0

C243

0.1uF/6

R677

0R/6/NC

+

C242
22uF/6.3V

12

C239

0.1uF/6

R330

100R/6

C244

1nF/6

R334 10K/6/NC

R343 10K/6/NC

R336
10K/6/NC

C246

0.1uF/6

SEQUOIA Low

Power Monitor

U8K

FLI32626H

CEC_LPM

Y1

IR_LPM

AA2

UDO_LPM

AB1

UDI_LPM

AC1

LPM_GPIO0

AA3

LPM_GPIO3

AA1

I/O_VDD_33_LPM

Y3

CORE_12_LPM

Y4

D33

UDZ5V6B/NC

21

R638
0R/6

+

C237

22uF/6.3V

12

C245
1nF/6

R513 0R/6

R342
10K/6

C247
22pF/6

C238

0.1uF/6

R512 0R/6/NC

CN11

4500-E04N

1
2
3
4

R346 0R/6

L44
0R/8

C249
22pF/6/NC

R332 10K/6/NC

R710
0R/6/NC

R331

100R/6

Q41
MMBT3904

31

2

R341 0R/6

C250
22pF/6/NC

D34

UDZ5V6B/NC

21

R711

4.7K/6

X1

19.6608MHz

R335 10K/6/NC

R340 10K/6/NC

R333 0R/6

L43
0R/8

C248
22pF/6

R709
10K/6

+

C240
22uF/6.3V

12

TP3

+

C241

22uF/6.3V

12

SEQUOIA Test

U8G

FLI32626H

TEST_EN0

AB2

TEST_EN1

AC2

RESETn

AC7

R639
0R/6

TP4

SEQUOIA Internal

Clock Generation

U8L

FLI32626H

XTAL

AC4

TCLK

AC5

OBUF_C

AA4

RPLL_3.3

AB5

MPLL_3.3

AB3

RPLL_1.2

AC3

MPLL_1.2

AA5

RPLL_GND

AB4

MPLL_GND

Y5

R345 0R/6

18430_513_090202.eps

090202

Main Board: Low Power Monitor

EN 51QCG1.0S LA 10.

2009-Mar-20

Circuit Diagrams and PWB Layouts

5

4 3 2

1

D

C

B

A

A

+3V3_I/O_SEQ

+1.2V_CORE

+3.3V_I/O

+1.2V_CORE_SEQ

+1.2V_CORE 19

+3.3V_I/O 5,6,15,17,19

+3.3V_I/O

+1.2V_CORE

Title

veRrebmuN tnemucoDeziS

teeh

S:eta

D

of

WLZSA1 ST FLI32626

B2A

SEQUOIA Power

PROJECT NAME:

WLZR-A1

A4

16 22Thursda

y,

January 08, 2009

C257

0.1uF/6

C264

1nF/6

C254

0.1uF/6

C266

0.1uF/6

C263

0.1uF/6

C267

0.1uF/6

C260

1nF/6

C268

0.1uF/6

C259

0.1uF/6

C256

0.1uF/6

+

C251

22uF/6.3V

12

C253

1nF/6

C269
1nF/6

C252

0.1uF/6

C270
1nF/6

SEQUOIA System
Power / Ground

U8N

FLI32626H

CORE_1.2J9CORE_1.3

J10

CORE_1.4

J14

CORE_1.5

J15

CORE_1.6K9CORE_1.7

K15

CORE_1.8

L15

CORE_1.9

P9

CORE_1.10

P15

CORE_1.11R9CORE_1.12

R10

CORE_1.13

R14

CORE_1.14

R15

I/O_VDD_3.3E9I/O_VDD_3.4

E15

I/O_VDD_3.5N5I/O_VDD_3.6W8I/O_VDD_3.7

W10

I/O_VDD_3.8

W13

DGND

J11

DGND

J12

DGND

J13

DGND

K10

DGND

K11

DGND

K12

DGND

K13

DGND

K14

DGND

L9

DGND

L10

DGND

L11

DGND

L12

DGND

L13

DGND

L14

DGND

M9

DGND

M10

DGND

M11

DGND

M12

DGND

M13

DGND

M14

DGND

M15

DGND

N9

DGND

N10

DGND

N11

DGND

N12

DGND

N14

DGND

N13

DGND

N15

DGND

P10

DGND

P11

DGND

P13

DGND

P12

DGND

P14

DGND

R11

DGND

R12

DGND

R13

C262

1nF/6

C271
1nF/6

C261

0.1uF/6

C258

1nF/6

C255

1nF/6

+

C265

22uF/6.3V

12

18430_514_090202.eps

090202

Main Board: Sequoia Power

EN 52QCG1.0S LA 10.

2009-Mar-20

Circuit Diagrams and PWB Layouts

5

4 3 2

1

D

C

B

A

A

SPI_HOLDN

TX1

SPI_DO

DDC_WP

/SRESET
FAST_HP_A

DVI_DETECT
HDMI_HP_B

HDMI_HP_A

VGA_CAB

DP_DAP

RX0

SPI_WPN

SPI_DI

TX0

RX1

NVRAM_WP

HDCP_WP

+5VS

+3.3V_I/O

NVRAM_WP

HDCP_WP

MSTR1_SDA

MSTR1_SCL

COM_SCL

COM_SDA

MSTR1_SCL

OCM_INT0

RXP

TXP

MSTR1_SCL

MSTR1_SDA

SMCU3_SCL

SMCU3_SDA

SMCU3_SCL

SMCU3_SDA

MSTR1_SDA

COM_SCL

MSTR1_SCL

INT

SPI_CLK

MSTR1_SCL

MSTR1_SDA

SPI_DO

MSTR0_SDA

MSTR1_SDA

MSTR0_SCL

PWM3

SPI_DI

SPI_CLK

SMT

COM_SDA

COM_SDA
COM_SCL

COM_SDA

SPI_CEN

COM_SCL

OCM_INT0

ACD

+5V_SW

+3.3V_SMCU

PBIAS2

BPCCE_SW
APCCE_SW

MSTR0_SDA

2

MSTR1_SDA

6,18,22

MSTR1_SCL

6,18,22

TX18

RX18

TX0

8

RX0

8

MAIN_MUTE 22

INT

PWM3 20

PWM1 12

I2S_DOUT1 13
I2S_DOUT2 13

I2S_WS_OUT 13

I2S_CLK_OUT 13

/SRESET 6

HDMI_HP_A 2

MSTR0_SCL

2

FAST_HP_A 2

DDC_WP 2,3,7

DVI_DETECT 3
HDMI_HP_B 3

VGA_CAB 7

+5VS 2,3,7,15,18,19,20,21,22

+3.3V_I/O 5,6,15,16,19

DP_HP5

DP_DAP 5

NVRAM_WP 13

HDCP_WP 13

MSTR1_SCL 6,18

,

MSTR1_SDA 6,18,2

2

ISP_SEL 8

Status1

21

TXP 1 5

RXP 15

SMCU3_SDA 21

SMCU3_SCL 21

SMT

7

LED_RED 18
LED_GREEN 18

Status2

21

STBY 20,22

COM_SDA 22

COM_SCL 22

SYS_POWERON15,19,21,22

ACD 20,22

DIGI_SAVING-3V3 21

+5V_SW 6,10,12,20,22

+3.3V_SMCU 2,18,20,21,22

PBIAS2 20

BPCCE_SW 3
APCCE_SW 2

+3.3V_I/O

+3.3V_I/O

+5VS

+3.3V_I/O

+3.3V_I/O

+3.3V_I/O

+3.3V_SMCU

+3.3V_SMCU

+3.3V_I/O

Title

veRrebmuN tnemucoDeziS

tee

hS:eta

D

of

WLZSA1 ST FLI32626

D2A

OCM Peripherals

PROJECT NAME:

WLZR-A1

A4

17 22Thursda

y,

January 08, 2009

16Mbit

DPRX_SDA

DPRX_SCL

SPI_DI CN1207.3

I2S_CLK_OUT CN1207.7

I2S_DOUT1 CN1207.1

I2S_DOUT2 CN1207.2

SPI_DO CN1207.4

I2S_WS_OUT CN1207.6

SPI_CLK CN1207.5

OSC_SEL

ICD_ENABLE_x186

FORCE_DEBUG

External Xtal with internal oscillator

OCM_20_n24

OCM_BOOT_XROM
WDT_MODE

ATE_VECTOR_MODE

Exteranl TTL oscillator

ICD_SDA on VGA_SDA, ICD_SCL on VGA_SCLI2C to JTAG Bridge is disabled

FORCE DEBUG mode

Normal

M

CO tib-02

MCO

tib-42

ffo

MO

R lanretnI

n

o MOR lanret

nI

WDT resets all digital logic in the ICWDT resets internal x186 ucontroller

Normal

Nibble mode enabled for loading ATE
vectors.

I2C address: 48H and 49H

I2C address: A6H
and A7H

HDMI EXTERNAL
HDCP KEY

Modify by Kodi
2008/2/22

R640
0R/6

U28

24LC02B/NC

A0

1

A1

2

A2

3

VSS

4

SDA

5

SCL

6

WP

7

VCC

8

R407 1K/6

R391 4.7K/6

R367 10K/6

R409 0R/6

R387 NC

R356 0R/6

SEQUOIA OCM

Peripherals

U8I
FLI32626H

SPI_CSn

Y10

SPI_DI

AA10

SPI_DO

AB10

SPI_CLK

W11

OCM_INT

Y7

PWM0

AC11

PWM1

AB11

PWM2

E16

PWM3/OCM_TIMER

D16

OCM_UDI0

E17

OCM_UDO0

D17

OCM_UDI1

A17

OCM_UDO1

A16

MSTR0_SDA

B16

MSTR0_SCL

C16

MSTR1_SDA

Y11

MSTR1_SCL

AA11

GPIO_95

E18

GPIO_94

D18

GPIO_93

B17

GPIO_92

C17

GPIO_91

AC10

GPIO_90

W9

C273

0.1uF/6

U44

NC7SB3157P6X_NL

B1

1

GND

2

B0

3

A

4

VCC

5

S

6

R357

100R/6

R507 10K/6

Q19

DTC144E

1

32

R641
0R/6

R404 1K/6

R394 4.7K/6/NC

C272 0.1uF/6

C275

0.1uF/6

R371 10K/6

R410 0R/6

C364

0.1uF/6

R508
0R/6/NC

U25

24LC64

A0

1

A1

2

A2

3

VSS

4

SDA

5

SCL

6

WP

7

VCC

8

R349 10K/6

R388 NC

TP5

R402 1K/6

U27

M24C04/NC

A0

1

A1

2

A2

3

VSS

4

SDA

5

SCL

6

WP

7

VCC

8

R3904.7K/6/NC

R363

100R/6

L47

121A40/8

R517 0R/6

R411

0R/6

Q18

DTC144E

1

32

R365 10K/6

R368 10K/6

U29

PCA9555PW(AL009555K04)

A2

3

INT

1

SCL

22

A1

2

A0

21

SDA

23

VDD

24

GND

12

P04

8

P07

11

P01

5

P03

7

P06

10

P00

4

P05

9

P02

6

P10

13

P11

14

P12

15

P13

16

P14

17

P15

18

P16

19

P17

20

R353 10K/6

R364 0R/6

R406 1K/6

R383 0R/6

R362

100R/6

R347 10K/6/NC

R597 0R/6

R379 NC

R3924.7K/6/NC

R376 10K/6

U45

NC7SB3157P6X_NL

B1

1

GND

2

B0

3

A

4

VCC

5

S

6

R510
0R/6/NC

R369 0R/6

D37

UDZ5V6B/NC

2

1

R509 10K/6

R455

0R/6/NC

R675 0R/6/NC

R439 0R/6

R352 10K/6

R385 0R/6

R400 0R/6

R378 NC

R380 10K/6

R360 0R/6

R4051K/6/NC

U24

SST25VF016

CE#

1

SO

2

WP#

3

VSS

4

SI

5

SCK

6

HOLD#

7

VCC

8

R350
0R/6

R395 4.7K/6/NC

R374 0R/6

D38
UDZ5V6B/NC

2

1

R456 0R/6/NC

R354 10K/6

SW1
SW_HCH_STSB5

1

1

2

2

3

3

4

4

L101

121A40/8

R377 NC

R351 10K/6

R389 0R/6

R518 0R/6

R401 0R/6

R366 10K/6

R396

4.7K/6/NC

R370 0R/6

R359 0R/6/NC

R372 0R/6

R676 0R/6

C276 0.1uF/6

R398 0R/6

C274 0.1uF/6

R408 1K/6

R399 NC

R393 4.7K/6

R514
0R/6

R386 10K/6

R403 1K/6/NC

R355 0R/6

R373 0R/6

R358 0R/6/NC

R361

100R/6

L100

121A40/8

R348 10K/6

18430_515_090202.eps

090202

Main Board: OCM Peripherals

EN 53QCG1.0S LA 10.

2009-Mar-20

Circuit Diagrams and PWB Layouts

5

4 3 2

1

D

C

B

A

A

LBADC_4

IR_IN

+3.3V_LBADC

LED_RED

LED_GREEN

+5VS

KEY_ADC1

LBADC_2

LBADC_3

KEY_ADC3

KEY_ADC2

PWRKEY_IN

MSTR1_SDA

MSTR1_SDA
MSTR1_SCL

MSTR1_SCL

PWRKEY_IN21

LED_RED17

LED_GREEN

17

+3.3V_LBADC 19

+5VS 2,3,7,15,17,19,20,21,22

IR_IN

21

COM_POWERON

21,22

MSTR1_SDA6,17,22

MSTR1_SCL6,17,22

+3.3V_LBADC

+5VS

+5VS

+3.3V_SMCU +3.3V_SMCU

Title

veRrebmuN tnemucoDeziS

t

eehS:etaD

of

WLZSA1 ST FLI32626

D2A

OCM Low Bandwith ADC

PROJECT NAME:

WLZR-A1

A4

18 22Thursda

y,

January 08, 2009

+

C278
22uF/6.3V

12

TP13

R430 NC

R420 0R/6

R416 NC

R431 NC

R519 10K/6/1%

R661 0R/6

L52 0R/6

TP12

C279

0.1uF/6

R432

4.7K/6

R422 0R/6/NC

R415 NC

L49
121A40/8/NC

L51

0R/6

R435

4.7K/6

R417 NC

C282 0.1uF/6

R424

0R/6

C288

0.1uF/6

+

C284

22uF/6.3V

12

L50

0R/6

C283

0.1uF/6

R425
10K/6

TP15

C281 0.1uF/6

C286

0.1uF/6

Q20

MMBT3906/NC

3 1

2

R426
10K/6/NC

+

C277
22uF/6.3V

12

C289

0.1uF/6

CN13

EIC_4500-E07N

1

2

3

4

5

6

7

C2800.1uF/6

R521 0R/6

C287

100pF/6

R412 100K/6

U35

NC7SB3157P6X_NL

B1

1

GND

2

B0

3

A

4

VCC

5

S

6

Q21
MMBT3906/NC

3 1

2

R429 NC

SEQUOIA Low

Bandwidth

ADC

U8J

FLI32626H

LBADC_IN1

W6

LBADC_IN2

AA6

LBADC_IN3

AB6

LBADC_IN4

AC6

LBADC_3.3

Y6

LBADC_GND

W7

R418 0R/6

R413 100K/6

R520 0R/6

L107
121A40/8

C285

0.1uF/6

R419
0R/6

TP14

R433

470R/6

R414 10K/6/1%

R434
470R/6

CN14

EIC_4500-E08N

1

2

3

4

5

6

7

8

18430_516_090202.eps

090202

Main Board: OCM Low Bandwidth ADC

EN 54QCG1.0S LA 10.

2009-Mar-20

Circuit Diagrams and PWB Layouts

A

y,

Main Board: Power Sequoia

5

+5VSB

D

+1.8V_DDR

+1.2V_CORE

C

Power
Sequencing
Diode

SYS_POWERON,21,22

B

L57
121A40/8

C290

100uF/16V

Low ESR

+3.3V_I/O

2

3

D40 BAV99

1

R665

4.7K/6

+

JP1

2
1

EIC_4606-02

R664 0R/6/NC

MMBT3904

C291

0.1uF/6

SYS_POWERON

2

Q38

R436
10K/6

R663
10K/6

31

C296
1uF/6

R442
20K/6/1%

C298
1500pF/6

+5VS

121A40/8

R444 0R/6/NC

R451

4.7K/6

EN 55QCG1.0S LA 10.

4 3 2

L55

U30
AOZ1010/SO8

6

EN

5

COMP

AGND

3

L66

C299

0.1uF/6

2

Q27

MMBT3904

2

LXA

VIN

LXB

FB

PGND

1

121A40/8/NC

1
2
3
4 5

R449 10K/6

R450 0R/6

31

C303
NC

SCDS 62T-3R3

3.3uH_1.9A

8

7

4

VOUT = 0.8 *
(1+RA/RB)

L64

8
7
6

RA

R437

2K/6/1%

L67

121A40/8

Q25
SI9435

C293 10uF/1206/16V

RB

R443

3.3K/6/1%

+5VSB

12

+

C294 220uF/16V

L56

121A40/8

22uH_1.5A

220uF/16V

Low ESR

S1

2
3
4
5

holec256d126p2

S4

2
3
4
5 6

holec256d126p2

S7

2
3
4
5

holec138d138n

C295

1

1

1

12

+

9
8
7
6
1

9
8
7

1

10
9
8
7
6
1

+5V_SW

+5VSB

+5VS

C292

0.1uF/6

+5V_SW 6,10,12,20,22

+5VSB 6,7,8,10,20,21

+1.2V

121A40/8

121A40/8

121A40/8

121A40/8

121A40/8

S2

2
3
4
5 6

holec256d126p2

S5

2
3
4
5 6

holec256d126p2

S8

2
3
4
5

holec138d138n

+5VS 2,3,7,15,17,18,20,21,22

L58

L60

L61

L62

L63

1

1

1

9
8
7

1

9
8
7

1

10
9
8
7
6
1

+1.2V_CORE

+1.2V_ADC

+1.2V_DPRX

+1.2V_HDMI

+1.2V_AUD

2
3
4
5

2
3
4
5 6

2
3
4
5 6

holec138d138n

+1.2V_CORE

+1.2V_ADC

+1.2V_DPRX

+1.2V_HDMI

+1.2V_AUD

S3

holec256d126p2

S6

holec256d126p2

S9

9
8

1

7
6
1

9
8

1

7

1

10
9
8

1

7

1

1

+1.2V_CORE 16

+1.2V_ADC 9

+1.2V_DPRX 5

+1.2V_HDMI 4

+1.2V_AUD 14

S10

2
3
4
5 6

holec138d138n

10
9
8

1

7

1

+3.3V_COMMON

+3.3V_I/O

+3.3V_LVDS

+3.3V_DDR

+3.3V_ADC

+3.3V_LBADC

+5VSB

A

L73

121A40/8

C304

220uF/16V

12

C306

+

0.1uF/6

C307

0.1uF/6

121A40/8

+3.3V_LPM

L96

R457 200/6/1%

U32

3

VIN

1

ADJ/GND

AIC1084/TO263
R458
330R/6/1%

VOUT

NEED
HEAT
SINK

1.5A Max

2

C305

0.1uF/6

121A40/8

121A40/8/NC

C308

47uF/6.3V

121A40/8

+

121A40/8

L74

L76

L79

L81

+3.3V_COMMON

+3.3V_LBADC

+3.3V_I/O

+3.3V_LVDS

121A40/8

121A40/8

121A40/8

121A40/8

L75

L78

L80

L82

+3.3V_DDR

+3.3V_ADC

+3.3V_HDMI

+3.3V_AUD

Near to Scaler

2009-Mar-20

+3.3V_COMMON 12,20

+3.3V_I/O 5,6,15,16,17

+3.3V_LVDS 11,12

+3.3V_DDR 10

+3.3V_ADC 9

PROJECT NAME:

WLZR-A1

Title

Power Sequoia

A4

D

WLZSA1 ST FLI32626

January 08, 2009

+3.3V_HDMI

+3.3V_AUD

+3.3V_LPM

+3.3V_LBADC

tee

hS:eta

+3.3V_HDMI 4

+3.3V_AUD 14

+3.3V_LPM 15,20

+3.3V_LBADC 18

19 22Thursda

of

18430_517_090202.eps

veRrebmuN tnemucoDeziS

D2A

090202

Circuit Diagrams and PWB Layouts

5

4 3 2

1

D

C

B

A

A

PWM

PWM

PS_ON

PBIAS

STBY

+5VS

+3.3V_LPM

+1.2V_LPM

+12V_SW

+5V_SW

+3.3V_COMMON

PWM3

BKLT_EN

PWM

BKLT_EN

+12V

PBIAS2

PBIAS 11

STBY 17,2

2

+5VS 2,3,7,15,17,18,19,21,22

+3.3V_LPM 15,19

+1.2V_LPM 15

+12V_SW 6,12,22

+5V_SW 6,10,12,22

+3.3V_COMMON 12,19

PWM3 17

ACD 17,22

PWM 12

PBIAS2 17

+3.3V_COMMON

+24VA

+24VA

+5V_SW

+5V_SW

+3.3V_COMMON

+5V_SW

+5VS

+5VS

GND

+5VS

+5V_U33

+5VS

+12V_SW

+12V

+12V_SW

+12V

+12VA

+1.2V_LPM

18mA

+5V_U33

+3.3V_LPM

31mA

+5VSB

+3.3V_SMCU

+5VS

+3.3V_SMCU

+3.3V_SMCU

Title

veR

reb

muN

tnem

uco

DeziS

teehS:etaD

of

WLZSA1 ST FLI32626

D2A

Power Sysytem

PROJECT NAME:

WLZR-A1

A4

20 22Thursda

y,

January 08, 2009

1.5A Max

+12V_SW

+5V_SW

+5VS

+24VA 8/9.5 A

2A

2A

2A

1.2~12(A)

0.25~4(A)

0.8~ 6.5(A)

60mA/2A

LCDelta

PD52

PD52

PD46

PD46

R467 NC

R690
10K/6

R465

100R/6

TP11

R486
1K/6/1%

R474 10K/6

C323

0.1uF/6

C313

0.1uF/6/NC

CN16

EIC_4606-10/NC

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

C314

0.1uF/6

+

C355

47uF/6.3V

Q26
MMBT3904/NC

31

2

Q28

MMBT3904/NC

31

2

R470
1K/6

+

C311

470uF/16V

R485 200/6/1%

C331 33nF/6

J7
EIC_4606-14

1
2
3
4
5
6
7
8
9
10
11
12
13
14

R473

1K/6

12

Q31
MMBT3904

31

2

C321

0.1uF/6

Q33
MMBT3904

31

2

L89

121A40/8

C325
NC

R476

10K/6

R460
0R/6

L103

121A40/8/NC

TP6

+

C322

470uF/16V

R464
10K/6

L94

121A40/8

L90

121A40/8/NC

R471

10K/6

R487

1K/6

R523
0R/6

R522

0R/6/NC

R478

470R/6

TP7

+

C336

47uF/6.3V

C324

0.1uF/6

TP10

C320

0.1uF/6/NC

R459 0R/6/NC

R469
1K/6

TP9

C316

0.1uF/6

L92

121A40/8

R667 330R/6/1%

L93

121A40/8/NC

C327
NC

+

C310

220uF/35V/NC

12

R484
1K/6/NC

L95

121A40/8

L83

121A40/8

L85

121A40/8

C315

0.1uF/6

R463 10K/6/NC

+

C332

220uF/16V

12

R481
10K/6/NC

C317

0.1uF/6

R489

330R/6/1%

L102
121A40/8

L88

121A40/8/NC

C328
1uF/8

L91

121A40/8/NC

+

C319

470uF/16V

CN19
EIC_4606-12

1

2

3

4

5

678

9

10

11

12

C329
1uF/8

Q30

MMBT3906

3 1

2

L86

121A40/8

C326

10uF/16V

12

R466
0R/6

R482

4.7K/6/NC

U34

AIC1084/TO263

ADJ/GND

1

VOUT

2

VIN

3

+

C330

47uF/6.3V

L104

121A40/8

CN15

EIC_4500-E12N/NC

1

2

3

4

5

6

7

8

9

10

11

12

R468

4.7K/6/NC

Q29
MMBT3904

31

2

C333

0.1uF/6

R666 200/6/1%

R375

4.7K/6

R479
10K/6

C359

0.1uF/6

R697

4.7K/6/NC

R472
0R/6/NC

R480 4.7K/6

R475

4.7K/6

+

C358

220uF/16V

12

R477
0R/6

C334

0.1uF/6

U33

APL5915KAI-TRL

GND

1

FB

2

VOUT

4

VIN

5

EN

8

VOUT

3

VCNTL

6

POK

7

E-PAD

9

U46

AP1117ELA/TO223

ADJ/GND

1

VOUT

2

VIN

3

OUT

4

R461
10K/6/NC

R488

2K/6/1%

L87

121A40/8

C356

0.1uF/6

Q32

MMBT3906

3 1

2

R483

4.7K/6

TP8

C335

0.1uF/6

R462
NC

18430_518_090202.eps

090202

Main Board: Power System

EN 56QCG1.0S LA 10.

2009-Mar-20

Main Board: SMCU

A

y,

0R/6/NC

5V_SCL

D

C339
6pF/6

C

B

P10
P11
P12
P13
P14
P15
P16
P17

A

X2

19.6608MHz

TCLK1

C340
6pF/6

1
2
3
4

CN20

4500-E04N

+5VS

+5VS

R565 NC

R564 NC

R582 NC

R581 NC

+3.3V_SMCU

R566 NC

R567 NC

R584 NC

R583 NC

Circuit Diagrams and PWB Layouts

5

R524

CEC_POWERON15

SYNC_CNT

22

+5VS

0R/6/NC

R548 0R/6
R550 0R/6
R552 0R/6
R554 0R/6
R556 0R/6
R558 0R/6
R561 0R/6
R645 0R/6/NC

R570 NC

R568 NC

R569 NC

R572 NC

R571 NC

R585 NC

R586 NC

R589 NC

R588 NC

R587 NC

SCL_SMCU
TXD1_SMCU

C338

0.1uF/6

RXD1_SMCU

R642

R575 NC

R576 NC

R574 NC

R573 NC

R592 NC

R593 NC

R591 NC

R590 NC

+5VS

D45 1N4148

R546 0R/6/NC

R545 0R/6/NC

R578 NC

R577 NC

R563 NC

R579 NC

R594 NC

R595 NC

R525 0R/6

R526 0R/6

R527 5.1K/6

R532 0R/6

R535 0R/6

12

R539 0R/6
R541 0R/6/NC

R543 1k/6

TXD1_SMCU
RXD1_SMCU

R580 0R/6

MODE

SW2

SW_HCH_STSB5

14
12

CN21

87256-1411

P33
P34
P35
P37
P42
P45
P46
P47

MODE

nRESET
P47

P46

13
11

910
78
56
34
12

EN 57QCG1.0S LA 10.

4 3 2

U36

P35
P37

P45
P17

10

1

1

3

3

SYS_POWERON

+5VS

10K/6

10K/6

SDA_SMCU

1

P3_5/SSCK/SCL/CMP1_2

2

P3_7/CNTR0/SSO/TXD1

3

RESET

4

XOUT/P4_7

5

VSS/AVSS

6

XIN/P4_6

7

VCC/AVCC

8

MODE

9

P4_5/INT0/RXD1
P1_7/CNTR00/INT10

R5F211A4SP

2

2

4

R553 0R/6/NC
R555 0R/6

R557 0R/6/NC
R559 0R/6/NC

R562 0R/6/NC

0R/6/NC

12

4

10uF/1

R549 0R/6

R551 0R/6/NC

R643 0R/6/NC

R644 0R/6/NC

R646 0R/6/NC

R701

R445

R448

P3_3/TCIN/INT3/SSI00/CMP1_0

C357

206/16V

nRESET

MPE_JTAG_CLK

MPE_JTAG_MODE
MPE_JTAG_TDO

MPE_JTAG_TDI
MPE_JTAG_RST

D46BAT54C

12

3

COM_POWERON

18,22

R703
10K/6

+3.3V_SMCU

Q15

2N7002

3

2

3

P3_4/SCS/SDA/CMP1_1

P1_0/KI0/AN8/CMP0_0
P1_1/KI1/AN9/CMP0_1

P1_2/KI2/AN10/CMP0_2

P1_3/KI3/AN11/TZOUT

P1_5/RXD0/CNTR01/INT11

DIGI_SAVING-5V

COM_POWERON

R516 10K/6

R515 10K/6

1

2

Q22
2N7002

P4_2/VREF

P1_4/TXD0

P1_6/CLK0/SSIO1

IR_IN18

+5VS

R696
10K/6/NC

R547

4.7K/6

MODE

+5VS

+5VSB

31

1

Q40
MMBT3904

SMCU3_SDA

SMCU3_SCLSCL_SMCU

P34

20
19
18
17
16
15
14
13
12
11

EIC_4606-03

R528 0R/6

P33

R530 0R/6

P10

R531 0R/6

P11

R533 0R/6

P42
P12

R536 0R/6

P13

R537 0R/6

P14

R538 0R/6

P15

R540 0R/6

P16

R542 0R/6

IR_IN

COM_POWERON

1
2
3

18

J8

+5VS

C341

0.1uF/6

PWRKEY_IN

J8 Pin1-Pin2 short
SMCU update BIOS status
J8 Pin2-Pin3 short
Normal status

R700
10K/6

DIGI_SAVING-3V317

R702

10K/6

2

Control Pin saving

DIGI_SAVING

-3V3

DIGI_SAVING-3V3

ON

H

SMCU3_SDA 17

SMCU3_SCL 17

R529

VCC
A
S

PWRKEY_IN

0R/6/NC

U37

B0
B1

GND

+3.3V_LPM

+3.3V_I/O

SDA_SMCU

IR_SMCU

Status2
Status1

PWRKEY_SMCU
DIGI_SAVING-5V
TXD0_SMCU
RXD0_SMCU
SYS_POWERON

R544 0R/6/NC

NC7SB3157P6X_NL

5
4
6

L

PROJECT NAME:

WLZR-A1

Title

A4

D

3
1
2

4500-E06N
CN22

MPE_JTAG_RST
MPE_JTAG_TDI
MPE_JTAG_TDO
MPE_JTAG_MODE
MPE_JTAG_CLK

+3.3V_SMCU

+5VS

SMCU

January 08, 2009

5V_SDA 22

Status2 17
Status1 17

TXD0_SMCU 22

RXD0_SMCU 22

SYS_POWERON 15,17,19,22

IR_LPM 15

R669 0R/6

R560 0R/6/NC

6
5
4
3
2
1

+3.3V_SMCU 2,17,18,20,22

+3.3V_LPM 15,19,20

+3.3V_I/O 5,6,15,16,17,19

+5VS 2,3,7,15,17,18,19,20,22

PWRKEY_SMCU

+5VS

MODE

TXD1_SMCU
RXD1_SMCU

MPE_JTAG_RST 6
MPE_JTAG_TDI 6
MPE_JTAG_TDO 6
MPE_JTAG_MODE 6
MPE_JTAG_CLK 6

WLZSA1 ST FLI32626

tee

hS:eta

1

PWRKEY_LPM 15

TXD1_SMCU 8
RXD1_SMCU 8

21 22Thursda

of

18430_519_090202.eps

veRrebmuN tnemucoDeziS

D2A

090202

2009-Mar-20

Circuit Diagrams and PWB Layouts

A

y,

ሽ

ᔾ

Main Board: Board to board connect

5

+5VS

5V_SDA

10K/6

10K/6

R503

R504

+3.3V_SMCU

Q34

2N7002

3

2

1

D

5V_SCL

17,20

STBY17,20

SYS_POWERON

17

MAIN_MUTE

COM_SDA

7
,17,18

MSTR1_SDA

21

5V_SDA

MSTR1_SCL

7,18

17

C

B

5V_SCL21

COM_SCL

SYNC_CNT21

7,9

7,9

7,9

9

9

7

7

RED_IN

GRN_IN

BLU_IN

HS_IN

VS_IN

PC_RB7

PC_GB

PC_BB

HSB9

VSB9

ACD

ACD

TS

YS

MAIN_MUTE

COM_SDA

5V_SDA
MSTR1_SCL
5V_SCL
COM_SCL

SYNC_CNT

3

OR

N

EWOP_S

R670 0R/6/NC
R492 0R/6/NC
R505 0R/6
R494 0R/6/NC
R506 0R/6
R671 0R/6/NC

R635 0R/6

R611 0R/6/NC

R612 0R/6/NC

R613 0R/6/NC

R614 0R/6/NC

R615 0R/6/NC

R616 0R/6

R617 0R/6

R618 0R/6

R619 0R/6

R620 0R/6

Near to

U8

COM_POWERON

A

COM_POWERON

COM_POWERON

VCC
A
S

U48

B0
B1

GND

+5VS

NC7SB3157P6X_NL

TX_IO RX_IO

C360

0.1uF/6

5
4
6

R490 10K/6

R491 10K/6

2

Q35
2N7002

1

3
1
2

EN 58QCG1.0S LA 10.

4 3 2

+12V_SW

COM_SDA

COM_SCL

YB

TSYB

OP

N

EW

_SYS

MAIN_MUTE

I/O_SDAMSTR1_SDA

I/O_SCL

CN17_P24

SW_ROUT_I/O

SW_GOUT_I/O

SW_BOUT_I/O

SW_HOUT_I/O

SW_VOUT_I/O

DSUB_RIN_I/O

DSUB_GIN_I/O

DSUB_BIN_I/O

DSUB_AHIN_I/O

DSUB_AVIN_I/O

OR

CVBS

CN17
TX25-60P-LT-H1E

30

15

29

14

28

13

27

12

26

11

25

10

24

9

23

8

22

7

21

6

20

5

19

4

18

3

17

2

16

1

(1A/pin)

+5VS

60

45

59

44

58

43

57

42

56

41

55

40

54

39

53

38

52

37

51

36

50

35

49

34

48

33

47

32

46

31

+5V_SW

PC_AUD_IN_L2

PC_AUD_IN_R2

AUD_OUT_LS_LB

AUD_OUT_LS_RB

COMP_PR

COMP_Y

COMP_PB

SVIDEO_C

SVIDEO_Y

CVBS

R493 0R/6

R495 0R/6

R624 0R/6

R623 0R/6

R629 0R/6

R630 0R/6

R598 0R/6

R602 0R/6

R609 0R/6

R601 0R/6

R610 0R/6

R608 0R/6

Near to
U8

TX_MAIN 8
TXD0_SMCU 21

+5VS

COM_POWERON

C361

0.1uF/6

NC7SB3157P6X_NL

5
4
6

VCC
A
S

U47

B0
B1

GND

3
1
2

RX_MAIN 8

RXD0_SMCU 21

+3.3V_LPM

+5VS

+5VSB

+5V_SW

+12V_SW

+3.3V_I/O

TX_IO

RX_IO

+3.3V_SMCU

AUD_IN_R2 14

AUD_IN_L2 14

BIN-7,9

A2 9

B3 9

SV3 9

B2 9

SV4 9

SV2 9

GIN-7,9

RIN-7,9

AUD_OUT_LS_L 14

AUD_OUT_LS_R 14

PROJECT NAME:

WLZR-A1

Title

Board to Board Connect

A4

D

WLZSA1 ST FLI32626

January 08, 2009

1

+3.3V_LPM 15,19,20

+5VS 2,3,7,15,17,18,19,20,21

+5VSB 6,7,8,10,19,20,21

+5V_SW 6,10,12,20

+12V_SW 6,12,20

+3.3V_I/O 5,6,15,16,17,19

+3.3V_SMCU 2,17,18,20,21

CN17

BIN-

GIN-

RIN-

R691

0R/6/NC

hS:eta

tee

R692

0R/6/NC

22 22Thursda

R693

of

18430_520_090202.eps

0R/6/NC

veRrebmuN tnemucoDeziS

D2A

090202

2009-Mar-20

Circuit Diagrams and PWB Layouts

EN 59QCG1.0S LA 10.

Extension Board: Video input

5

AV_YIN

C1 100pF/6

C6 100pF/6

L81

C269

0.1uF/6

R6

L1
0R/6

R4

75R/2010

L3
0R/6

75R/2010/NC

+5VC

DSUB_AHIN

CVBS_OUT

DSUB_AHIN3,4

DSUB_GIN

JACK1

6

8
11
10

5

D

AV_CIN

1

3

TYCO_1566504_4_5P

P1

P2
P2

J1

P1

CBNC2P-YKC31-0184ON6_0

AV_CIN

C C

D7

EZJZ0V800AA/6/NC

+5VS

B B

CYNC_ENABLE9

G1

G1

G2

D6

+5VS

EZJZ0V800AA/6/NC

C268

220nF/6

R552
10K/6/NC

R553

4.7K/6

C9

100pF/6

C18

100pF/6

9
7

2

4

BNC_CVBS_IN

C14

R16

100pF/6

75R/2010

L7 0R/ 6

R22

75R/2010

Q68

3415/SOT23

S

G

R550

4.7K/6

R551
1K/6

Q69

2

MMBT3904

1 3

RCA_CVBS_IN

D1

EZJZ0V800AA/6/NC

D2

EZJZ0V800AA/6/NC

D5

EZJZ0V800AA/6/NC

L6 0R/ 6

+5VS

121A4/8/NC

+5VC

D

+

C267

10uF/50V

DSUB_GIN4

4

NC 4/29

SCIN 4

SYIN 4

U39

NC7SB3157P6X_NL/NC

3

B0

1

B1

2

GND

+5V_SW

121A4/8

R7 10R/6

R34 0R/6

DSUB_AHIN

+5VC

5

VCC

4

A

6

S

L2

C11

1 2

47uF/25V

C19

1 2

47uF/25V

SOG_SW

C274

0.1uF/6/NC

C3

0.1uF/6

+

+

+5VC

C7

0.1uF/6

+5VC

+5VC

121A4/8

12

+

R11
10K/6

R15

4.7K/6

R20
10K/6

R27

4.7K/6

L8

C21

1

47uF/25V

C4
22uF/50V

R13

100R/6

R23

100R/6

+

2

SOG_SW 4

R2 4.7K/6

6

VCC

5

GND

4

IN

MM1671

L4
0R/6

Q1

2

MMBT3904

1 3

R17 680R/6

R18

1.8K/6

Q2

2

MMBT3904

1 3

R28 680R/6

R29

1.8K/6

R30
10K/6

R31

100R/6

R32
15K/6

U1

1

PS

2

OUT

3

SAG

R9 75R/2010

C10

0.1uF/6

C17

0.1uF/6

Q3

2

MMBT3904

1 3

R33 680R/6

R36

1.8K/6

3

R3 NC

C2
100uF/25V

1 2

+

C5

47uF/25V

1 2

+

C20

0.1uF/6

R35

2.2K/6/NC

CSYNC_IN

CVBSIN 4

C16

0.1uF/6

1B161A

5

1B2

4

1B3

3

1B4

10

2B1

11

2B2

12

2B3

13

2B4

Control
Pins

CSYNC_SEL

VIDEO_SEL

C12

0.47uF/6

+5VC

C15
470pF/6

U3

16

PI5V331QE

7
9

VCC

2A

14

S0

2

S1

1

1OE

15

2OE

GND

8

CVBS CSYNC

L

2 1

R24 0R/6
R26 0R/6

S-VIDEO

HL

R8

1.1K/6

D4

1SS355

VIDEO_SEL 9
CSYNC_SEL 9

HL

LH

2

D3

UDZ5V6B

2 1

+5VC

U2

1

CVBS_SYNC_OUT

2

CVBS_IN

3

V_SYNC_OUT

4

GND

NS_LM1881_SOP_8P

BNC_Y

H

+5V_SW

L5

121A4/8

R10 560K/6

OD/EVN

BRST/BK

SYNC_CNT 4

8

VCC

7
6

RSET

5

+5V_SW 3,4,9

C8

0.1uF/6

R14
560K/6

C13

0.1uF/6

1

D

+5VC

Q61

MMBT3904

1 3

R536 680R/6

R537

1.8K/6

C252

0.1uF/6

TechView International Technology Inc.

No.361,5F.,Fu- Sing 1 Rd.,Gueishan Hsiang, Taoyuan, Taiwan

Title :

01.VIDEO INPUT
SCH File Name :
P

Approval:

3

2

D

Standard Circuit Design

Check:

1

Tel :[phone]
Fax:[phone]

Document Number:

B2A

Rev:

CP: emaN eliF BC

Draw:

111Friday, January 0 9, 2009

teehS:eta

<Doc>

Size :

Custom

>veR<>emaN BCP<

:veR B

of

R533

C253

BNC_Y2,4

A A

5

4

1

47uF/25V

10K/6

+

R534

2

R535

4.7K/6

2

100R/6

18430_521_090204.eps

090204

2009-Mar-20

Circuit Diagrams and PWB Layouts

ಛᇆᒵ ᒵᐈ

ಛᇆᒵႊץچ

Extension Board: Analog input

5

EN 60QCG1.0S LA 10.

4

3

2

1

D

Near to CN8

L14
0R/6

L15
0R/6

L16
0R/6

75R/2010

R49

75R/2010

R50

R51

BNC_Y

BNC_PB

BNC_PR

C36 NC

C37 NC

C38 NC

BNC_Y 1,4

BNC_PB 4

BNC_PR 4

P3

P1

CN2

P3

P2

P1

G3

G1

G3

G2P2

G1

+5VS

2

3

D17

C39 NC

EZJZ0V800AA/6/NC

1

D15 BAV99

C34 NC

3

+5VS

2

1

D16 BAV99

75R/2010

C35 NC

MINI_YKC31_0185V_3P

C C

Y/PB/PR 3ය : 16mil
Y/PB/PR

D

B B

TechView International Technology Inc.

A A

No.361,5F.,Fu-Sing 1 Rd.,Gueishan Hsiang, Taoyuan, Taiwan

Title :

02.ANALOG INPUT

SCH File Name :

5

4

3

D

2

Standard Circuit Design
<PCB Name> <Rev>

Check:Approval:

Document Number:

teehS:eta

Tel :[phone]
Fax:[phone]

Rev:

Draw:

211Friday, January 09, 2009

1

<Doc>

B2A

:veR BCP: emaN eliF BCP

of

18430_522_090204.eps

Size :

A4

090204

2009-Mar-20

Circuit Diagrams and PWB Layouts

ය

ಛᇆ

ᒵ

ᐈ

ಛ

ᇆᒵ

ႊ

ץ

چ

၏

EN 61QCG1.0S LA 10.

Extension Board: Analog output

5

Near to CN9

R/G/B 3
½u : 16mil

D D

CN3

1
9

17

16

C

TEKCON-MINI-DB15

B B

2
10
3
11
4
12
5
13
6
14
7
15
8

net name changed / 0320

D21

R/G/B/H/V
½u : 7mil

+5V_SW

2

3

1

D18

BAV99

12

D19

EZJZ0V800AA/6/NC

+5V_SW

2

3

D20

1

BAV99

UDZ5V6B

D22

UDZ5V6B

C13247pF/6

2 1

R254

75R/2010

R255
220K/6

C123 NC

R259

75R/2010

R260
220K/6

C126 NC

R262

75R/2010

R263

220K/6

C129 NC

R266
100R/6

R267 100R/6

C13347pF/6

2 1

C121

470uF/16V

2

1

C125

470uF/16V

12

C128
470uF/16V

2

1

U21

74LVC1G126GW

+3.3V_out

53

4

U15

TSH340_SOT23_5P

4

NC

5

VCC

REDOUT

U17

TSH340_SOT23_5P

4

NC

5

VCC

GREENOUT

U19

4

NC

5

VCC

TSH340_SOT23_5P

BLUEOUT

24

+3.3V_out

1

R557

0R/6

74LVC1G126GW

53

U22

24

1

GND

OUT

GND

OUT

GND

OUT

3

IN

2

1

3

IN

2

1

3

IN

2

1

R268
100R/6

R269
100R/6

4

-VSS

U16

NC4

TSH340IDT/NC

5

4

-VSS

U18

TSH340IDT/NC

NC4

5

4

-VSS

U20

NC4

5

TSH340IDT/NC

DSUB_AHIN 1,4
DSUB_AVIN 4

3

IN

OUT6+VCC

3

IN

OUT6+VCC

3

IN

OUT6+VCC

2

NC1

7

2

NC1

7

2

NC1

7

C122

1

NC2

NC3

8

C127

0.1uF/6

1

NC2

NC3

8

C131

0.1uF/6

1

NC2

NC3

8

0.1uF/6

3

121A4/8

121A4/8

121A4/8

L28

R251
3K/6

C120
470uF/16V

R253

1K/6

L29

R256
3K/6

R258

1K/6

L30

R261
3K/6

C130
470uF/16V

R265

1K/6

+

C124
470uF/16V

+

+

+5V_out

R252 0R/6

+5V_out

R257 0R/6

+5V_out

R264 0R/6

+5VSB

DSUB_RIN

DSUB_GIN

DSUB_BIN

+5VSB 5,6 ,9

DSUB_RIN 4

DSUB_GIN 4

DSUB_BIN 4

2

1

C

R561
200R/6F/NC

+5VS

L83
121A4/8

+

C270

A A

5

470uF/16V

C2730.1uF/6/NC

U38

3

VOUT

VIN

1

ADJ/GND

AP1117ELA/TO223/NC

R562
330R/6F/NC

OUT

2

4

C271

10uF/50V/NC

+

4

L84

121A4/8/NC

C272

0.1uF/6/NC

+3.3V_out

121A4/8

L85

+3.3V

+5VS

L86

121A4/8/NC

3

+5V_out

L87

121A4/8

+5VSB

TechView International Technology Inc.

No.361,5F.,Fu-Sing 1 Rd.,Gueishan Hsiang, Taoyuan, Taiwan

05.ANALOG OUTPUT

Title :
SCH File Name :

2

Standard Circuit Design

Check:Approval:

Document Number:

1

teehS:etaD

Tel :[phone]
Fax:[phone]

<Doc>

B2A

Size :

Rev:

:veR BCP: emaN eliF BCP

<>emaN BCP<

Draw:

of

311Friday, January 09, 2009

A3

>veR

18430_523_090204.eps

090204

2009-Mar-20

Circuit Diagrams and PWB Layouts

A

Extension Board: Board to board connect

5 4

D

ACD

STBY8

SYS_POWERON8,9,11

MUTE5,6

5,8,9,10,11

C

B

3

3

SCL_SUB

SYNC_CNT1

ANG_VOUT1

DSUB_RIN3

DSUB_GIN3

DSUB_BIN

DSUB_AHIN1,3

DSUB_AVIN

SDA_SUB5,8,9,10,11

SYNC_CNT

DSUB_RIN

DSUB_GIN

DSUB_BIN

DSUB_AHIN

DSUB_AVIN

DSUB_RIN

DSUB_GIN

DSUB_BIN

DSUB_AHIN

DSUB_AVIN

SDA_SUB

SCL_SUB

R273 0R/6

R275 0R/6

R277 0R/6

R279 0R/6

R281 0R/6/NC

R283 0R/6/NC

R284 0R/6/NC

R287 0R/6/NC

R288 0R/6/NC

R291 0R/6

R292 0R/6

R294 0R/6

R297 0R/6

R298 0R/6

ACD

STBY

SYS_POWERON

MUTE

SDA_IO

SCL_IO

CN17_P24

CN17_P9

SW_ROUT_I/O

SW_GOUT_I/O

SW_BOUT_I/O

SW_HOUT_I/O

SW_VOUT_I/O

DSUB_RIN_I/O

DSUB_GIN_I/O

DSUB_BIN_I/O

DSUB_AHIN_I/O

DSUB_AVIN_I/O

CVBS_IO

EN 62QCG1.0S LA 10.

3

62

+12V_SW +5VS

CN4

30

15

29

14

28

13

27

12

26

11

25

10

24

9

23

8

22

7

21

6

20

5

19

4

18

3

17

2

16

1

61

60

45

59

44

58

43

57

42

56

41

55

40

54

39

53

38

52

37

51

36

50

35

49

34

48

33

47

32

46

31

2

+5V_SW

R270 0R/6

R271 0R/6

PC_AUD_IN_L3

PC_AUD_IN_R3

PC_AUD_IN_L2

PC_AUD_IN_R2

PC_AUD_IN_L1

AUD_LINEOUT_L AUD_OUT1_L

AUD_LINEOUT_R

AUD_OUT_LS_LB

AUD_OUT_LS_RB

COMP_PR_IO

COMP_Y_IO

COMP_PB_IO

SVIDEO_C_IO

SVIDEO_Y_IO

CVBS_IO

R272 0R/6

R274 0R/6

R276 0R/6

R278 0R/6

R280 0R/6

R282 0R/6

R285 0R/6

R286 0R/6

R289 0R/6

R290 0R/6

R293 0R/6

R295 0R/6

R296 0R/6

R299 0R/6

R300 0R/6

R301 0R/6

TX

RX

HDMIOPT_LIN

HDMIOPT_RINPC_AUD_IN_R1

AUD_OUT1_R

BNC_PR

BNC_Y

BNC_PB

SCIN

SVIDEO_Y

CVBSIN

1

+5V_SW

+5VS

+12V_SW

TX 8

RX 8

AUD_HP_L_OUT

AUD_HP_R_OUT

AUD_IN_L2 5

AUD_IN_R2 5

HDMIOPT_LIN 5

HDMIOPT_RIN 5

AUD_OUT1_L 5

AUD_OUT1_R 5

AUD_OUT_LS_L 5

AUD_OUT_LS_R 5

BNC_PR 2

BNC_Y 1,2

BNC_PB 2

SCIN 1

SYIN 1

CVBSIN 1

+5V_SW 1,3,9

+5VS 1,2,3,8

+12V_SW 6,7,9,1

TX24-60R

-LT-H1E(DFHD60MR004)

TechView International Technology Inc.

A

2009-Mar-20

No.361,5F.,Fu-Sing 1 Rd.,Gueishan Hsiang, Taoyuan, Taiwan

06.Board to Board Connect

Title :
SCH File Name :

Friday, January 09, 2009

Standard Circuit Design
<PCB Name> <Rev>

Check:Approval:

Document Number:

Rev:

Draw:

teehS:etaD

411

Tel :[phone]
Fax:[phone]

<Doc>

Size :

B2A

:veR BCP: emaN eliF BCP

of

18430_524_090204.eps

A4

090204

Circuit Diagrams and PWB Layouts

EN 63QCG1.0S LA 10.

Extension Board: Audio input

5

678

D D

JACK2

PHONEJACK STEREO

SINGA_2PJ_246V_B

F

C

C

E

B

D

A

B B

A A

HDMIOPT_RIN4

HDMIOPT_LIN4

4500-E03N/NC

JACK3

10

11

J3

1
2
4
5
3

18_9P

1

3

2

4

6

5

7

9

8

HDMIOPT_RIN

1
2
3

Near to JACK2

C139

C140

100pF/6

100pF/6

Near to JACK3

C150

C151

100pF/6

C169

C170

100pF/6

MONIA_R

MONIA_L

12

100pF/6

100pF/6

C177

C176

MUTE

C187
1uF/6/NC

HDMI_RIN
HDMI_LIN

C188
1uF/6/NC

5

12

D23

12

100pF/6

12

100pF/6

D29

EZJZ0V800AA/6/NC

L31 0R/ 6

L35 0R/ 6

12

D24

EZJZ0V800AA/6/NC

EZJZ0V800AA/6/NC

12

D25

D26

EZJZ0V800AA/6/NC

12

D27

D28

EZJZ0V800AA/6/NC

L44
0R/6

L45

0R/6

12

D30

A9VOUT

EZJZ0V800AA/6/NC

C184

0.1uF/6

4

L36
0R/6

L37
0R/6

EZJZ0V800AA/6/NC

L38
0R/6

L39
0R/6

EZJZ0V800AA/6/NC

R322 0R/6

R324 0R/6

R341

3.3K/6

R343 NC

Q45

DTC144E/NC

1

AUD_IN_L2

R332

100K/6

4

R303
1K/6

R304

1K/6

R308
1K/6

R309

1K/6

R312
1K/6

R314

1K/6

R323 1K/6

R325 1K/6

32

4

R305

R306

100K/6

100K/6

R310

R311

100K/6

100K/6

R320

R321

100K/6

100K/6

R333

100K/6

PC_LIN
AV2_LIN

HDMI_LIN
AV1_LIN

R356 47K/6/NC

R357 47K/6/NC
R358 47K/6/NC
R359 47K/6/NC

C134 2.2uF/6

C135 2.2uF/6

C142 2.2uF/6

C143 2.2uF/6

C166 2.2uF/6

C167 2.2uF/6

32

1

Q42
DTC144E/NC

PC_LIN

PC_RIN

AV1_RIN

AV1_LIN

AV2_RIN

AV2_LIN

32

1

Q43

DTC144E/NC

1

2

D32

1N4148/NC

R348 47K/6/NC
R350 47K/6/NC
R352 47K/6/NC
R354 47K/6/NC

U26
CD4052/NC

1

B0

2

B2

3

BN

4

B3

5

B1

6

INH

7

VEE
GND8S1

R360 47K/6/NC
R361 47K/6/NC
R362 47K/6/NC
R363 47K/6/NC

+12VSB

121A4/8

AUD_OUT_LS_R

MONIAR

OUTa

AUD_OUT_LS_R

OUTa

OUTb

AUD_OUT_LS_L

C172 1uF/6

C173 1uF/6

C178

1N4148/NC

16

VCC

15

A2

14

A1

13

AN

12

A0

11

A3

10

S0

9

L32

470uF/16V

C144 1uF/6
C146 NC

C154 NC

SDA_SUB
SCL_SUB

+

100uF/25V

D33

+5VSB

C186

0.1uF/6

3

+

C136

C158 1uF/6

12

C141

0.1uF/6

R555
0R/6

R313 100R/6
R315 100R/6

L40 0R/ 6/NC
L41 0R/ 6

L42 0R/ 6
L43 0R/ 6/NC

Q44
MMBT3906

2

3 1

R338

47K/6

R349 47K/6/NC
R351 47K/6/NC
R353 47K/6/NC
R355 47K/6/NC

AV2_RIN

AV1_RIN

PC_RIN

HDMI_RINHDMIOPT_LIN

3

3

1

AP1117ELA/TO223

R307
750R/6F

PC_RIN
AV1_RIN
AV2_RIN

C147 2200pF/6/NC

C152 22 00pF/6
C155 0.1uF/6

C160 1uF/6
C162 1uF/6

C250 2 2uF/1206

C251 22uF/1206

A9VOUT

2

3

1

D31

R339

BAV99

27K/6

+

C182

47uF/25V

AUD_IN_R2 4

R302
120R/6F

U23

VIN

ADJ/GND

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15

AUD_SEL1 9
AUD_SEL2 9

2

VOUT

4

OUT

U24

IN1a
IN2a
IN3a
IN4a
MONa
NC1
TONE-Ha
TONE-La
LINEa
OUTa
CVa
CVb
SDA
SCL
GND

JRC_NJW1141M_SDMP_30P

AUDIO_R

AUDIO_L

MONb

TONE-Hb

TONE-Lb

LINEb

OUTb

C181

470pF/6

A9VOUT

C185

470pF/6

C137

IN1b
IN2b
IN3b
IN4b

NC2

AGC
CTH

CTL
Vref

V+

A9VOUT

1 3

1 3

L33

121A4/8

+

C138

0.1uF/6

10uF/50V

30

AV1_LIN

29

AV2_LIN

28
27
26

C148 2200pF/6/NC

25

C153 2200pF/6

24

C156 0.1uF/6

23
22
21

C161 0.33uF/6

20

C163 1uF/6

19

C164 1uF/6

18

C165 1uF/6

17
16

C168

100uF/25V

Q41
MMBT3904/NC

AMP_ROUT

2

R334

0R/6

R335
NC

Q46

MMBT3904/NC

AMP_LOUT

2

R346

0R/6

R347
NC

2

A9V

121A4/8

PC_LIN

R556
0R/6

A9V

+

C171

0.1uF/6

R326
0R/6/NC

C179 33pF/6

R336 15K/6

R342 47K/6

R345
0R/6/NC

2

A9VOUT

L34

AUD_OUT_LS_L

C145 1uF/6

C149 NC

C157 NC

C159 1uF/6

AUD_OUT1_R

R318

0R/6/NC

LINE_R

1

MONIAL

OUTb

AUD_OUT1_L

R319 0R/6/N C

R327

47K/6

OUTA
INA1
INA2
VSS

U25

TL062/SOIC8

MONIAL

R317 0R /6

VCC

OUTB

INB1
INB2

MONIAR

R316 0R /6

R330 27K/6

1
2
3
4

C174
1uF/6

8
7
6
5

LINE_L

+5VSB

+12VSB

AUDIO_R

AUDIO_L

AUD_OUT_LS_L

AUD_OUT_LS_R

AUD_OUT1_L

AUD_OUT1_R

MUTE

R328
100K/6

SDA_SUB

SCL_SUB

C175

0.1uF/6

R344

+5VSB 3,6,9

+12VSB 9, 10

AUDIO_R 6

AUDIO_L 6

AUD_OUT_LS_L 4

AUD_OUT_LS_R 4

AUD_OUT1_L 4

AUD_OUT1_R 4

MUTE 4,6

SDA_SUB 4,8,9,10,11

SCL_SUB 4,8,9,10,11

A9V

R329 100K/6

R331 47K/6

R337 27K/6

R340 47K/6

15K/6

C183 33pF/6

TechView International Technology Inc.

No.361,5F.,Fu-Sing 1 Rd.,Gueishan Hsiang, Taoyuan, Taiwan

07.AUDIO INPUT

Title :
SCH File Name :

Standard Circuit Design

Check:Approval:

Document Number:

teehS:etaD

1

C180
1uF/6

Tel :[phone]
Fax:[phone]

<Doc>

Size :

B2A

Rev:

:veR BCP: emaN eliF BCP

<>emaN BCP<

Draw:

of

511Friday, January 09, 2009

18430_525_090204.eps

A3

>veR

090204

C

2009-Mar-20

Circuit Diagrams and PWB Layouts

5 4

3

2

1

D

C

B

A

A

SPKRO-

SPKRO+

AMP_MUTE

SPKLO+

SPKLO-

MUTE

AMP_SLEEP

Audio_SLEEP

AUDIO_R

AUDIO_L

+12V_SW

+5V_SW

PROTN

AUDIO_L

5

AUDIO_R

5

AUD_GAIN1

9

AUD_GAIN09
AUD_NCDRC1

9

AUD_NCDRC0

9

MUTE

4,5

+12V_SW 4,7,9,11

SPKLO+ 7

SPKLO- 7

SPKRO+ 7

SPKRO- 7

Audio_SLEEP 9

+5V_SW 1,3,4,9

Limit

9

AGND

AGND

AGND

+3.3AVDD_AMP

+3.3AVDD_AMP

VCC_AMP

VCC_AMP

A9VOUT

+3.3V_ADU

VCC_AMP

+3.3V_ADU

+12V_SW

+3.3V_ADU

VCC_AMP

+5VSB

+3.3V

AGND

AGND

Title :

Size :

Document Number:

Rev:

teehS:etaD

of

SCH File Name :

:veR BCP: emaN eliF BCP

Check:Approval:

Draw:

No.361,5F.,Fu-Sing 1 Rd.,Gueishan Hsiang, Taoyuan, Taiwan

TechView International Technology Inc.

Tel :[phone]
Fax:[phone]

B2A

08.Audio AMP
A4

611Friday, January 09, 2009

<Doc>
Standard Circuit Design
<PCB Name> <Rev>

1uF < C396 < 4.7uF

LC Filter for 8 ohm

L

+ (34)/46 dB

H

H

H

+ (16)/28 dB

+ (28)/40 dB

Gain0HGain1

+ (22)/34 dB

L

Total Gain

LL

H

DRC2

DRC1

Non-clip

(Normal)

Mode

H

L

H

H

L

L

L

DRC1

DRC0

Q47

DTC144E

1

32

R388
120K/6/NC

+

C206
100uF/25V

R554 0R/6

Q48

DTC144E

1

32

R393
47K/6

L52

121A4/8/NC

C195 1uF/6

R390 82K/6/NC

L47

22uH

R368 47K/6

R384 0R/6

R386 200K/6

C191

0.22uF/8

C192 0.1uF/8

+

C212

470uF/16V

C198

220pF/6/NC

L82 121A4/8

C210

0.1uF/6

C189 0.1uF/8

R372 10K/6

U27
YDA148

PVDDREG

1

AVDD

2

INLP

3

INLM

4

VREF

5

INRM

6

INRP

7

AVSS

8

PLIMIT

9

PVDDPR

10

OUTPR1

12

PVSSR

13

OUTMR2

14

OUTMR1

15

PVDDMR

16

SLEEPN

17

PROTN

18

CKOUT

20

MUTEN

19

CKIN

21

NCDRC0

22

NCDRC1

23

GAIN0

24

GAIN1

25

PVDDML

26

OUTML1

27

OUTML2

28

PVSSL

29

OUTPL1

30

OUTPL2

31

PVDDPL

32

OUTPR2

11

HEAT PAD

33

CASE

35

CASE34CASE

36

CASE1

37

TP1

L48 22uH

C209
1uF/6

R380 75R/6/NC

C204
1uF/6

C199 1uF/6

R383 NC

R385 82K/6

C207
1uF/6/NC

R382 10K/6

R558

10k/6/NC

L54
121A4/8

L49

22uH

C211

0.1uF/6/NC

+

C203

100uF/25V

R389 0R/6

R366 0R/6

L46

22uH

R387 10K/6

L55

121A4/8

R397
330R/6F

R374 0R/6/NC

R364 0R/6

R394
200R/6F

Q70
MMBT3904

31

2

C214

0.1uF/6

C201
1uF/6

C208

0.1uF/6

C197

0.22uF/8

R376 0R/6/NC

R378 75R/6

R370 10K/6/NC

R392 NC

C200 0.1uF/8

R379 75R/6/NC

R373 10K/6/NC

C194 1uF/6

C215 0.1uF/6

R391 NCR559

4.7K/6

R381 75R/6

R369 0R/6

R365 47K/6

R375 0R/6/NC

C205
1uF/6

R377 0R/6/NC

U28

AP1117ELA/TO223

ADJ/GND

1

VOUT

2

VIN

3

OUT

4

C190 1uF/6

C216

0.1uF/6

R396 NC

L50
121A4/8

R395 3.3K/6

R371 10K/6

C196 0.1uF/8

C202
1uF/6

L51
121A4/8

R367 0R/6

C193

220pF/6/NC

+

C213

10uF/50V

18430_526_090204.eps

090204

Extension Board: Audio amplifier

EN 64QCG1.0S LA 10.

2009-Mar-20

Circuit Diagrams and PWB Layouts

A

Extension Board: Speaker switch

5 4

D

EN 65QCG1.0S LA 10.

3

2

1

+12V_SW

R404
1K/6

C

SPK_SW9

Q49

MMBT3904

31

2

AGND

GND_SIGNAL change to AGND 3/26

L56

121A4/8

L57
NC

R400 NC
R402 0R/6

16

1

3

2

4

CN5

A

ABC

C

B

D

D

5

G

6

G

TEKCON_5110-855-310-52_4P

Cancel AGND 0325

DIP Package : 5110_4pin

SPKLO-

SPKRO+ 6

SPKRO+ EXTR+
SPKLO+

R401 0R/1206/NC

SPKLO+

13

1

8

9

11

R403 0R/1206/NC

SPKRO+

4

LS1
RELAY DPDT

6

INTR+

INTL+

EXTR+

EXTL+

R398 0R/1206/NC
R399 0R/1206/NC

INTR+

INTL+

SPKRO-

4
3
2
1

CN6

EIC_4606-04

SPKLO- 6SPKLO+ 6
SPKRO- 6

SPKRO-

EXTL+

SPKLO-

C217 470pF/6

C218 470pF/6

C219 470pF/6

C220 470pF/6

AGND

GND_SIGNAL change to AGND 3/26

S1

2

B

3
4
5 6

MTH315D138

10
9
8

1

7

1

S2

2
3

1

4
5 6

MTH315D138

10
9
8
7

1

S3

2
3
4
5

MTH315D138

10
9
8

1

7
6
1

S4

2
3

1

4
5 6

MTH315D138

10
9
8
7

1

+12V_SW

+12V_SW 4,6,9,11

TechView International Technology Inc.

A

2009-Mar-20

No.361,5F.,Fu-Sing 1 Rd.,Gueishan Hsiang, Taoyuan, Taiwan

Title :

09.SPEAKER SW

SCH File Name :

Standard Circuit Design
<PCB Name> <Rev>

Check:Approval:

Document Number:

Rev:

Draw:

teehS:etaD

711Friday, January 09, 2009

Tel :[phone]
Fax:[phone]

<Doc>

Size :

B2A

:veR BCP: emaN eliF BCP

of

18430_527_090204.eps

A4

090204

Extension Board: RS232

5

5

4

4

3

3

2

2

1

1

D

D

C C

B B

A A

RX2

TUO_DX

RTUO_DXR

TX2
RX1

TXD_OUT

TXD_IN

RXD_IN

TX2

TX1

RX1

RX2

TX1

+5VS

RXD_OUTRXD_OUT

TXD_OUT

RXD_INCAT

TXD_INCAT

TXD_OUT

TXD_IN

RXD_IN

TXD_INCAT

RXD_INCAT

RXD_INCAT1
TXD_INCAT1

TXD_INCAT1

RXD_INCAT1

+5VS 1,2,3,4,9,10,11

TX 4

RX 4

RS232_S1 9
RS232_S0 9

SDA_SUB 4,5,9,10,11

SCL_SUB 4,5,9,10,11

SYS_POWERON 4,9,11

STBY 4

MCUVCC

MCUVCC

MCUVCC +5VS

+5VS

Title :

Size :

Document Number:

Rev:

teehS:eta

D

of

SCH File Name :

:veR BCP: emaN eliF BCP

Check:Approval:

Draw:

No.361,5F.,Fu-Sing 1 Rd.,Gueishan Hsiang, Taoyuan, Taiwan

TechView International Technology Inc.

Tel :[phone]
Fax:[phone]

B2A

10.RS232
A4

811Friday, January 09, 2009

<Doc>
Standard Circuit Design
<PCB Name> <Rev>

Near to J2

L

H

TXD

L

RXD

H

Enable

H

H

0

IN-terminal

S0

L

S1

Control
Pins

MODE

L

1

2

NA

OUT-terminal

RXD TXD

Disable

Disable

Enable Enable

Enable Enable Enable

Enable

Enable

Enable

Enable

X

X

XX

+

C226

10uF/50V

L61 0R/6

J5

4500-E12N

1
2
3
4
5
6
7
8
9
10
11
12

R445 22K/6

C223 0.47uF/6

R412 NC

R420 100R/6

R423 100R/6

R417 100R/6

R434 0R/6

R436 100R/6

R415 0R/6

R411

NC

R405 33R/6

C222 0.1uF/6

R407 33R/6

R425 22K/6

R428 0R/6

R409 100R/6

R419 100R/6

U31

PI5C3253

1OE

1

S1

2

1B4

3

1B3

4

1B2

5

1B1

6

1A

7

GND

8

2A

9

S0

14

2OE

15

VCC

16

2B1

10

2B2

11

2B3

12

2B4

13

C225

0.1uF/6

12

R432 100R/6

R438 22K/6

+

C229

10uF/50V

R408 33R/6

R430 100R/6

1

2

R567 0R/6/NC

L62

121A4/8

L58 0R/6

D36

EZJZ0V800AA/6/NC

12

R437 100R/6

C224 0.47uF/6

R431 100R/6

1

2

+

C227

10uF/50V

L59 0R/6

L63

121A4/8

R414 100R/6

R568 0R/6/NC

R410 100R/6

D35

EZJZ0V800AA/6/NC

12

C221

0.47uF/6

C230

0.1uF/6

12

R416 100R/6

R426 100R/6

U29

SP3243

R2OUTB

20

INVALID

21

GND

25

VCC

26

C1+

28

C1-

24

C2+

1

C2-

2

V+

27

V-

3

FORCEON

23

FORCEOFF

22

R1IN

4

R2IN

5

R3IN

6

R4IN

7

R5IN

8

T1IN

14

T2IN

13

T3IN

12

R1OUT

19

R2OUT

18

R3OUT

17

R4OUT

16

R5OUT

15

T1OUT

9

T2OUT

10

T3OUT

11

R413 100R/6

R429 0R/6

R440 100R/6

D37

EZJZ0V800AA/6/NC

12

L64

121A4/8

R427 NC

R439 100R/6

D34

EZJZ0V800AA/6/NC

12

C228

0.1uF/6

R442 100R/6R441 0R/6

R418 100R/6

R433 100R/6/NC

U30

PI5C3253

1OE

1

S1

2

1B4

3

1B3

4

1B2

5

1B1

6

1A

7

GND

8

2A

9

S0

14

2OE

15

VCC

16

2B1

10

2B2

11

2B3

12

2B4

13

L60 0R/6

R444 100R/6

R566

33R/6/NC

R424 0R/6

R422 0R/6

R443 0R/6

R421 100R/6

R406 33R/6

R435 100R/6

J4

TEKCON_1297_000_410_52_18P

13
17
12
16
11
15
10 1

6

2

7

3

8

4

5
9

14
18

G1G3

G2G4

R565
33R/6/NC

18430_528_090204.eps

090204

Circuit Diagrams and PWB Layouts

EN 66QCG1.0S LA 10.

2009-Mar-20

Circuit Diagrams and PWB Layouts

A

Extension Board: GP IO and power

5 4

EN 67QCG1.0S LA 10.

3

2

1

D

C

4,5,8,10,11

B

A

SYS_POWERON4,8,11

SDA_SUB4,5,8,10,11

SCL_SUB

SDA_SUB

SCL_SUB

+5VS

Disable

R572
10k/6/NC

+5V_SW +5VSB

R560

4.7K/6/NC

MMBT3904/NC

+5VS

121A4/8

R462 2.7K/6

R467 0R/6
R469 0R/6

R473 NC

R475 NC
R477 10K/6
R479 10K/6
R481 NC
R483 NC
R485 0R/6

2

Q71

L71

OCM_INT0_55

PCA9555P

L65

121A4/8

R446

10K/6/NC

31

W(AL009555K04)

C235

0.1uF/6

24

23
22

1

21

2
3

U32

C231

0.1uF/6

R449 4.7K/6

VDD

SDA
SCL

INT

A0
A1
A2

2

Q53

MMBT3904

P17
P16
P15
P14
P13
P12
P11
P10

P07
P06
P05
P04
P03
P02
P01
P00

GND

12

L66

121A4/8/NC

1
2
3
4 5

R448 10K/6

R450 0R/6

D38

1

31

NC

PCA55_P17

20

PCA55_P16

19

PCA55_P15

18

PCA55_P14

17

PCA55_P13

16

PCA55_P12

15

PCA55_P11

14

PCA55_P10

13

PCA55_P07

11

PCA55_P06

10

PCA55_P05

9

PCA55_P04

8

PCA55_P03

7

PCA55_P02

6

PCA55_P01

5

PCA55_P00

4

8
7
6

2

L67
121A4/8

Q50
SI9435

C233
NC

I2C address: 4(A2A1A0)H

PCA55_P11

R571

10k/6/NC

FB1
FB2

CN13

EIC_4500-05/NC

1
2
3
4
5

PCA55_P07
PCA55_P06
PCA55_P05

PCA55_P04
PCA55_P03
PCA55_P02

PCA55_P01
PCA55_P00

PCA55_P17
PCA55_P16
PCA55_P15
PCA55_P14
PCA55_P13

PCA55_P14
PCA55_P13

PCA55_P12

R454 0R/6
R455 0R/6
R456 0R/6

R460 0R/6R464 2.7K/6
R461 0R/6
R463 0R/6

R470 0R/6
R471 0R/6

R573 0R/6/NC

R480 0R/6/NC
R482 0R/6/NC
R484 0R/6
R486 0R/6
R487 0R/6

R488 0R/6/NC
R489 0R/6/NC
R569 0R/6/NC

R492 0R/6
R493 0R/6/NC
R494 0R/6/NC

R570
10k/6/NC

+12V_SW

121A4/8

L68

C232

0.1uF/6

R453

4.7K/6

121A4/8/NC

R451 10K/6

31

2

Power_ON

Audio_SW

CSYNC_SEL

CYNC_ENABLE

Q54
MMBT3904

SPK_SW

VIDEO_SEL

RS232_S1
RS232_S0

AUD_GAIN0
AUD_GAIN1

Audio_SLEEP
AUD_NC
AUD_NCDRC0

AUD_SEL2
AUD_SEL1

Disable

FB1
FB2PCA55_P10

L69

1
2
3
4

R452 0R/6

D39

1 2

NC

DRC1

+12VSB

L70

121A4/8

8
7
6

Q51

5

SI9435

C234
NC

Limit 6
Audio_SW 11

SPK_SW 7
VIDEO_SEL 1
CSYNC_SEL 1

RS232_S1 8
RS232_S0 8

SOG_SW 6

AUD_GAIN0 6
AUD_GAIN1 6
Audio_SLEEP 6
AUD_NCDRC1 6
AUD_NCDRC0 6

AUD_SEL2 5
AUD_SEL1 5

CYNC_ENABLE 1

C263

10uF/50V

+

C254

0.1uF/6

+12V_SW

+12VSB

+5VS

+5V_SW

+5VSB

+12V_SW 4,6,7,11

+12VSB 5,10

+5VS 1,2,3,4,8,10,11

+5V_SW 1,3,4

+5VSB 3,5,6

TechView International Technology Inc.

No.361,5F.,Fu-Sing 1 Rd.,Gueishan Hsiang, Taoyuan, Taiwan

Title :

11.GPIO & POWER

SCH File Name :

Standard Circuit Design
<PCB Name> <Rev>

Check:Approval:

Document Number:

teehS:etaD

Tel :[phone]
Fax:[phone]

<Doc>

B2A

Rev:

Draw:

911Friday, January 09, 2009

:veR BCP: emaN eliF BCP

of

18430_529_090204.eps

Size :

A4

090204

2009-Mar-20

Circuit Diagrams and PWB Layouts

5

5

4

4

3

3

2

2

1

1

D

D

C C

B B

A A

FAN_CTL1

FAN_DET1

+5VS

+12V_SW

+3.3V_FAN

FAN_DET1

FAN_DET2

FAN_DET2

FAN_CTL2

SCL_FAN

SDA_FAN

FAN_CTL2

+3.3V_FAN

+12V_SW 4,6,7,9,11

+3.3V_FAN

+5VS 1,2,3,4,8,9,11

SDA_SUB 4,5,8,

9

SCL_SUB 4,5,8,9

SDA_FAN

11

SCL_FAN11

FANVCC+12VSB

FANVCC

RTCVCC

+5VS

RTCVCC

RTCVCC

FANVCC

FANVCC

FANVCC

+3.3V

Title :

Size :

Document Number:

Rev:

teehS:eta

D

of

SCH File Name :

:veR BCP: emaN eliF BCP

Check:Approval:

Draw:

No.361,5F.,Fu-Sing 1 Rd.,Gueishan Hsiang, Taoyuan, Taiwan

TechView International Technology Inc.

Tel :[phone]
Fax:[phone]

B2A

12.FAN CONTROL; RTC
A4

10 11Friday, January 09, 2009

<Doc>
Standard Circuit Design
<PCB Name> <Rev>

1

2

1

2

C2410.1uF/6

Q72

MMBT3904/NC

31

2

R563
0R/6

R519

4.7K/6

L73

121A4/8

+

C247
47uF/25V

12

R515

10K/6

R516 33R/6

Q58

DTC144E

1

32

R506
33K/6

R530 100R/6

U34

PHP_PFC8563T_TSSOP_8P

OSCI

1

OSCO

2

/INT

3

VSS

4

SDA

5

SCL

6

CLKOUT

7

VDD

8

R525 NC

C246

0.1uF/6

R512
0R/6

CN8

EIC_4500-E03N

1

2

3

R510
1K/6

+

C248

47uF/25V

12

C249

0.1uF/6

R523

10K/6

R504

560R/6

R517 33R/6

R564

10K/6/NC

Q57

APM3195P

2 3

1

CN9

4500-E04N

1

2

3

4

Y1

32.768kHz

R526 4.7K/6

R514

10K/6

D41

1N4148

1 2

+

C243
1F_5.5V

12

R531

4.7K/6

C237

0.1uF/6

L74

121A4/8

R513
27K/6

Q56

MMBT3904

2

1 3

C244
18pF/6

+

C240

47uF/25V

12

Q59

APM3195P

2 3

1

+

C245
47uF/25V

12

C2420.1uF/6

R509 4.7K/6

R511

4.7K/6

R532

4.7K/6

R528 4.7K/6

Q60

DTC144E

1

32

R520

0R/6

R527 NC

Q55

MMBT3906

31

2

CN7

EIC_4500-E03N

1

2

3

U35 F75375S

FANIN2/GPIO0

2

FANIN1

1

PWMOUT1/DACOUT1/ADDR_TRAP

3

PWMOUT2/DACOUT2/GPIO1

4

FAN_FAULT#/SMI#/GPIO2

5

VOLT_FAULT#/OVT#/GPIO3/EXT. CLOCK

6

SCLK

7

SDATA

8

VCC

16

VT2

14

VT1

15

VREF

13

VIN1

12

VIN2

11

VIN3

10

GND

9

R524

10K/6

R522

10K/6

R508 4.7K/6

R529 100R/6

R505

12K/6

C238

0.1uF/6

R507

12K/6

L75 121A4/8

D40

1N4148

1 2

R518 4.7K/6

+

C239

47uF/25V

12

R521
27K/6

18430_530_090204.eps

090204

Extension Board: Fan control; RTC

EN 68QCG1.0S LA 10.

2009-Mar-20

Circuit Diagrams and PWB Layouts

EN 69QCG1.0S LA 10.

Extension Board: PC power

2

4

2
3
4 5

R538 10K/6

R539 0R/6

31

Q63
MMBT3904

81
7
6

D42

1 2

NC

121A4/8

Q62
SI9435

C257
NC

L77

VCC_AMP+12V_SW

C256

0.1uF/6

+

C264

10uF/50V

5

L76

121A4/8

D D

Audio_SW9

C

Audio_SW

C255

0.1uF/6

R540

4.7K/6

3

+12V_SW

2

CN11

EIC_4606-05/NC

1
2
3
4
5

1

From M/B input 12V

C

CN12

4500-E04N/NC

1
2
3
4

SDA_FAN
SCL_FAN

+3.3V

Light_Sensor

U36

NC7SB3157P6X_NL(AL003157107)

3

B0

VCC
A
S

NC7SB3157P6X_NL(AL003157107)

VCC
A
S

GND

U37

GND

1

B1

2

3

B0

1

B1

2

4

R548 0R/6/NC

R549 0R/6/NC

R544 0R/6

R547 0R/6

+3.3V

Q66

2N7002

3

2

1

3

R545 10K/6

R546 10K/6

2

Q67
2N7002

1

SDA_FAN

SCL_FAN

SDA_FAN 10

SCL_FAN 10

TechView International Technology Inc.

No.361,5F.,Fu-Sing 1 Rd.,Gueishan Hsiang, Taoyuan, Taiwan

Title :

12.PC_POWER
SCH File Name :
P

3

2

Standard Circuit Design

Check:Approval:

Document Number:

hS:etaD

tee

1

Tel :[phone]
Fax:[phone]

<Doc>

B

B2A

Size :

>veR<>emaN BCP<

:veR BCP: emaN eliF BC

of

Rev:

Draw:

11 11Friday, January 09, 2009

18430_531_090204.eps

090204

C261

0.1uF/6

C262

0.1uF/6

+5VS

+5VS

5
4
6

5
4
6

B B

SDA_SUB4,5,8,9,10

SYS_POWERON4,8,9

4,5,8,9,10

A A

SCL_SUB

5

SDA_SUB

SYS_POWERON

SCL_SUB

2009-Mar-20

IR LED board

5

5

4

4

3

3

2

2

1

1

D

D

C C

B B

A A

SCL

LS3.3VSDA

SCL

SDA

REMO_V33

REMO_V33

REMO_V33

IR_DATA

RED

GREEN

IR_DATA

GREEN

RED

Title

veRreb

muN t

nem

uco

D

ez

iS

teehS

:eta

D

of

02.IR_LED

PROJECT NAME:

A

33Thursday, January 08, 2009

MLTT86 Package

1

2

3

4

SMD IR Sensor

Package : REV_4P

WLZR

WJZS MST5251

A1A

Part modified

SMD Connector

1

R8 0R/6

FIX6

FIX_MASK

L1 JP/RC0603

1

2

1

R7
100K/6

C3
10uF/8

C2 10uF/8

D2

ROHM_SML020MLTT86

4

1

3

2

1

1

2

2

3

3

4

4

5

5

6677889

9

R6
0R/6

D1

3.3V

1 2

R2

10k/6/NC

FIX1

FIX_MASK

R4 100R/6

1

1

2

2

3

3

4

4

5

5

6677889

9

FIX4

FIX_MASK

U2

OPTO_FM_1040FN_F_5NR_REV_4P

3
2
1
4

R1

10k/6/NC

FIX5

FIX_MASK

CN1
3801_1.25pi

tch_8pin

4

4

3

3

2

2

1

1

8

8

7

7

5

5

6

6

9

9

10

10

R5 100R/6

R9 47R/6

R3
0R/6

R10

3.3K/6

C1

0.1uF/6

U1

ISL29010

VDD

1

GND

2

REXT

3

A0

4

SCL

5

SDA

6

FIX2

FIX_MASK

FIX3

FIX_MASK

18430_532_090204.eps

090204

Circuit Diagrams and PWB Layouts

EN 70QCG1.0S LA 10.

2009-Mar-20