Philips AN1651 User Manual

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AN1651

Using the NE/SA5234 amplifier

Author: Les Hadley 1991 Oct

INTEGRATED CIRCUITS

Philips Semiconductors Application note

AN1651Using the NE/SA5234 amplifier

2

1991 Oct

Author: L. Hadley

I. SUMMARY

The NE/SA5234 is a unique low-voltage quad operational amplifier
specifically designed to operate in a broadly diverse environment. It
is an enhanced pin-for-pin replacement for the LM324 category of
devices. Supply conditions can range from 1.8V to 6.0V with a
resultant current drain of 2.8mA,-700µA per op amp.

Most notable are the input and output dynamic range characteristics
of the individual op amps. The common-mode input voltage can
actually exceed the positive and negative supply rails by 250mV
with no danger of output latching or polarity reversal. In addition, the
output of each op amp will swing to within 50mV of the supply rails
over the full supply range.

The frequency related characteristics are also above average for
low voltage devices in this class. Internal unity gain compensation
makes the NE5234 very resistant to any tendency to oscillate in low
closed-loop gain configurations. Even so, a unity-gain bandwidth of

2.5MHz is retained. Slew rate is 0.8V/µs and each op amp will
settle to a 1% of nominal level within 1.4µs.

II. DETAILED DESCRIPTION
Input Stage

The input differential amplifier consists of a compound transistor
structure of parallel NPN and PNP transistors which account for the
unique over-drive characteristics of the NE5234. Referring to Figure
1, it is seen that the NPN pair, Q1 and Q2, allow the input to
operate in the common-mode input voltage range of 1V above V

EE

.
This region is designated the N-mode region in Figure 3a.
Operation in the common-mode range below 1V transfers the input
stage into the P-mode of operation.

In the N-mode operating condition, collector current from Q1 and Q2
is summed in the output emitter node of Q10 and Q12 respectively.
Q1’s base is the non-inverting input and Q2’s base the inverting
input node for the amplifier.

V

CC

R10

R11

VB2

Q10

Q12

VB1

IB1

Q2

Q4Q3

Q5

SWITCH

Q9

R8 R9

Q6

Q7

Q8

I

P

I

N

V

BIAS

IN(–)

(+)

+

–

Q2

SL00630

Figure 1. NE5234 Input Stage

Linear operation between the two modes is governed by a current
steering circuit consisting of Q5,6 and 7 in conjunction with voltage
reference VB1. Operation in the

N-region of the common-mode range will automatically cause Q5 to
transfer the IB1 current source to Q7 and the NPN transistor pair Q1
and Q2. Operation below the 1V level at the inputs allows the
current from IB1 to be fed directly to Q3 and Q4 emitters giving them
priority in processing the signal and linearizing their transfer
function. (The sum of the NPN and PNP input pair currents remain
constant.)

Operation in the common-mode range near the positive supply rail
would normally cause the input stage NPN transistor’s base

collector junction to become forward biased (base current flow
directly to the collector circuit) reversing the collector current flow
direction. In a conventional op amp, this would have the adverse
effect of reversing the output signal polarity as the operating region
is traversed by the input signal. (see Figure 2)

To prevent this from occurring, large geometry diode-connected
transistors are cross-connected to the opposite NPN collector, (Q1,
Q2). This current, in turn, is summed at the emitter of Q12 pulling it
above the V

CC

rail voltage and preventing polarity reversal. The
inverse condition occurs when Q2 is driven above the positive rail,
with Q10 emitter being pulled up and signal polarity preserved. (See
Figure 1)

Philips Semiconductors Application note

AN1651Using the NE/SA5234 amplifier

1991 Oct

3

47k

47k

V

IN

V

OUT

V

CC

+
–

5V

CONVENTIONAL OP AMP PHILIPS NE5234

t

t

V

CC

V

OUT

V

OUT

V

IN

V

IN

V

GND

V

GND

V

GND

V

CC

5V

SL00569

Figure 2. Output Inversion Protection

6

5

4

3

2

1

0.5

-1

-0.1

+0.1

“N-MODE”

CMRR

V

EE

+1 < VCM < V

CC

“LARGE

SIGNAL”

CMRR

“N-MODE”

CMRR

V

EE

< VCM < VEE+0.5V

V

EE

V

OS

mV

COMMON MODE VOLTAGE (VOLTS)

NE5234 Common-Mode Operating Regions

SL00631

Figure 3.

For negative going input signals, which drive the inputs toward the
V

EE

rail and below, another set of diode-connected transistors come
into operation. These steer the current from the input into Q8 or Q9
emitter circuits again preventing the reversal effect.

Figure 3 shows graphically how the N and P mode transitions relate
to the common-mode input voltage and the offset voltage V

OS

.

Intermediate Amplifier and Output Stage
(Figure 4)

The intermediate stage is isolated from the input amplifier by emitter
followers
to prevent any adverse loading effect. This stage adds gain to the
over all amplifier and translates levels for the following class-AB
current-control driver. Note that I

2

is the inverting input and I1 the

non-inverting input. The output is taken from multiple collectors on
the non-inverting side and provides matching for the following stage.

Class-AB control of the output stage is achieved by Q61 and Q62
with the associated output current regulators. These act to monitor
the smallest current of the non-load supporting output transistor to
keep it in conduction. Thus, neither Q71 or Q81 is allowed to cutoff
but is forced to remain in the proper Class-AB region.

Overload protection is provided by monitor circuits consisting of
R76-D2 for sinking and R86-D3 for sourcing condition at the output.
When the output current, source or sink, reaches 15 milliamperes,
drive current to the stage is shunted away from current sources IB6
or IB9 reducing base current to driver transistors Q72 and Q82
respectively.

The prevention of saturation in the output stage is achieved by
saturation detectors Q78 and Q88. When either Q71 or Q81
approaches saturation, current is shunted away from the driver
transistors, Q72 or Q83 respectively.

III. CHARACTERISTICS
Internal Frequency Compensation

The use of nested Miller capacitors C2 through C6, in the
intermediate and output sections, provides the overall frequency
compensation for the amplifier. The dominant pole setting capacitor,
C2, provides a constant 6dB/octave roll-off to below the unity gain
frequency of 2.5MHz. Figure 5 shows the measured frequency
response plot for various values of closed-loop gains.

Philips Semiconductors Application note

AN1651Using the NE/SA5234 amplifier

1991 Oct

4

D2

I

B2

I

B4

I

B5

I

B6

I

B8

I

B7

I

B9

I

B3

V

B4

V

CC

I

2

I

1

V

EE

D3

CLASS

AB

CONTROL

Q61 Q62

Q83

Q85

Q81

Q82

Q71

Q75

Q72

Q78

Q53,54

Q51,52

C1

C2

C3

C4

C5

R82

C6

Q84

OUTPUT

INPUT

+

–

INTERMEDIATE STAGE CURRENT CONTROL CLASS AB OUTPUT

R85 R76

R86 R75

SL00632

Figure 4.

dB

100

80

60

40

20

0

10Hz 100Hz 1kHz 10kHz 100kHz 1MHz

FREQUENCY

10  10

6

G1000

SL00633

Figure 5. NE5234 Closed Loop Gain vs Frequency

Philips Semiconductors Application note

AN1651Using the NE/SA5234 amplifier

1991 Oct

5

4

11

+
–

47k

5234

100

x10

HP
3585
SPECTRUM
ANALYZER

10Ω

600Ω

+2.5V

–2.5V

SL00634

Figure 6. Noise Test Circuit

IV. NOISE REFERRED TO THE INPUT

The typical spectral voltage noise referred to each of the op amps in
the NE/SA5234 is specified to be 25nV/√Hz. Current noise is not
specified. In the interest of providing a balance of information on the
device parameters, a small sample of the standard NE5234s, were
tested for input noise current. While this data does not represent a
specification, it will give the designer a ball park figure to work with
when beginning a particular design with the device. For
completeness I have provided the corresponding spectral noise
voltage data for the same sample. The data was taken using an
HP3585A spectrum analyzer which has the capability of reading
noise in nV/√Hz.

The test circuit is shown in Figure 6. As is typical for such
measurements the amplifier under test is terminated at its input first
with a very low resistance, for the voltage noise reading, followed by
the same test with a high value of resistance to register the effect of
current noise. The amplifier is set to a non-inverting
closed-loop gain of 20dB. Dual supply operation was chosen to
allow direct termination of the input resistors to ground.

The measurements were made over the range from 200Hz to 2kHz.
Each sample is measured at 200Hz, 500Hz, 1kHz and 2kHz. The
data is averaged for each frequency and then the small sample
distribution is derived statistically giving the standard deviation
relative to the mean.

Referring to the graph in Figure 7a, the equivalent voltage noise is
seen to average 18 nV/√Hz. The 95% confidence interval is
determined to be approximately one nV/√Hz. The majority of the
errors which contribute to this measurement are due to the thermal
noise of the parallel combination of the feedback resistor network, in
addition to the 10Ω termination resistor on the non-inverting input.
At 300° Kelvin a 10Ω resistor generates 0.4 nV/√Hz and the
feedback network’s equivalent resistance of 90Ω generates

1.2nV/√Hz. Their order-of-magnitude difference from the main noise
sources allows them to be neglected in the overall calculation of
total stage noise.

Noise current is measured across a 47kΩ resistor and averaged in
the same manner. The thermal noise generated by this large
resistance is not insignificant. At room temperature it is 28nV/√Hz
and must be subtracted from the total noise as measured at the
output of the op amp in order to arrive at the equivalent current
generated noise voltage. Figure 7b shows the derived current
noise distribution for the small sample of 10 NE5234 devices. The
result shows that noise current in the 200Hz to 2kHz frequency is

typically 0.2pA/√Hz. The 1/f region was not determined for either
current or voltage noise.

95%

INT.

En for RS = 10Ω -nV/Hz

22

19

18

17

16

100 200 2000 10000

nV

Hz

Ǹ

a.

pAńHz

Ǹ

0.5

12

0.1
100

200

1k

2k

10000Hz

f

P

in 10

P

b.

SL00635

Figure 7. Typical Noise Current and Voltage vs Frequency

V. GUIDE LINES FOR MINIMIZING NOISE

When designing a circuit where noise must be kept to a minimum,
the source resistances should be kept low to limit thermally
generated degradation in the overall output response.
Orders-of-magnitude should be kept in mind when evaluating noise
performance of a particular circuit or in planning a new design. For
instance, a transducer with a 10kΩ source resistance will generate
2µV of RMS noise over a 20kHz bandwidth. Using the graphical
data above, total noise from a gain stage may be calculated.-

25nVń Hz

Ǹ

@ BWǸ+ 3.5V

RMS

(EQ. 1.)

Amplifier Noise Voltage

BW + 10kHz

Noise from source 10kΩ Resistance –

14nVń Hz

Ǹ

@ BWǸ+ 20V

RMS

(EQ. 2.)

Noise Voltage from source resistance

0.2pAń Hz

Ǹ

@ 103@ BWǸ+ 0.28V

RMS

(EQ. 3.)

Current generated noise

The total noise is the root-to-sum-of-the-squares of the individual
noise voltages –

+

)

)

Ǹ

(EQ. 4.)

+ 4.04V

RMS

En

(3.5)

2

(2.0)

2

(0.28)

2

To determine the signal-to-noise ratio of the stage we must first
choose a stage gain, make it 40dB, and a signal voltage magnitude
from the transducer which we will set at 10mV

. The resulting

RMS

Philips Semiconductors Application note

AN1651Using the NE/SA5234 amplifier

1991 Oct

6

signal-to-noise ratio at the output of this stage is determined by first
multiplying the gain times the signal which gives 1V

RMS

with a

resultant noise of 400mV

RMS

. The signal-to-noise ratio is calculated

as

Sń N 20log

10

(1.0ń 4x10

* 4

) + 68dB

(EQ. 5.)

This is quite adequate for good quality audio applications.
Next assume that the bandwidth is cut to 3.0kHz with an input of

1mV

RMS

. The RMS noise is modified by the ratio of the root of the

noise channel bandwidths.

ƪ

Ǹ

20x10

3

Ǹ

ƫ @ EN + 1.6V

RMS

(EQ. 6.)

ƪ

*

*

ƫ

(EQ. 7.)

+ 56dB

+

–

+
–

1mV

RMS

e

n

x100

R

S

= 100Ω

1.6µV
e

n

x10

100kΩ

1mV

RMS

SIGNAL

SL00636

Figure 8.

UNITY GAIN

+
–

10k

100k

3
2

1

600Ω

2.2µF

1µF

R

L

= 600Ω

V

CC

+

V

CC

2

+

–

3
2

1

10k 10k

+

1k

100pF10k

4.7µF

1µF

1µF

600Ω

V

CC

2

40dB CIRCUIT

ST1700
DISTORTION
ANALYZER

V

CC

ST1700

SL00637

Figure 9. NE5234 THD Test Circuits

VI. MULTIPLE STAGE CONSIDERATIONS

Since multiple noise generators are non-coherent, their total effect is
the root-of-the-sum-of-the-squares of the various noise generators
at a given amplifier input.
This makes orders-of-magnitude lower noise sources less important
than the higher magnitude source. Therefore, when considering the
combined signal-to-noise of multiple stages of gain, the first stage in
a chain dominates making its design parameters the most critical.
For this reason it is good practice to make the preamp stage gain as
high as practical to boost signal levels to the second stage allowing
at least an order-of-magnitude above the second-stage noise. For

instance, a signal input which exceeds the input noise of the
following stage by a factor of 10:1 will only be degraded by 0.5% or

-46dB, neglecting the first-stage noise. If we use the preceding
example with a first-stage output signal of 100mV

RMS

and a 56dB
S/N, and an output noise of 0.16mV . Following this with a 10kHz
band limited gain-of-10 second-stage, with a 100kΩ noise source at
the non-inverting input, the combined S/N is calculated as follows:
(assume a 100Ω source resistance from amplifier #1)

The Second stage output noise is:

3

3x10

Amplified Noise = 160µV

RMS

SńN 20 log

10

100x10

1.6x10

3

4

A 56dB S/N will provide superior voice channel communications .

+1.6mV

RMS

NOISE