Philips 87c552 DATASHEETS
INTEGRATED CIRCUITS
NOTICE
PLEASE SEE THE P87C552 DA TA SHEET FOR NEW DESIGN-INS
87C552
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM,
capture/compare, high I/O
Product specification
Supersedes data of 1998 Jan 19
IC20 Data Handbook
1998 May 01
Philips Semiconductors Product specification
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O
DESCRIPTION
The 87C552 Single-Chip 8-Bit Microcontroller is manufactured in an
advanced CMOS process and is a derivative of the 80C51
microcontroller family. The 87C552 has the same instruction set as
the 80C51. Three versions of the derivative exist:
•83C552—8k bytes mask programmable ROM
•80C552—ROMless version of the 83C552
•87C552—8k bytes EPROM
The 87C552 contains a 8k × 8 a volatile 256 × 8 read/write data
memory, five 8-bit I/O ports, one 8-bit input port, two 16-bit
timer/event counters (identical to the timers of the 80C51), an
additional 16-bit timer coupled to capture and compare latches, a
15-source, two-priority-level, nested interrupt structure, an 8-input
ADC, a dual DAC pulse width modulated interface, two serial
interfaces (UART and I
oscillator and timing circuits. For systems that require extra
capability , the 87C552 can be expanded using standard TTL
compatible memories and logic.
In addition, the 87C552 has two software selectable modes of power
reduction—idle mode and power-down mode. The idle mode freezes
the CPU while allowing the RAM, timers, serial ports, and interrupt
system to continue functioning. The power-down mode saves the
RAM contents but freezes the oscillator, causing all other chip
functions to be inoperative.
The device also functions as an arithmetic processor having
facilities for both binary and BCD arithmetic plus bit-handling
capabilities. The instruction set consists of over 100 instructions: 49
one-byte, 45 two-byte, and 17 three-byte. With a 16MHz crystal,
58% of the instructions are executed in 0.75µs and 40% in 1.5µs.
Multiply and divide instructions require 3µs.
2
C-bus), a “watchdog” timer and on-chip
FEATURES
•80C51 central processing unit
•8k × 8 EPROM expandable externally to 64k bytes
•An additional 16-bit timer/counter coupled to four capture registers
and three compare registers
•Two standard 16-bit timer/counters
•256 × 8 RAM, expandable externally to 64k bytes
•Capable of producing eight synchronized, timed outputs
•A 10-bit ADC with eight multiplexed analog inputs
•Two 8-bit resolution, pulse width modulation outputs
•Five 8-bit I/O ports plus one 8-bit input port shared with analog
inputs
2
•I
C-bus serial I/O port with byte oriented master and slave
functions
•Full-duplex UART compatible with the standard 80C51
•On-chip watchdog timer
•16MHz speed
•Extended temperature ranges
•OTP package available
87C552
ORDERING INFORMATION
EPROM TEMPERATURE °C AND PACKAGE
S87C552-4A68 0 to +70, Plastic Leaded Chip Carrier 16 SOT188-3
S87C552-4BA 0 to +70, Plastic Quad Flat Pack 16 SOT318-2
S87C552-5A68 –40 to +85, Plastic Leaded Chip Carrier 16 SOT188-3
NOTE:
1. For ROM and ROMless see data sheet 80C552/83C552
1998 May 01 853-1690 19336
2
FREQ
MHz
DRAWING NUMBER
Philips Semiconductors Product specification
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O
BLOCK DIAGRAM
T0 T1 INT0 INT1
XTAL1
XTAL2
EA
ALE
PSEN
3
3
0
WR
RD
3 3 3 3
T0, T1
TWO 16-BIT
TIMER/EVENT
COUNTERS
80C51 CORE
EXCLUDING
ROM/RAM
CPU
V
DD
PROGRAM
MEMORY
8k x 8
EPROM
16
8-BIT INTERNAL BUS
V
SS
DATA
MEMORY
256 x 8 RAM
PWM0 PWM1
DUAL
PWM
87C552
AV
REF
–+
ADC
STADC
ADC0-7 SDA SCL
SERIAL
2
I
C PORT
115
AV
SS
AV
DD
AD0-7
2
A8-15
0
ALTERNATE FUNCTION OF PORT 0
1
ALTERNATE FUNCTION OF PORT 1
2
ALTERNATE FUNCTION OF PORT 2
PARALLEL I/O
PORTS AND
EXTERNAL BUS
P0 P1 P2 P3 TxD RxD P5 P4 CT0I-CT3I T2 RT2 CMSR0-CMSR5
SERIAL
UART
PORT
3 3
3
ALTERNATE FUNCTION OF PORT 3
4
ALTERNATE FUNCTION OF PORT 4
5
ALTERNATE FUNCTION OF PORT 5
8-BIT
PORT
16
T2
16-BIT
COMPARA-
TORS
WITH
REGISTERS
FOUR
16-BIT
CAPTURE
LATCHES
1 1 1 4
T2
16-BIT
TIMER/
EVENT
COUNTERS
COMPARA-
TOR
OUTPUT
SELECTION
CMT0, CMT1
T3
WATCHDOG
TIMER
RST EW
SU00211
1998 May 01
3
Philips Semiconductors Product specification
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O
LOGIC SYMBOL
V
SS
V
DD
XTAL1
XTAL2
V
EA/
PP
ALE/PROG
PSEN
AV
SS
AV
DD
AVref+
AVref–
STADC
PWM0
PWM1
ADC0-7
PORT 5
CMSR0-5
RST
EW
PORT 4
CMT0
CMT1
PORT 0
PORT 1PORT 2PORT 3
RxD/DATA
TxD/CLOCK
ADDRESS AND
CT0I
CT1I
CT2I
CT3I
T2
RT2
SCL
SDA
HIGH ORDER
ADDRESS AND
DATA BUS
INT0
INT1
T0
T1
WR
RD
LOW ORDER
DATA BUS
SU00210
PIN CONFIGURATIONS
Pin Function
1 P5.0/ADC0
2V
3 STADC
4 PWM0
5 PWM1
6EW
7 P4.0/CMSR0
8 P4.1/CMSR1
9 P4.2/CMSR2
10 P4.3/CMSR3
11 P4.4/CMSR4
12 P4.5/CMSR5
13 P4.6/CMT0
14 P4.7/CMT1
15 RST
16 P1.0/CT0I
17 P1.1/CT1I
18 P1.2/CT2I
19 P1.3/CT3I
20 P1.4/T2
21 P1.5/RT2
22 P1.6/SCL
23 P1.7/SDA
87C552
9161
10
PLASTIC
LEADED
CHIP CARRIER
26
Pin Function
24 P3.0/RxD
DD
25 P3.1/TxD
26 P3.2/INT0
27 P3.3/INT1
28 P3.4/T0
29 P3.5/T1
30 P3.6/WR
31 P3.7/RD
32 NC
33 NC
34 XTAL2
35 XTAL1
36 V
SS
37 V
SS
38 NC
39 P2.0/A08
40 P2.1/A09
41 P2.2/A10
42 P2.3/A11
43 P2.4/A12
44 P2.5/A13
45 P2.6/A14
46 P2.7/A15
60
44
4327
Pin Function
47 PSEN
48 ALE/PROG
49 EA/V
50 P0.7/AD7
51 P0.6/AD6
52 P0.5/AD5
53 P0.4/AD4
54 P0.3/AD3
55 P0.2/AD2
56 P0.1/AD1
57 P0.0/AD0
58 AVref–
59 AVref+
60 AV
61 AV
62 P5.7/ADC7
63 P5.6/ADC6
64 P5.5/ADC5
65 P5.4/ADC4
66 P5.3/ADC3
67 P5.2/ADC2
68 P5.1/ADC1
PP
SS
DD
SU00208
PLASTIC QUAD FLAT PACK PIN FUNCTIONS
Pin Function
1 P4.1/CMSR1
2 P4.2/CMSR2
80 65
1
PQFP
24
25 40
64
41
3NC
4 P4.3/CMSR3
5 P4.4/CMSR4
6 P4.5/CMSR5
7
8 P4.7/CMT1
9 RST
10 P1.0/CT0I
11 P1.1/CT1I
12 P1.2/CT2I
13
14 P1.4/T2
15 P1.5/RT2
16 P1.6/SCL
17 P1.7/SDA
18 P3.0/RxD
19 P3.1/TxD
20 P3.2/INT0
NC = Not Connected
IC = Internally Connected (do not use)
P4.6/CMT0
P1.3/CT3I
Pin Function
21 NC
22 NC
23 P3.3/INT1
24 P3.4/T0
25 P3.5/T1
26 P3.6/WR
27 P3.7/RD
28 NC
29 NC
30 NC
31 XTAL2
32 XTAL1
33 IC
34 V
SS
35 V
SS
36 V
SS
37 NC
38 P2.0/A08
39 P2.1/A09
40 P2.2/A10
Pin Function
41 P2.3/A11
42 P2.4/A12
43 NC
44 NC
45 P2.5/A13
46 P2.6/A14
47 P2.7/A15
48 PSEN
49 ALE/PROG
50 EA/V
51 P0.7/AD7
52 P0.6/AD6
53 P0.5/AD5
54 P0.4/AD4
55 P0.3/AD3
56 P0.2/AD2
57
58 P0.0/AD0
59 AVref–
60 AVref+
PP
P0.1/AD1
Pin Function
61 AV
SS
62 NC
63 AV
DD
64 P5.7/ADC7
65 P5.6/ADC6
66 P5.5/ADC5
67 P5.4/ADC4
68 P5.3/ADC3
69 P5.2/ADC2
70 P5.1/ADC1
71 P5.0/ADC0
72 V
DD
73 IC
74 STADC
75 PWM0
76 PWM1
77 EW
78 NC
79 NC
80 P4.0/CMSR0
SU00209
1998 May 01
4
Philips Semiconductors Product specification
80C51 8-bit microcontroller
87C552
8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O
PIN DESCRIPTION
PIN NO.
MNEMONIC PLCC QFP TYPE NAME AND FUNCTION
V
DD
STADC 3 74 I Start ADC Operation: Input starting analog to digital conversion (ADC operation can also
PWM0 4 75 O Pulse Width Modulation: Output 0.
PWM1 5 76 O Pulse Width Modulation: Output 1.
EW 6 77 I Enable Watchdog Timer: Enable for T3 watchdog timer and disable power-down mode.
P0.0-P0.7 57-50 58-51 I/O Port 0: Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written
P1.0-P1.7 16-23 10-17 I/O Port 1: 8-bit I/O port. Alternate functions include:
P2.0-P2.7 39-46 38-42,
P3.0-P3.7 24-31 18-20,
P4.0-P4.7 7-14 80, 1-2
P5.0-P5.7 68-62, 71-64, I Port 5: 8-bit input port.
RST 15 9 I/O Reset: Input to reset the 87C552. It also provides a reset pulse as output when timer T3
XTAL1 35 32 I Crystal Input 1: Input to the inverting amplifier that forms the oscillator, and input to the
XTAL2 34 31 O Crystal Input 2: Output of the inverting amplifier that forms the oscillator. Left open-circuit
V
SS
PSEN 47 48 O Program Store Enable: Active-low read strobe to external program memory.
2 72 I Digital Power Supply: +5V power supply pin during normal operation, idle and
16-21 10-15 I/O (P1.0-P1.5): Quasi-bidirectional port pins.
22-23 16-17 I/O (P1.6, P1.7): Open drain port pins.
16-19 10-13 I CT0I-CT3I (P1.0-P1.3): Capture timer input signals for timer T2.
20 14 I T2 (P1.4): T2 event input.
21 15 I RT2 (P1.5): T2 timer reset signal. Rising edge triggered.
22 16 I/O SCL (P1.6): Serial port clock line I2C-bus.
23 17 I/O SDA (P1.7): Serial port data line I2C-bus.
45-47
23-27
24 18 RxD(P3.0): Serial input port.
25 19 TxD (P3.1): Serial output port.
26 20 INT0 (P3.2): External interrupt.
27 23 INT1 (P3.3): External interrupt.
28 24 T0 (P3.4): Timer 0 external input.
29 25 T1 (P3.5): Timer 1 external input.
30 26 WR (P3.6): External data memory write strobe.
31 27 RD (P3.7): External data memory read strobe.
4-8
7-12 80, 1-2
4-6
13, 14 7, 8 O CMT0, CMT1 (P4.6, P4.7): Timer T2 compare and toggle outputs on a match with timer T2.
1 ADC0-ADC7 (P5.0-P5.7): Alternate function: Eight input channels to ADC.
36, 37 34-36 I Digital ground.
power-down mode.
be started by software).
to them float and can be used as high-impedance inputs. Port 0 is also the multiplexed
low-order address and data bus during accesses to external program and data memory. In
this application it uses strong internal pull-ups when emitting 1s. Port 0 is also used to input
the code byte during programming and to output the code byte during verification.
Port 1 is also used to input the lower order address byte during EPROM programming and
verification. A0 is on P1.0, etc.
I/O Port 2: 8-bit quasi-bidirectional I/O port.
Alternate function: High-order address byte for external memory (A08-A15). Port 2 is also
used to input the upper order address during EPROM programming and verification. A8 is
on P2.0, A9 on P2.1, through A12 on P2.4.
I/O Port 3: 8-bit quasi-bidirectional I/O port. Alternate functions include:
I/O Port 4: 8-bit quasi-bidirectional I/O port. Alternate functions include:
O CMSR0-CMSR5 (P4.0-P4.5): Timer T2 compare and set/reset outputs on a match with
timer T2.
overflows.
internal clock generator. Receives the external clock signal when an external oscillator is
used.
when an external clock is used.
1998 May 01
5
Philips Semiconductors Product specification
80C51 8-bit microcontroller
87C552
8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O
PIN DESCRIPTION (Continued)
PIN NO.
MNEMONIC PLCC QFP TYPE NAME AND FUNCTION
ALE/PROG 48 49 O Address Latch Enable: Latches the low byte of the address during accesses to external
EA/V
PP
AV
REF–
AV
REF+
AV
SS
AV
DD
NOTE:
1. To avoid “latch-up” effect at power-on, the voltage on any pin at any time must not be higher or lower than V
respectively.
49 50 I External Access: When EA is held at TTL level high, the CPU executes out of the internal
58 59 I Analog to Digital Conversion Reference Resistor: Low-end.
59 60 I Analog to Digital Conversion Reference Resistor: High-end.
60 61 I Analog Ground
61 63 I Analog Power Supply
memory. It is activated every six oscillator periods. During an external data memory
access, one ALE pulse is skipped. ALE can drive up to eight LS TTL inputs and handles
CMOS inputs without an external pull-up. This pin is also the program pulse input (PROG
during EPROM programming.
program ROM provided the program counter is less than 8192. When EA
low level, the CPU executes out of external program memory. EA
This pin also receives the 12.75V programming supply voltage (V
programming.
+ 0.5V or VSS – 0.5V,
DD
is held at TTL
is not allowed to float.
) during EPROM
PP
)
OSCILLA T OR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output, respectively , of an
inverting amplifier . The pins can be configured for use as an on-chip
oscillator, as shown in the logic symbol.
To drive the device from an external clock source, XTAL1 should be
driven while XTAL2 is left unconnected. There are no requirements
on the duty cycle of the external clock signal, because the input to
the internal clock circuitry is through a divide-by-two flip-flop.
However, minimum and maximum high and low times specified in
the data sheet must be observed.
RESET
A reset is accomplished by holding the RST pin high for at least two
machine cycles (24 oscillator periods), while the oscillator is running.
To insure a good power-on reset, the RST pin must be high long
enough to allow the oscillator time to start up (normally a few
milliseconds) plus two machine cycles. At power-on, the voltage on
V
and RST must come up at the same time for a proper start-up.
DD
IDLE MODE
In the idle mode, the CPU puts itself to sleep while some of the
on-chip peripherals stay active. The instruction to invoke the idle
mode is the last instruction executed in the normal operating mode
before the idle mode is activated. The CPU contents, the on-chip
RAM, and all of the special function registers remain intact during
this mode. The idle mode can be terminated either by any enabled
interrupt (at which time the process is picked up at the interrupt
service routine and continued), or by a hardware reset which starts
the processor in the same manner as a power-on reset.
POWER-DOWN MODE
In the power-down mode, the oscillator is stopped and the
instruction to invoke power-down is the last instruction executed.
Only the contents of the on-chip RAM are preserved. A hardware
reset is the only way to terminate the power-down mode. The control
bits for the reduced power modes are in the special function register
PCON. Table 1 shows the state of the I/O ports during low current
operating modes.
Table 1. External Pin Status During Idle and Power-Down Modes
MODE
Idle Internal 1 1 Data Data Data Data Data High
Idle External 1 1 Float Data Address Data Data High
Power-down Internal 0 0 Data Data Data Data Data High
Power-down External 0 0 Float Data Data Data Data High
PROGRAM
MEMORY
ALE PSEN PORT 0 PORT 1 PORT 2 PORT 3 PORT 4
PWM0/
PWM1
1998 May 01
6
Philips Semiconductors Product specification
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O
Serial Control Register (S1CON) – See Table 2
S1CON (D8H)
CR2 ENS1 STA STO SI AA CR1 CR0
Bits CR0, CR1 and CR2 determine the serial clock frequency that is generated in the master mode of operation.
Table 2. Serial Clock Rates
BIT FREQUENCY (kHz) AT f
CR2 CR1 CR0 6MHz 12MHz 16MHz f
0 0 0 23 47 62.5 256
0 0 1 27 54 71 224
0 1 0 31.25 62.5 83.3 192
0 1 1 37 75 100 160
1 0 0 6.25 12.5 17 960
1 0 1 50 100 133
1 1 0 100 200 267
1 1 1 0.25 < 62.5 0.5 < 62.5 0.67 < 56 96 × (256 – (reload value Timer 1))
0 to 225 0 to 224 0 to 223 Timer 1 in Mode 2.
NOTE:
1. These frequencies exceed the upper limit of 100kHz of the I
2
C-bus specification and cannot be used in an I2C-bus application.
OSC
DIVIDED BY
OSC
1
1
120
60
87C552
ABSOLUTE MAXIMUM RATINGS
Storage temperature range –65 to +150 °C
Voltage on EA/VPP to V
Voltage on any other pin to V
Input, output DC current on any single I/O pin 5.0 mA
Power dissipation (based on package heat transfer limitations, not device power
consumption)
NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section
of this specification is not implied.
2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima.
3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V
noted.
SS
SS
1, 2, 3
PARAMETER
RATING UNIT
–0.5 to +13 V
–0.5 to +6.5 V
1.0 W
unless otherwise
SS
DEVICE SPECIFICATIONS
SUPPLY VOLTAGE (V) FREQUENCY (MHz)
TYPE MIN MAX MIN MAX TEMPERATURE RANGE (°C)
P87C552-4 4.5 5.5 3.5 16 0 to +70
P87C552-5 4.5 5.5 3.5 16 –40 to +85
1998 May 01
7
Philips Semiconductors Product specification
2V
V
V
80C51 8-bit microcontroller
87C552
8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O
DC ELECTRICAL CHARACTERISTICS
VSS, AVSS = 0V
TEST LIMITS
SYMBOL PARAMETER CONDITIONS MIN MAX UNIT
I
DD
I
ID
I
PD
Inputs
V
IL
V
IL1
V
IL2
V
IH
V
IH1
V
IH2
I
IL
I
TL
±I
IL1
±I
IL2
±I
IL3
Outputs
V
OL
V
OL1
V
OL2
V
OH
V
OH1
V
OH2
R
RST
C
IO
Analog Inputs
AV
DD
AI
DD
AI
ID
AI
PD
Supply current operating: See notes 1 and 2
PCA8XC552-5-16 f
= 16MHz 40 mA
OSC
Idle mode: See notes 1 and 3
87C552 f
= 16MHz 7 mA
OSC
Power-down current: See notes 1 and 4;
<
<
87C552
PD
DD
max
50 µA
Input low voltage, except EA, P1.6, P1.7 –0.5 0.2VDD–0.1 V
Input low voltage to EA –0.5 0.2VDD–0.3 V
Input low voltage to P1.6/SCL, P1.7/SDA
5
–0.5 0.3V
DD
Input high voltage, except XTAL1, RST 0.2VDD+0.9 VDD+0.5 V
Input high voltage, XTAL1, RST 0.7V
Input high voltage, P1.6/SCL, P1.7/SDA
5
0.7V
DD
DD
VDD+0.5 V
6.0 V
Logical 0 input current, ports 1, 2, 3, 4, except P1.6, P1.7 VIN = 0.45V –50 µA
Logical 1-to-0 transition current, ports 1, 2, 3, 4, except P1.6, P1.7 See note 6 –650 µA
Input leakage current, port 0, EA, STADC, EW 0.45V < V
Input leakage current, P1.6/SCL, P1.7/SDA
0V < V
Input leakage current, port 5 0.45V < V
Output low voltage, ports 1, 2, 3, 4, except P1.6, P1.7 IOL = 1.6mA
Output low voltage, port 0, ALE, PSEN, PWM0,
< V
I
0V < V
< 6V
I
< 5.5V
DD
< V
I
IOL = 3.2mA
7
7
DD
DD
10 µA
10 µA
1 µA
0.45 V
0.45 V
PWM1
Output low voltage, P1.6/SCL, P1.7/SDA IOL = 3.0mA
7
0.4 V
Output high voltage, ports 1, 2, 3, 4, except P1.6/SCL, P1.7/SDA
–IOH = 60µA 2.4 V
Output high voltage (port 0 in external bus mode, ALE,
PSEN, PWM0, PWM1)
8
–IOH = 25µA 0.75V
–IOH = 10µA 0.9V
–IOH = 400µA 2.4 V
–IOH = 150µA 0.75V
–IOH = 40µA 0.9V
DD
DD
DD
DD
Output high voltage (RST) –IOH = 400µA 2.4 V
–IOH = 120µA 0.8V
DD
Internal reset pull-down resistor 50 150 kΩ
Pin capacitance Test freq = 1MHz,
T
= 25°C
amb
10 pF
Analog supply voltage:
9
87C552
Analog supply current: operating: Port 5 = 0 to AV
AVDD = VDD±0.2V 4.5 5.5 V
DD
1.2 mA
Idle mode:
87C552 50 µA
Power-down mode: 2V < AVPD < AVDD max
87C552 50 µA
V
V
V
V
V
V
1998 May 01
8
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