Philips 83ce654 DATASHEETS

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83CE654

CMOS single-chip 8-bit microcontroller
with Electromagnetic Compatibility
improvements

Preliminary specification 1996 Aug 15

INTEGRATED CIRCUITS

IC20 Data Handbook

Philips Semiconductors Preliminary specification

83CE654

CMOS single-chip 8-bit microcontroller with
Electromagnetic Compatibility improvements

2

1996 Aug 15

DESCRIPTION

The 83CE654 Single-Chip 8-Bit
Microcontroller is manufactured in an
advanced CMOS process and is a derivative
of the 80C51 microcontroller family. The
83CE654 has the same instruction set as the
80C51. The 83CE654 has 16k bytes mask
programmable ROM and 256 bytes RAM.

This device provides architectural
enhancements that make it applicable in a
variety of applications for general control
systems. The 83CE654 contains a
non-volatile 16k × 8 read-only program
memory, a volatile 256 × 8 read/write data
memory, four 8-bit I/O ports, two 16-bit
timer/event counters (identical to the timers of
the 80C51), a multi-source, two-priority-level,
nested interrupt structure, an I

2

C interface,
UART and on-chip oscillator and timing
circuits. For systems that require extra
capability, the 83CE654 can be expanded
using standard TTL compatible memories
and logic.

The device also functions as an arithmetic
processor having facilities for both binary and
BCD arithmetic plus bit-handling capabilities.
The instruction set consists of over 100
instructions: 49 one-byte, 45 two-byte and
17 three-byte. With a 16MHz crystal, 58% of
the instructions are executed in 0.75µs and
40% in 1.5µs. Multiply and divide instructions
require 3µs.

FEATURES

•80C51 central processing unit

•16k × 8 ROM expandable externally to

64k bytes

•256 × 8 RAM, expandable externally to

64k bytes

•Two standard 16-bit timer/counters

•Four 8-bit I/O ports

•I

2

C-bus serial I/O port with byte oriented

master and slave functions

•Full-duplex UART facilities

•ROM code protection

•XTAL frequency range: 1.2MHz to 16MHz

•Software enable/disable of ALE output

pulse

•Electromagnetic compatibility (EMC)

improvements

•Operating ambient temperature range:

– P83CE654 FBB T

amb

0°C to +70°C

– P83CE654 FFB T

amb

–40°C to +85°C

PIN CONFIGURATION

PLASTIC

QUAD

FLAT

PACK

44 34

1

11

33

23

12 22

Pin Function Pin Function

1 P1.5 23 P2.5/A13
2 P1.6/SCL 24 P2.6/A14
3 P1.7/SDA 25 P2.7/A15
4 RST 26 PSEN
5 P3.0/RxD 27 ALE
6 V

SS4

28 V

SS2

7 P3.1/TxD 29 EA
8 P3.2/INT0 30 P0.7/AD7

9 P3.3/INT1 31 P0.6/AD6
10 P3.4/T0 32 P0.5/AD5
11 P3.5/T1 33 P0.4/AD4
12 P3.6/WR 34 P0.3/AD3
13 P3.7RD 35 P0.2/AD2
14 XTAL2 36 P0.1/AD1
15 XTAL1 37 P0.0/AD0
16 V

SS1

38 V

DD2

17 V

DD1

39 V

SS3

18 P2.0/A8 40 P1.0
19 P2.1/A9 41 P1.1
20 P2.2/A10 42 P1.2
21 P2.3/A11 43 P1.3
22 P2.4/A12 44 P1.4

LOGIC SYMBOL

PORT 0PORT 1PORT 2

PORT 3

ADDRESS AND

DATA BUS

ADDRESS BUS

VSSV

DD

ALTERNATE

FUNCTIONS

RST
XTAL1
XTAL2

EA

ALE

PSEN

RxD

TxD
INT0
INT1

T0
T1

WR

RD

SCL
SDA

Philips Semiconductors Preliminary specification

83CE654

CMOS single-chip 8-bit microcontroller with
Electromagnetic Compatibility improvements

1996 Aug 15

3

ORDERING INFORMATION

ROM

TEMPERATURE RANGE oC

AND PACKAGE

FREQUENCY

MHz

DRAWING NUMBER

P83CE654FBB 0 to +70, Plastic Quad Flat Pack 1.2 to 16 SOT307-2

1

P83CE654FFB –40 to +85, Plastic Quad Flat Pack 1.2 to 16 SOT307-2

1

NOTE:

1. SOT311 replaced by SOT307-2.

ELECTROMAGNETIC
COMPATIBILITY (EMC)
IMPROVEMENTS

Primary attention is paid on the reduction of
electromagnetic emission of the
microcontroller P83CE654.

The following features effect in reducing the
electromagnetic emission and additionally
improve the electromagnetic susceptibility:

•Two supply voltage pins (V

DD1

, V

DD2

) and

four ground pins (V

SS1

to V

SS4

)

•Separate V

DD

pins for the internal logic and

the port buffers

•Internal decoupling capacitance improves

the EMC radiation behavior and the EMC
immunity

•External capacitors are to be located as

close as possible between pins V

DD2

and

V

SS3

as well as V

DD1

and V

SS1

; ceramic

chip capacitors are recommended (100nF).

•The ALE output signal (pulses at a

frequency of f

OSC

/6) can be disabled under
software control (bit 5 in the SFR PCON:
“RFI”); if disabled, no ALE pulse will occur.

ALE pin will be pulled down internally,
switching an external address latch to a
quiet state. The MOVX instruction will still
toggle ALE as a normal MOVX. ALE will
retain its normal high value during Idle
mode and a low value during Power-down
mode while in the “RFI” reduction mode.
Additionally during internal access (EA

= 1)
ALE will toggle normally when the address
exceeds the internal program memory size.
During external access (EA

= 0) ALE will
always toggle normally, whether the flag
“RFI” is set or not.

BLOCK DIAGRAM

64K BYTE BUS

EXPANSION

CONTRTOL

PROG SERIAL PORT
FULL DUPLEX UART

SYNCHRONOUS SHIFT

PROGRAMMABLE I/O

CPU

OSCILLATOR

AND

TIMING

PROGRAM

MEMORY

DATA

MEMORY

(256 x 8 RAM)

TWO 16-BIT

TIMER/EVENT

COUNTERS

I

2

C SERIAL I/O

SDA

SCL

SHARED

WITH

PORT 1

T0 T1

COUNTER INPUTS SHARED WITH PORT 3

XTAL2 XTAL1

FREQUENCY
REFERENCE

INTERNAL

INTERRUPTS

INT0

INT1

EXTERNAL INTERRUPTS

SHARED WITH PORT 3

CONTROL

PARALLEL PORTS,

ADDRESS/DATA BUS

AND I/O PINS

SERIAL IN SERIAL OUT

SHARED WITH

PORT 3

(16K x 8 ROM)

Philips Semiconductors Preliminary specification

83CE654

CMOS single-chip 8-bit microcontroller with
Electromagnetic Compatibility improvements

1996 Aug 15

4

PIN DESCRIPTIONS

MNEMONIC

PIN

NUMBER

TYPE NAME AND FUNCTION

V

SS1

, V

SS2

,

V

SS3

, V

SS4

16, 28,

39, 6

I Ground: 0V reference. All pins must be connected.

V

DD1

, V

DD2

17, 38 I Power Supply: This is the power supply voltage for normal, idle, and power-down operation. Both pins

must be connected.

P0.0–0.7 37–30 I/O Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them float and can

be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during
accesses to external program and data memory. In this application, it uses strong internal pull-ups when
emitting 1s. Port 0 can sink/source 8 LSTTL inputs.

P1.0–P1.7 40–44,

1–3

I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups, except P1.6 and P1.7 which are open

drain. Port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as
inputs. As inputs, port 1 pins that are externally pulled low will source current because of the internal
pull-ups. (See DC Electrical Characteristics: I

IL

). Port 1 also receives the low-order address byte during

program memory verification. Alternate functions include:
P1.6 2 I/O SCL: I2C-bus serial port clock line.
P1.7 3 I/O SDA: I2C-bus serial port data line.

P2.0–P2.7 18–25 I/O Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s written to

them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 2 pins that are

externally being pulled low will source current because of the internal pull-ups. (See DC Electrical

Characteristics: I

IL

). Port 2 emits the high-order address byte during fetches from external program
memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this
application, it uses strong internal pull-ups when emitting 1s. During accesses to external data memory
that use 8-bit addresses (MOV @Ri), port 2 emits the contents of the P2 special function register.

P3.0–P3.7 5,

7–13

I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written to

them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 3 pins that are
externally being pulled low will source current because of the pull-ups. (See DC Electrical Characteristics:
I

IL

). Port 3 also serves the special features of the 80C51 family, as listed below:
5 I RxD (P3.0): Serial input port
7 O TxD (P3.1): Serial output port
8 I INT0 (P3.2): External interrupt 0 or gate control input for timer/event counter 0
9 I INT1 (P3.3): External interrupt 1 or gate control input for timer/event counter 1

10 I T0 (P3.4): Timer 0 external input
11 I T1 (P3.5): Timer 1 external input
12 O WR (P3.6): External data memory write strobe
13 O RD (P3.7): External data memory read strobe

RST 4 I Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. An

internal pull-down resistor to V

SS

permits a power-on reset using only an external capacitor to VDD.

ALE 27 I/O Address Latch Enable: Output pulse for latching the low byte of the address during an access to external

memory. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency, and can be
used for external timing or clocking. Note that one ALE pulse is skipped during each access to external
data memory. ALE can sink/source 8 LSTTL inputs. It can drive CMOS inputs without an external pull-up.
To prohibit the toggling of ALE pin (RFI noise reduction) the bit RFI in the PCON Register (PCON.5) must
be set by software. This bit is cleared on RESET and can be cleared by software. When set, ALE pin will
be pulled down internally, switching an external address latch to a quiet state. The MOVX instruction will
still toggle ALE as a normal MOVX. ALE will retain its normal high value during Idle mode and a low value
during Power-down mode while in the “RFI” mode. Additionally during internal access (EA

= 1) ALE will
toggle normally when the address exceeds the internal program memory size. During external access
(EA

= 0) ALE will always toggle normally, whether the flag “RFI” is set or not.

PSEN 26 O Program Store Enable: The read strobe to external program memory. When the 83CE654 is executing

code from the external program memory, PSEN

is activated twice each machine cycle, except that two

PSEN

activations are skipped during each access to external data memory. PSEN is not activated during

fetches from internal program memory. PSEN

can sink/source 8 LSTTL inputs.

EA 29 I External Access Enable: when, during RESET, EA is held at a TTL HIGH level the CPU executes out of

the internal program ROM, provided the program counter is less than 16384. When EA

is held at a TTL

LOW level during RESET, the CPU executes out of external program memory via Port 0 and Port 2. EA

is

not allowed to float.

XTAL1 15 I Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits.
XTAL2 14 O Crystal 2: Output from the inverting oscillator amplifier.

NOTE:

To avoid “latch-up” effect at power-on, the voltage on any pin at any time must not be higher or lower than V

DD

+ 0.5V or VSS – 0.5V,

respectively.

Philips Semiconductors Preliminary specification

83CE654

CMOS single-chip 8-bit microcontroller with
Electromagnetic Compatibility improvements

1996 Aug 15

5

Table 1. 83CE654 Special Function Registers

SYMBOL DESCRIPTION

DIRECT

ADDRESS

BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION
MSB LSB

RESET
VALUE

ACC* Accumulator E0H E7 E6 E5 E4 E3 E2 E1 E0 00H
B* B register F0H F7 F6 F5 F4 F3 F2 F1 F0 00H
DPTR:

DPH
DPL

Data pointer
(2 bytes)
Data pointer high
Data pointer low

83H
82H

00H
00H

AF AE AD AC AB AA A9 A8

IE*# Interrupt enable A8H EA ES1 ES0 ET1 EX1 ET0 EX0 0x000000B

BF BE BD BC BB BA B9 B8

IP*# Interrupt priority B8H – PS1 PS0 PT1 PX1 PT0 PX0 xx000000B

87 86 85 84 83 82 81 80

P0* Port 0 80H AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 FFH

97 96 95 94 93 92 91 90

P1*# Port 1 90H SDA SCL FFH

A7 A6 A5 A4 A3 A2 A1 A0

P2* Port 2 A0H A15 A14 A13 A12 A11 A10 A9 A8 FFH

B7 B6 B5 B4 B3 B2 B1 B0
P3* Port 3 B0H RD WR T1 T0 INT1 INT0 TXD RXD FFH
PCON# Power control 87H SMOD – RFI – GF1 GF0 PD IDL 0xxx0000B

9F 9E 9D 9C 9B 9A 99 98
S0CON*# Serial 0 port control 98H SM0 SM1 SM2 REN TB8 RB8 TI RI 00H
S0BUF# Serial 0 data buffer 99H xxxxxxxxB

D7 D6 D5 D4 D3 D2 D1 D0
PSW* Program status word D0H CY AC F0 RS1 RS0 OV F1 P 00H
S1DAT# Serial 1 data DAH 00H
SP Stack pointer 81H 07H
S1ADR# Serial 1 address DBH

 SLAVE ADDRESS 

GC 00H

S1STA# Serial 1 status D9H SC4 SC3 SC2 SC1 SC0 0 0 0 F8H

DF DE DD DC DB DA D9 D8
S1CON*# Serial 1 control D8H CR2 ENS1 STA STO SI AA CR1 CR0 00000000B

8F 8E 8D 8C 8B 8A 89 88
TCON* Timer control 88H TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00H
TH1 Timer high 1 8DH 00H
TH0 Timer high 0 8CH 00H
TL1 Timer low 1 8BH 00H
TL0 Timer low 0 8AH 00H
TMOD Timer mode 89H GATE C/T M1 M0 GATE C/T M1 M0 00H

* SFRs are bit addressable.
# SFRs are modified from or added to the 80C51 SFRs.

Philips Semiconductors Preliminary specification

83CE654

CMOS single-chip 8-bit microcontroller with
Electromagnetic Compatibility improvements

1996 Aug 15

6

ROM CODE PROTECTION

The 83CE654 has an additional security
feature. ROM code protection may be
selected by setting a mask-programmable
security bit (i.e., user dependent). This
feature may be requested during ROM code
submission. When selected, the ROM code is
protected and cannot be read out at any time
by any test mode or by any instruction in the
external program memory space.

The MOVC instructions are the only
instructions that have access to program
code in the internal or external program
memory. The EA

input is latched during
RESET and is “don’t care” after RESET (also
if the security bit is not set). This
implementation prevents reading internal
program code by switching from external
program memory to internal program memory
during a MOVC instruction or any other
instruction that uses immediate data.

Table 2 lists the access to the internal and
external program memory by the MOVC
instructions when the security bit has been
set to a logical “1”:

OSCILLATOR
CHARACTERISTICS

XTAL1 and XTAL2 are the input and output,
respectively, of an inverting amplifier. The
pins can be configured for use as an on-chip
oscillator, as shown in the Logic Symbol,
page 2.

To drive the device from an external clock
source, XTAL1 should be driven while XTAL2
is left unconnected. There are no
requirements on the duty cycle of the
external clock signal, because the input to
the internal clock circuitry is through a
divide-by-two flip-flop. However, minimum
and maximum high and low times specified in
the data sheet must be observed.

Reset

A reset is accomplished by holding the RST
pin high for at least two machine cycles
(24 oscillator periods), while the oscillator is
running. To insure a good power-on reset, the
RST pin must be high long enough to allow
the oscillator time to start up (normally a few
milliseconds) plus two machine cycles. At
power-on, the voltage on V

DD

and RST must
come up at the same time for a proper
start-up.

Power-on Reset (See Figure 1.)

When V

DD

is turned on, and provided its
rise-time does not exceed 10ms, an
automatic reset can be obtained by
connecting the RST pin to V

DD

via a 2.2µF
capacitor. When the power is switched on,
the voltage on the RST pin is equal to V

DD

minus the capacitor voltage, and decreases
from V

DD

as the capacitor charges through

the internal resistor (R

RST

) to ground. The

larger the capacitor, the more slowly V

RST

decreases. V

RST

must remain above the
lower threshold of the Schmitt trigger long
enough to effect a complete reset. The time
required is the oscillator start-up time, plus 2
machine cycles.

83CE654

V

DD

RST

R

RST

2.2µF

V

DD

Figure 1. Power-on Reset

Idle Mode

In the idle mode, the CPU puts itself to sleep
while all of the on-chip peripherals stay
active. The instruction to invoke the idle
mode is the last instruction executed in the
normal operating mode before the idle mode
is activated. The CPU contents, the on-chip
RAM, and all of the special function registers
remain intact during this mode. The idle
mode can be terminated either by any
enabled interrupt (at which time the process
is picked up at the interrupt service routine
and continued), or by a hardware reset which
starts the processor in the same manner as a
power-on reset.

Power-Down Mode

In the power-down mode, the oscillator is
stopped and the instruction to invoke
power-down is the last instruction executed.
Only the contents of the on-chip RAM are
preserved. A hardware reset is the only way

to terminate the power-down mode. the
control bits for the reduced power modes are
in the special function register PCON. Table 3
shows the state of the I/O ports during low
current operating modes.

Power Control Register PCON

These special modes are activated by
software via the Special Function Register
PCON. Its hardware address is 87H. PCON
is not bit addressable. The reset value of
PCON is (0x0x0000).

PCON
(87H)

SMOD – RFI – GF1 GF0 PD IDL

7 6 5 4 3 2 1 0

Bit Symbol Function

PCON.7 SMOD Double Baud rate bit.

When set to logic 1 the
baud rate is doubled when
Timer 1 is used to
generate baud rate, and
the Serial Port is used in

modes 1, 2 or 3.
PCON.6 – (reserved for future use*)
PCON.5 RFI When set to logic 1 the

toggling of ALE pin is

prohibited. This bit is

cleared on RESET.
PCON.4 – (reserved for future use*)
PCON.3 GF1 General purpose flag bit.
PCON.2 GF0 General purpose flag bit.
PCON.1 PD Power-down bit. Setting

this bit activates

Power-down mode.
PCON.0 IDL Idle mode bit. Setting this

bit activates the Idle

mode. If 1s are written to

PD and IDL at the same

time, PD takes

precedence.

NOTE:

* User software should not write 1s to

reserved bits. These bits may be used in
future 80C51 family products to invoke
new features. In that case, the reset or
inactive value of the new bit will be 0, and
its active value will be 1. The value read
from a reserved bit is indeterminate.

I2C Serial Communication—SIO1

The I2C serial port is identical to the I2C
serial port on the 8XC552. The operation of
this subsystem is described in detail in the
8XC552 section of this manual.

Note that in both the 83CE654 and the
8XC552 the I

2

C pins are alternate functions
to port pins P1.6 and P1.7. Because of this,
P1.6 and P1.7 on these parts do not have a
pull-up structure as found on the 80C51.
Therefore P1.6 and P1.7 have open drain
outputs on the 83CE654.