Philips 80cl31 DATASHEETS
INTEGRATED CIRCUITS
80CL31/80CL51
Low-voltage single-chip
8-bit microcontrollers
Product specification 1995 January
IC20 Data Handbook
Philips Semiconductors Product specification
80CL31/80CL51Low-voltage single-chip 8-bit microcontrollers
FEA TURES
• Full static 80C51 CPU
• 8-bit CPU, ROM, RAM, 1/0 in a single 40-lead DIL / mini-pack
• 4K x 8 ROM, expandable externally to 64K bytes
• 128 bytes RAM, expandable externally to 64K bytes
• Four 8-bit ports, 321/0 lines
• Two 16-bit timer / event counters
• External memory expandable up to 128K, external ROM up to
64K and / or RAM up to 64K
• On-chip oscillator suitable for RC, LC, quartz crystal or ceramic
resonator
• Thirteen source, thirteen vector interrupt structure with two priority
levels
• Full duplex serial port (UART)
• Enhanced architecture with:
– non-page oriented instructions
– direct addressing
– four eight byte RAM register banks
– stack depth up to 128 bytes
– multiply, divide, subtract and compare instructions
• Power-Down and IDLE instructions
• Wake-up via external interrupts at Port 1
• Single supply voltage of 1.8V to 6.0V (5.0V ±10% for P80C51)
• Frequency range of 0 to 16MHz (3.5MHz to 16MHz for P80C51)
• Very low current consumption
• Operating temperature range: -40 to +85
DESCRIPTION
The 80CL51 is manufactured in an advanced CMOS technology.
The instruction set of the 80CL51 is based on that of the 8051. The
80CL51 is a general purpose microcontroller especially suited for
battery-powered applications. The device has low power
consumption and a wide range of supply voltage. For emulation
purposes, the 85CL000 (Piggy-back version) with 256 bytes of RAM
is recommended. The 80CL51 has two software selectable modes
of reduced activity for further power reduction: Idle and Power-down.
The 80CL51 also functions as an arithmetic processor having
facilities for both binary and BCD arithmetic plus bit-handling
capabilities. The instruction set consists of over 100 instructions: 49
one-byte, 46 two-byte, and 16 three-byte.
The P80CL31 is the ROMless version of the P80CL51. P80C51 is a
5V version of the low voltage P80CL51.
The P80CL31 is the ROMless version of the P80CL51. P80C51 is a
5V version of the low voltage P80CL51.
o
C
PIN CONFIGURATIONS
/P1.0
INT2
INT3/P1.1
INT4
INT5/P1.3
INT6
INT7/P1.5
INT8/
INT9
RXD/DATA/P3.0
TXD/CLOCK/P3.1
INT0
INT1/
WR
/P1.2
/P1.4
P1.6
/P1.7
RST
/P3.2
P3.3
T0/P3.4
T1/P3.5
/P3.6
RD
/P3.7
XTAL2
XTAL1
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
PACKAGES
14
15
16
17
18
19
20
PLASTIC
DUAL
IN-LINE
SMALL
OUTLINE
AND
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
V
DD
P0.0/AD0
P0.1/AD1
P0.2/AD2
P0.3/AD3
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA
ALE
PSEN
P2.7/A15
P2.6/A14
P2.5/A13
P2.4/A12
P2.3/A11
P2.2/A10
P2.1/A9
P2.0/A8
P1.5/INT7
P1.6/INT8
P1.7/INT9
RST
P3.0/RXD
NC
P3.1/TXD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P1.4/INT6
P1.3/INT5
P1.2/INT4
P1.1/INT3
4041
424344
1
2
3
4
5
PLASTIC QUAD FLAT PACKAGE
6
7
8
9
10
11
12 13 14 15 16 17 18 19 20
XTAL2
XTAL1
P3.7/RD
P3.6/WR
DD
V
NC
P1.0/INT2
SS
V
P0.0/AD0
39 38 37 36 35 34
NC
P2.0/A8
P2.1/A9
P2.2/A10
P0.1/AD1
P0.2/AD2
2221
P2.3/A11
P0.3/AD3
33
32
31
30
29
28
27
26
25
24
23
P2.4/A12
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA
NC
ALE
PSEN
P2.7/A15
P2.6/A14
P2.5/A13
January 1995
2
Philips Semiconductors Product specification
AND PACKAGE
NUMBER
80CL31/80CL51Low-voltage single-chip 8-bit microcontrollers
ORDERING INFORMATION
PHILIPS PART ORDER
NUMBER PART MARKING
ROMless ROM ROMless ROM
P80CL31HFP P80CL51HFP P80CL31HFP N P80CL51HFP N
P80CL31HFT P80CL51HFT P80CL31HFTD P80CL51HFT D
P80CL31HFH
NOTE:
1. Parts ordered by the Philips North America part number will be marked with the Philips part marking.
P80CL51HFH P80CL31HFH B P80CL51HFH B
P80C51HFP P80C51HFP N
P80C51HFT P80C51HFT D
P80C51HFH P80C51HFHB
PHILIPS NORTH AMERICA
PART ORDER NUMBER
1
TEMPERATURE RANGE oC
–40 to +85;
40-lead Plastic Dual In-line Package (1.8V to 6V)
–40 to +85;
40-lead Plastic Small Outline Package (1.8V to 6V)
–40 to +85;
44-lead Plastic Quad Flat Package (1.8V to 6V)
–40 to +85;
40-lead Plastic Dual In-line Package (5.0V ±10%)
–40 to +85;
40-lead Plastic Small Outline Package (5.0V ±10%)
–40 to +85;
44-lead Plastic Quad Flat Package (5.0V ±10%)
DRAWING
SOT129-1
SOT158-1
SOT307-2
SOT129-1
SOT158-1
SOT307-2
January 1995
3
Philips Semiconductors Product specification
DESIGNATION
FUNCTION
ill
(I
alternative functions INT2 to INT9
80CL31/80CL51Low-voltage single-chip 8-bit microcontrollers
PIN DESCRIPTIONS
PIN
QFP DIP
40 1 P1.O/INT2
41 2 P1.1/lNT3
42 3 P1.2/lNT4
43 4 P1.3/INT5
44 5 P1.4/lNT6
1 6 P1.5/lNT7
2 7 P1.6/lNT8
3 8 P1.7/lNT9
4 9 RST Reset: A high level on this pin for two machine cycles while the oscillator is running resets the
5–13 10-17 Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 3 output buffers can
5 10 P3.0/RXD/data RXD/data: Serial port receiver data input (asynchronous)or data input/output (synchronous)
7 11 P3.1/TXD/clock TXD/clock: Serial port transmitter data output (asynchronous) or clock output (synchronous)
8 12 P3.2/lNT0 INT0: External interrupt 0.
9 13 P3.3/lNT1 INT1: External interrupt 1.
10 14 P3.4/T0 T0: Timer 0 external input.
11 15 P3.5/T1 T1: Timer 1 external input.
12 16 P3.6/WR WR: External data memory write strobe.
13 17 P3.7/RD RD: External data memory read strobe.
14 18 XTAL2 Crystal output: Output of the inverting amplifier of the oscillator. Left open when external clock is
15 19 XTAL1 Crystal input: Input to the inverting amplifier of the oscillator; also the input for an externally
16 20 Vss Ground: Circuit ground potential.
18-25 21-28 P2.0-P2.7 Port 2: Port 2 is an 8-bit bidirectional 1/0 port with internal pullups. Port 2 pins that have 1s written
26 29 PSEN Program store enable output: Read strobe to external program memory. When executing code
27 30 ALE Address Latch Enable: Output pulse for latching the low byte of the address during access to
29 31 EA External Access: When EA is held High the CPU executes out of internal program memory (un-
30-37 32-39 P0.0-P00.7 Port 0: Port 0 is an 8-bit open drain bidirectional I/O port. As an open drain output port it can sink 8
38 40 V
DD
Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pullups. Port 1 pins that have 1s written
to them are pulled HIGH by the internal pullups, and in that state can be used as inputs. The Port 1
output buffer can sink/source 4 LS TTL loads. As inputs, Port 1 pins that are externally pulled LOW
w
source current
device.
sink/source 4 LS TTL inputs. Port 3 pins that have 1s written to them are pulled HIGH by the
internal pull ups, and in that state can be used as inputs. As inputs, Port 3 pins that are externally
pulled LOW will source current (I
used.
Crystal input: Input to the inverting amplifier of the oscillator; also the input for an externally gen-
erated clock source.
generated clock source.
to them are pulled HIGH by the internal pullups, and in that state can be used as inputs. The Port 2
output buffer can sink/source 4 LS TTL loads.
Port 2 emits the high-order address byte during accesses to external memory that use 1 6-bit addresses (MOVX @DPTR). In this application it uses the strong internal pullups when emitting 1s.
During accesses to external memory that use 8-bit addresses (MOVX @Ri), Port 2 emits the contents of the P2 Special Function Register.
out of external program memory, PSEN is activated twice each machine cycle. However, during
each access to external data memory two PSEN activations are skipped.
external memory . ALE is emitted at a constant rate of 1/6 of the oscillator frequency, and may be
used for external timing or clocking purposes.
less the program counter exceeds 0FFFH). Holding EA LOW forces the CPU to execute out of
external memory regardless of the value of the program counter.
LS TTL loads. Port 0 pins that have 1s written to them float, and in that state will function as high
impedance inputs. Port 0 is also the multiplexed low order address and data bus during access to
external memory . In this application it uses strong internal pull-ups when emitting logic 1s.
Power supply.
in the characteristics) due to the internal pullups. Port 1 also serves the
lL
.
in the characteristics) due to the internal pull ups.
lL
January 1995
4
Philips Semiconductors Product specification
80CL31/80CL51Low-voltage single-chip 8-bit microcontrollers
BLOCK DIAGRAM
FREQUENNCY REFERENCE
XTAL2 XTAL1
OSCILLATOR
AND TIMING
CPU
10 3
INTERNAL
INTERRUPTS
EXTERNAL ENTERRUPTS
1. Pins shared with parallels ports pins.
1
PROGRAM
MEMORY
(4K BY 8 ROM)
64K BYTE BUS
EXPANSION
CONTROL
CONTROL
DATA MEMORY
(128 BY 8 RAM)
80CL51
PROGRAMMABLE
PARALLEL PORTS
ADDRESS/DATA BUS
I/O
I/O PINS
COUNTER
T0 T1
TWO 16-BIT TIMER/
EVENT COUNTERS
PROGRAMMABLE
SERIAL PORT,
FULL DUPLEX UART,
SYNCHRONOUS
RXD TXD
1
SHIFT
(1)
FUNCTIONAL DIAGRAM
ALTERNATIVE
FUNCTIONS
RxD/data
TxD/clock
INT0
INT1
T0
T1
WR
RD
PORT 3
XTAL1
XTAL2
PSEN
ALE
EA
V
DD
V
RST
SS
PORT 0
PORT 1
PORT 2
ADDRESS AND
DATA BUS
INT2/INT9
ADDRESS BUS
January 1995
5
Philips Semiconductors Product specification
80CL31/80CL51Low-voltage single-chip 8-bit microcontrollers
1.0 FUNCTIONAL DESCRIPTION
General
The 80CL51 is a stand-alone high-performance CMOS
microcontroller designed for use in real-time applications such as
instrumentation, industrial control, intelligent computer peripherals
and consumer products.
The device provides hardware features, architectural enhancements
and new instructions to function as a controller for applications
requiring up to 64K bytes of program memory and/or up to 64K
bytes of data storage.
The 80CL51 contains a non-volatile 4K byte × 8 read-only program
memory; a static 128 byte × 8 read/write data memory; 32 1/0 lines;
two 16-bit timer/event counters; a thirteen- source two priority-level,
nested interrupt structure and on-chip oscillator and timing circuit.
The device has two software selectable modes of reduced activity
for power reduction: IDLE and Power-down. The Idle mode freezes
the CPU while allowing the RAM, timers, serial I/O and interrupt
system to continue functioning. The Power-down mode saves the
RAM contents but freezes the oscillator causing all other chip
functions to be inoperative.
The P80C51 is a 5V version of the low voltage microcontroller
P80CL51. Hereafter the generic term P80CL51 will be used for the
functional description of both types. The special features of the
P80C51 are handled in chapter 1.9.
CPU timing
A machine cycle consists of a sequence of 6 states. Each state time
lasts for two oscillator periods, thus a machine cycle takes 12
oscillator periods or 1µs if the oscillator frequency is 12MHz.
1.1 Memory organization
The 80CL51 has a 4K Program Memory (ROM) plus 128 bytes of
Data Memory (RAM) on board. The device has separate address
spaces for Program and Data Memory (see Memory Map). Using
Ports P0 and P2, the 80CL51 can address up to 64K bytes of
external memory . The CPU generates both read and write signals
(RD and WR) for external Data Memory accesses, and the read
strobe (PSEN) for external Program Memory.
1.1.1 Program Memory
The 80CL51 contains 4K bytes of internal ROM. After reset the CPU
begins execution at location 0000H. The lower 4K bytes of Program
Memory can be implemented in either on- chip ROM or external
Memory. If the EA pin is strapped to V
, then program memory
DD
fetches from addresses 000H through 0FFFH are directed to the
internal ROM. Fetches from addresses 1000H through FFFFH are
directed to external ROM. Program counter values greater than
0FFFH are automatically addressed to external memory regardless
of the state of the EA pin.
1.1.2 Data Memory
The 80CL51 contains 128 bytes of internal RAM and 25 Special
Function Registers (SFR). The Memory Map below shows the
internal Data Memory space divided into the Lower 128, the Upper
128, and the SFR space.
The lower 128 bytes of the internal RAM are organized as mapped
in Figure 1. The lowest 32 bytes are grouped into 4 banks of 8
registers. Program instructions refer to these registers R0 through
R7. Two bits in the Program Status Word select which register bank
is in use. The next 16 bytes above the register banks form a block of
bit-addressable memory space. The 128 bits in this area can be
directly addressed by the single-bit manipulation instructions. The
remaining registers (30H to 7FH) are directly and indirectly byte
addressable.
1.1.3 Special Function Registers
The upper 128 bytes are the address locations of the SFRs. Figure
2 shows the Special Function Register (SFR) space. SFRs include
the port latches, timers, peripheral control, serial I/O registers, etc.
These registers can only be accessed by direct addressing. There
are 128 addressable locations in the SFR address space (SFRs with
addresses divisible by eight).
1.1.4 Addressing
The 80CL51 has five methods for addressing source operands:
– Register
– Direct
– Register-lndirect
– Immediate
– Base-Register-plus Index-Register-indirect
MEMORY MAP
January 1995
4095
64K
4096
INTERNAL
= 1)
(EA
EXTERNAL
4095
INTERNAL
= 0)
(EA
225
127
0
INTERNAL
DATA RAM
INTERNAL DATA MEMORYPROGRAM MEMORY
6
OVERLAPPED
SPACE
SPECIAL
FUNCTION
REGISTERS
64K
0
EXTERNAL
DATA RAM
Philips Semiconductors Product specification
80CL31/80CL51Low-voltage single-chip 8-bit microcontrollers
7FH
2FH
BIT-ADDRESSABLESPACE
(BIT ADDRESSES 0-7F)
20H
R7
I
I
R0
R7
I
I
R0
R7
I
I
R0
R7
I
I
R0
1FH
18H
17H
10H
0FH
08H
07H
4 BANKS OF 8 REGISTERS
(R0-R)
0
Figure 1. The Lower 128 Bytes of Internal RAM
The first three methods can be used for addressing destination
operands. Most instructions have a “destination/source” filed that
specifies data type, addressing methods and operands involved. For
operations other than MOVs, the destination operand is also a
source operand.
Access to memory addressing is as follows:
– Registers in one of the four register banks through register,
direct or indirect.
– Internal RAM (128 bytes) through direct or register-indirect.
– Special Function Register through Direct.
– External data memory through Register-lndirect
– Program memory look-up tables through Base-Register-Plus
Index-Register-Indirect.
1.2 I/O Facilities
1.2.1 Ports
The 80CL51 has 32 I/O lines treated as 32 individually addressable
bits or as four parallel 8- bit addressable ports. Port 0, 1, 2 and 3
perform the following alternate functions:
Port 0: provides the multiplexed low-order address and data bus
for expanding the device with standard memories and
peripherals.
Port 1: provides the inputs for the external interrupts INT2/lNT9.
Port 2: provides the high-order address when expanding the
device with external program or data memory.
Port 3: pins can be configured individually to provide:
(1) external interrupt request inputs
(2) counter input
(3) control signals to read and write to external memories
(4) UART input and output
To enable a Port 3 pin alternate function, the Port 3 bit latch in its
SFR must contain a logic 1.
Each port consists of a latch (Special Function Registers P0 to P3),
an output driver and an input buffer. Ports 1,2,3 have internal pull
ups. Figure 3(a) shows that the strong transistor p1 is turned on for
only 2 oscillator periods after a 0-to-1 transition in the port latch.
When on, it turns on p3 (a weak pull up) through the inverter. This
inverter and p3 form a latch which hold the 1. In Port 0 the pull up p1
is only on when emitting 1s for external memory access. Writing a 1
to a Port 0 bit latch leaves both output transistors switched off so the
pin can be used as a high-impedance input.
1.2.2 Port Options
The pins of port 1, port 2, and port 3 may be individually configured
with one of the following options (see Figure 3):
Option 1: Standard Port; quasi-bidirectional I/O with pull up. The
strong booster pull up p1 is turned on for two oscillator
periods after a 0-to-1 transition in the port latch (see
Figure 3(a)).
Option 2: Open drain; quasi-bidirectional I/O with n-channel open
drain output. Use as an output requires the connection of
an external pull up resistor (see Figure 3(c)).
Option 3: Push-Pull; output with drive capability in both polarities.
Under this option, pins can only be used as outputs. See
Figure 3(b).
January 1995
7
Philips Semiconductors Product specification
80CL31/80CL51Low-voltage single-chip 8-bit microcontrollers
DIRECT
REGISTER
MNEMONIC
BIT ADDRESS
BYTE ADDRESS
(HEX)
IP1
IX1
IEN1
ACC
PSW
IRQ1
IP0
P3
IEN0
P2
S0BUF
S0CON
FF FE FD FC FB FA F9 F8
F7 F6 F5 F4 F3 F2 F1 F0
B
EF EE ED EC EB EA E9 E8
E7 E6 E5 E4 E3 E2 E1 E0
D7 D6 D5 D4 D3 D2 D1 D0
C7 C6 C5 C4 C3 C2 C1 C0
BD BC BB BA B9 B8
B7 B6 B5 B4 B3 B2 B1 B0
AF AE AD AC AB AA A9 A8
A7 A6 A5 A4 A3 A2 A1 A0
9F 9E 9D 9C 9B 9A 99 98
F8H
F0H
E9H
E8H
EOH
D0H
C0H
B8H
B0H
A8H
A0H
99H
98H
SFRs CONTAINING DIRECTLY
ADDRESSABLE BITS
TH1
TH0
TL1
TL0
TMOD
TCON
PCON
DPH
DPL
97 96 95 94 93 92 91 90
P1
8F 8E 8D 8C 8B 8A 89 88
SP
87 86 85 84 83 82 81 80
P0
Figure 2. Special Function Registers
90H
8DH
8CH
8BH
8AH
89H
88H
87H
83H
82H
81H
80H
January 1995
8
Philips Semiconductors Product specification
80CL31/80CL51Low-voltage single-chip 8-bit microcontrollers
STRONG PULL UP
2 OSCILLATOR PERIODS
P2
P1
FROM
PORT
LATCH
(a)
Q
INPUT DATA
INPUT BUFFER
READ PORT PIN
n
+5V
P3
I/O PIN
STRONG PULL UP
(b)
(c)
FROM
PORT
LATCH
Q
FROM
PORT
LATCH
Q
INPUT DATA
READ PORT PIN
Figure 3. Ports
The definition of port options for port 0 is slightly different. T wo
cases have to be examined. First, accesses to external memory
(EA=0 or access above the built -in memory boundary), second, I/O
accesses.
External Memory Accesses
Option 1: True 0 and 1 are written as address to the external
memory (strong pull up is used).
Option 2: An external pull up resistor is needed for external
accesses.
Option 3: Not allowed for external memory access as the port can
only be used as output.
I/O Accesses
Option 1: When writing a 1 to the port-latch, the strong pull up p1
will be on for 2 oscillator periods. No weak pull up exists.
Without an external pull up, this option can be used as a
high-impedance input.
+5V
P1
I/O PIN
n
+5V
EXT.
PULL UP
I/O PIN
n
INPUT BUFFER
Option 2: Open drain; quasi-bidirectional I/O with n-channel open
drain output. Use as an output requires the connection of
an external pull up resistor (see Figure 3(c)).
Option 3: Push-Pull; output with drive capability in both polarities.
Under this option, pins can only be used as outputs.
Individual mask selection of the post-reset state is available on any
of the above pins. Make your selection by appending “S” or “R” to
option 1, 2, or 3 above (e.g. 1 S for a standard I/O to be set after
RESET or 2R for an open-drain I/O to be reset after RESET).
1.3 Timer/event counter
The 80CL51 contains two 16-bit Timer/Counter registers, T imer 0
and Timer 1, which can perform the following functions:
– Measure time intervals and pulse durations
– Count events
– Generate interrupts requests
January 1995
9
Philips Semiconductors Product specification
80CL31/80CL51Low-voltage single-chip 8-bit microcontrollers
Timer 0 and Timer 1 can be independently programmed to operate
as follows:
Mode 0 - 8-bit timer or counter with divide-by-32 prescaler
1.4 Idle and Power-down operation
Idle mode operation permits the interrupt, serial port and timer
blocks to continue functioning while the clock to the CPU is halted.
The following functions remain active during Idle mode:
Mode 1 - 16-bit time-interval or event counter
Mode 2 - 8-bit time interval or event counter with automatic reload
upon overflow
Mode 3 - Timer 0 establishes TL0 and TH0 as two separate
counters.
In the “Timer” function, the register is incremented every machine
cycle. Since a machine cycle consists of 12 oscillator periods, the
count rate is 1/12 of the oscillator frequency.
In the “Counter” function, the register is incremented in response to
a 1-to-0 transition. Since it takes 2 machine cycles (24 oscillator
The Power-down operation freezes the oscillator. The Power-down
mode can only be activated by setting the PD bit in the PCON
register.
1.4.1 Power control register
Power-down and Idle modes are activated by software via the
Special Function Register PCON. Its hardware address is 87H.
PCON is byte addressable only.
periods) to recognize a 1-to-0 transition, the maximum count rate is
1/24 of the oscillator frequency. To ensure a given level is sampled,
it should be held for at least one full machine cycle.
PCON
BIT POSITION FUNCTION
SMOD PCON.7
PCON.4-PCON.6
Double baud-rate bit, see description of the UART, chapter 1.5.
(reserved)
GF1 PCON.3 General purpose flag bit
GFO PCON.2 General purpose flag bit
PD PCON.1 Power-down activation bit
IDL PCON.0 Idle mode activation bit
– Timer 0, Timer 1
– UART
– External interrupt
XTAL2
OSCILLATOR
PD
XTAL1
CLOCK
GENERATOR
Figure 4. Idle and Power-down Hardware
IDL
INPUTS
SERIAL PORTS
TIMER BLOCKS
CPU
January 1995
10
Philips Semiconductors Product specification
80CL31/80CL51Low-voltage single-chip 8-bit microcontrollers
1.4.2 Power-down mode
The instruction setting PCON.1 is the last executed prior to going
into the Power-down mode. In Power-down mode the oscillator is
stopped. The contents of the on-chip RAM and SFRs are preserved.
The port pins output the values held by their respective SFRs. ALE
and PSEN are held LOW.
In the Power-down mode V
may be reduced to minimize power
DD
consumption. However, the supply voltage must not be reduced until
Power-down mode is active, and must be restored before the
hardware reset is applied and frees the oscillator. Reset must be
held active until the oscillator has restarted and stabilized.
The wake-up operation after power-down in this controller has two
basic approaches:
1.4.2.1 Wake-up using INT2 to INT9
If INT2 to INT9 are enabled, the 80CL51 can be awakened from
power-down mode with the external interrupts. To ensure that the
oscillator is stable before the controller restarts, the internal clock
will remain inactive for 1536 oscillator periods. This is controlled by
an on-chip delay counter.
1.4.2.2 Wake-up using RESET
To wake-up the 80CL51 the RESET pin has to be kept HIGH for a
minimum of 24 oscillator periods. The on-chip delay counter is
inactive. The user has to ensure that the oscillator is stable before
any operation is attempted. Figure 5 illustrates the two possibilities
for wake-up.
1.4.3 Idle mode
The instruction that sets PCON.0 is the last instruction executed
before going into Idle mode. Once in the Idle mode, the internal
clock is gated away from the CPU, but not from the Interrupt, Timer
and Serial port functions. The CPU status is preserved along with
the Stack Pointer, Program Counter, Program Status Word and
Accumulator. The RAM and all other registers maintain their data
during Idle mode. The port pins retain the logical states they held at
Idle mode activation. ALE and PSEN hold at the logic HIGH level.
There are two methods used to terminate the Idle mode. Activation
of any enabled interrupt will cause PCON to be cleared by
hardware, terminating Idle mode. The interrupt is serviced, and
following the instruction RETI, the next instruction to be executed
will be the one following the instruction that put the device in the Idle
mode.
Flag bits GF0 and GF1 may be used to determine whether the
interrupt was received during normal execution or Idle mode. For
example, the instruction that writes to PCON.0 can also set or clear
one or both flag bits. When Idle mode is terminated by an interrupt,
the service routine can examine the status of the flag bits.
The second method of terminating the Idle mode is with an external
hardware reset. Since the oscillator is still running, the hardware
reset is required to be active for only two machine cycles to
complete the reset operation.
Reset redefines all SFRs, but does not affect the on-chip RAM.
The status of the external pins during Idle and Power-down mode is
shown in Table 1. If the Power-down mode is activated while
accessing external memory, port data held in the Special Function
Register P2 is restored to Port 2. If the data is a logic 1, the port pin
is held HIGH during the Power-down mode by the strong pull up
transistor p1 (see Figure 3(a)).
Table 1. Status of the External Pins During Idle and Power-down Mode
MODE MEMORY ALE PSEN PORT 0 PORT 1 PORT 2 PORT 3
Idle internal 1 1 Port Data Port Data Port Data Port Data
Idle external 1 1 Floating Port Data Address Port Data
Power-down internal 0 0 Port Data Port Data Port Data Port Data
Power-down external 0 0 Floating Port Data Port Data Port Data
POWER-DOWN
RESET-PIN
EXTERNAL INTERRUPT
OSCILLATOR
DELAY COUNTER
1536 PERIODS
Figure 5. Wake-up Operation
>24 PERIODS
January 1995
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Philips Semiconductors Product specification
80CL31/80CL51Low-voltage single-chip 8-bit microcontrollers
1.5 Standard serial interface SI0: UART
This serial port is full duplex, meaning it can transmit and receive
simultaneously. It is also receive-buffered, meaning it can
commence reception of a second byte before a previously received
byte has been read from the register. (However, if the first byte still
hasn’t been read by the time reception of the second byte is
complete, one of the bytes will be lost). The serial port receive and
transmit registers are both accessed at Special Function Register
S0BUF. Writing to S0BUF loads the transmit register, and reading
S0BUF loads the transmit register, and reading S0BUF accesses a
physically separate receive register.
The serial port can operate in 4 modes:
Mode 0: Serial data enters and exits through RxD. TxD outputs the
shift clock. 8 bits are transmitted/ received (LSB first). The
baud is fixed at 1/12 the oscillator frequency.
Mode 1: 10 bits are transmitted (through TxD) or received (through
RxD): a start bit (0), 8 data bits (LSB first), and a stop bit
(1). On receive, the stop bit goes into RB8 in Special
Function Register SCON. The baud rate is variable.
Mode 2: 11 bits are transmitted (through TxD) or received (through
RxD): start bit (0), 8 data bits (LSB first), a programmable
9th data bit, and a stop bit (1). On Transmit, the 9th data
bit (TB8 in SCON) can be assigned the value of 0 or 1.
Or, for example, the parity bit (P, in the PSW) could be
moved into TB8. On receive, the 9th data bit goes into
RB8 in Special Function Register SCON, while the stop
bit is ignored. The baud rate is programmable to either
1/32 or 1/64 the oscillator frequency.
Mode 3: 11 bits are transmitted (through TxD) or received (through
RxD): a start bit (0), 8 data bits (LSB first), a
programmable 9th data bit and a stop bit (1). In fact,
Mode 3 is the same as Mode 2 in all respects except
baud rate. The baud rate in Mode 3 is variable.
In all four modes, transmission is initiated by any instruction that
uses S0BUF as a destination register. Reception is initiated in Mode
0 by the condition Rl = 0 and REN = 1. Reception is initiated in the
other modes by the incoming start bit if REN = 1.
1.5.1 Multiprocessor communications
Modes 2 and 3 have a special provision for multiprocessor
communications. In these modes, 9 data bits are received. The 9th
one goes into RB8. Then comes a stop bit. The port can be
programmed such that when the stop bit is received, the serial port
interrupt will be activated only if RB8 = 1. This feature is enabled by
setting bit SM2 in SCON. A way to use this feature in multiprocessor
systems is as follows:
When the master processor wants to transmit a block of data to one
of several slaves, it first sends out an address byte which identifies
the target slave. An address byte differs from a data byte in that the
9th bit is 1 in an address byte and 0 in a data byte. With SM2 = 1, no
slave will be interrupted by a data byte. An address byte, however,
will interrupt all slaves, so that each slave can examine the received
byte and see if it is being addressed. The addressed slave will clear
its SM2 bit and prepare to receive the data bytes that will be coming.
The slaves that weren’t being addressed leave their SM2s set and
go on about their business, ignoring the coming data bytes.
SM2 has no effect in Mode 0, and in Mode 1 can be used to check
the validity of the stop bit. In a Mode 1 reception, if SM2 = 1, the
receive interrupt will not be activated unless a valid stop bit is
received.
1.5.2 Serial port control register
The serial port control and status register is the Special Function
Register S0CON, shown in Figure 6. The register contains not only
the mode selection bits, but also the 9th data bit for transmit and
receive (TB8 and RB8), and the serial port interrupt bits (T1 and
R1). See next page.
Baud Rates
The baud rate in Mode 0 is fixed: Mode 0 Baud Rate = Oscillator
Frequency /12. The baud rate in Mode 2 depends on the value of bit
SMOD in Special Function Register PCON. If SMOD = 0 (which is
the value on reset), the baud rate is 1/64 the oscillator frequency. If
SMOD = 1, the baud rate is 1/32 the oscillator frequency.
SMOD
Mode 2 Baud Rate = (2
The baud rates in Modes 1 and 3 are determined by the Timer 1
overflow rate.
Using Timer 1 to generate baud rates
When Timer 1 is used as the baud rate generator , the baud rates in
Modes 1 and 3 are determined by the Timer 1 overflow rate and the
value of SMOD as follows:
SMOD
/32)(Timer 1 Overflow Rate)
(2
The Timer 1 interrupt should be disabled in this application. The
Timer itself can be configured for either “timer” or “counter”
operation, and in any of its 3 running modes. In the most typical
applications, it is configured for “timer operation, in the auto-reload
mode (high nibble of TMOD = 0010B). In that case the baud rate is
given by the formula:
Mode 1, 3 Baud Rate =
SMOD
{(2
One can achieve very low baud rates with Timer 1 by leaving the
Timer 1 interrupt enabled, and configuring this Timer to run as a
16-bit timer (high nibble of TMOD = 0001B), and using the Timer 1
interrupt to do a 16-bit software reload. Table 2 lists various
commonly used baud rates and how they can be obtained from
Timer 1.
More about Mode 0
Figure 7 shows a simplified functional diagram of the serial port in
Mode 0, and associated timing. Transmission is initiated by any
instruction that uses S0BUF as a destination register. The “write to
S0BUF” signal at S6P2 also loads a 1 into the 9th position of the
transmit shift register and tells the TX Control block to commence a
transmission. The internal timing is such that the one full machine
cycle will elapse between “write to S0BUF”, and activation of SEND.
SEND enables the output of the shift register to the alternate output
function line of P3.0 and also enables SHIFT CLOCK to the
alternate output function line of P3.1. SHIFT CLOCK is low during
S3, S4, and S5 of every machine cycle, and high during S6, S1 and
S2. At S6P2 of every machine cycle in which SEND is active, the
contents of the transmit shift are shifted to the right one position.
As data bits shift out to the right, zeros come in from the left. When
the MSB of the data byte is at the output position of the shift register,
then the 1 that was initially loaded into the 9th position is just to the
left of the MSB, and all positions to the left of that contain zeros.
This condition flags the TX Control block to do one last shift and
then deactivate SEND and set T1. Both of these actions occur at
S1P1 of the 10th machine cycle after “write to S0BUF”.
Reception is initiated by the condition REN = 1 and R1 = 0. At S6P2
of the next machine cycle, the RX Control unit writes the bits
11111110 to the receive shift register, and in the next clock phase
activates RECEIVE.
/32) (Oscillator Frequency)} / {12 (256 - (TH 1 )}
/64)(Oscillator Frequency)
January 1995
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