Philips 80C562, 83C562 Technical data
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INTEGRATED CIRCUITS
80C562/83C562
Single-chip 8-bit microcontroller
Product specification 1992 Jan 08
IC20 Data Handbook
Philips Semiconductors Product specification
80C562/83C562Single-chip 8-bit microcontroller
Single-chip 8-bit microcontroller with 8-bit A/D, capture/compare timer, high-speed outputs, PWM
DESCRIPTION
The 80C562/83C562 (hereafter generically
referred to as 8XC562) Single-Chip 8-Bit
Microcontroller is manufactured in an
advanced CMOS process and is a derivative
of the 80C51 microcontroller family. The
83C562/83C562 has the same instruction set
as the 80C51.
The 8XC562 contains a non-volatile 256 × 8
read-only program memory, a volatile 256 × 8
read/write data memory (83C562) (the
80C562 is ROMless), a volatile 256 × 8
read/write data memory, six 8-bit I/O ports,
two 16-bit timer/event counters (identical to
the timers of the 80C51), an additional 16-bit
timer coupled to capture and compare
latches, a 15-source, two-priority-level,
nested interrupt structure, an 8-input ADC,
two pulse width modulated outputs, standard
80C51 UART, a “watchdog” timer and on-chip
oscillator and timing circuits. For systems that
require extra capability , the 83C562 can be
expanded using standard TTL compatible
memories and logic.
The device also functions as an arithmetic
processor having facilities for both binary and
BCD arithmetic plus bit-handling capabilities.
The instruction set consists of over 100
instructions: 49 one-byte, 45 two-byte and 17
three-byte. With a 12MHz crystal, 58% of the
instructions are executed in 1µs and 40% in
2µs. Multiply and divide instructions require
4µs.
FEA TURES
•80C51 instruction set
•8k × 8 ROM expandable externally to
64k bytes
•256 × 8 RAM, expandable externally to
64k bytes
•Two standard 16-bit timer/counters
•An additional 16-bit timer/counter coupled
to four capture registers and three compare
registers
•Capable of producing eight synchronized,
timed outputs
•An 8-bit ADC with eight multiplexed analog
inputs
•Two 8-bit resolution, pulse width modulated
outputs
•Five 8-bit I/O ports plus one 8-bit input port
shared with analog inputs
•Full-duplex UART compatible with the
standard 80C51
•On-chip watchdog timer
•Three temperature ranges
– 0 to +70°C
– –40 to +85°C
– –40 to +125°C
PIN CONFIGURATION
9161
10
PLASTIC
LEADED
CHIP CARRIER
26
Pin Function
1 P5.0/ADC0
2V
DD
3 STADC
4 PWM0
5 PWM1
6EW
7 P4.0/CMSR0
8 P4.1/CMSR1
9 P4.2/CMSR2
10 P4.3/CMSR3
11 P4.4/CMSR4
12 P4.5/CMSR5
13 P4.6/CMT0
14 P4.7/CMT1
15 RST
16 P1.0/CT0I
17 P1.1/CT1I
18 P1.2/CT2I
19 P1.3/CT3I
20 P1.4/T2
21 P1.5/RT2
22 P1.6
23 P1.7
24 P3.0/RxD
25 P3.1/TxD
26 P3.2/INT0
27 P3.3/INT1
28 P3.4/T0
29 P3.5/T1
30 P3.6/WR
31 P3.7/RD
32 NC
33 NC
34 XTAL2
Pin Function
35 XTAL1
36 V
37 V
38 NC
39 P2.0/A08
40 P2.1/A09
41 P2.2/A10
42 P2.3/A11
43 P2.4/A12
44 P2.5/A13
45 P2.6/A14
46 P2.7/A15
47 PSEN
48 ALE
49 EA
50 P0.7/AD7
51 P0.6/AD6
52 P0.5/AD5
53 P0.4/AD4
54 P0.3/AD3
55 P0.2/AD2
56 P0.1/AD1
57 P0.0/AD0
58 AVref–
59 AVref+
60 AV
61 AV
62 P5.7/ADC7
63 P5.6/ADC6
64 P5.5/ADC5
65 P5.4/ADC4
66 P5.3/ADC3
67 P5.2/ADC2
68 P5.1/ADC1
60
44
4327
SS
SS
SS
DD
SU00224
1992 Jan 08 853–1463 05128
2
Philips Semiconductors Product specification
80C562/83C562Single-chip 8-bit microcontroller
ORDERING INFORMATION
PHILIPS PART
ORDER NUMBER
PART MARKING
PHILIPS NORTH AMERICA
PART ORDER NUMBER
Drawing
ROMless ROM ROMless ROM
PCB80C562-
WP
16
PCB83C562-
WP
/xxx
16
S80C562-4A68 S83C562-4A68 SOT188 S87C552-4A682SOT188-3
Number
EPROM
S87C552-4K6821473A
PCF80C562-
WP
12
PCF83C562-
WP
/xxx
12
S80C562-2A68 S83C562-2A68 SOT188 S87C552-5A682SOT188-3 –40 to +85, Plastic
S87C552-5K6821473A
PCA80C562-
WP
12
PCA83C562-
WP
/xxx
12
S80C562-6A68 S83C562-6A68 SOT188 –40 to +125, Plastic
NOTES:
1. 80C562 and 83C562 frequency range is 1.2MHz–12MHz or 1.2MHz–16MHz.
2. 87C552 frequency range is 3.5MHz–16MHz. For full specification, see the 87C552 data sheets.
3. xxx denotes the ROM code number.
Drawing
Number
TEMPERATURE
RANGE °C
AND PACKAGE FREQ
0 to +70, Plastic
Leaded Chip Carrier
0 to +70, Plastic
Leaded Chip Carrier
w/Window
Leaded Chip
Carrier
–40 to +85, Plastic
Leaded Chip Carrier
w/Window
Leaded Chip Carrier
MHz
16
16
12
12
12
LOGIC SYMBOL
ADC0-7
CMSR0-5
CMT0
CMT1
V
SS
V
DD
XTAL1
XTAL2
EA
ALE
PSEN
AV
SS
AV
DD
AVref+
AVref–
STADC
PWM0
PWM1
RST
EW
LOW ORDER
ADDRESS AND
PORT 0
CT0I
CT1I
CT2I
CT3I
T2
PORT 1PORT 2PORT 3
RT2
PORT 5
PORT 4
RxD
TxD
INT0
INT1
T0
T1
WR
RD
ADDRESS AND
DATA BUS
HIGH ORDER
DATA BUS
1992 Jan 08
SU00225
3
Philips Semiconductors Product specification
80C562/83C562Single-chip 8-bit microcontroller
BLOCK DIAGRAM
XTAL1
XTAL2
EA
ALE
PSEN
3
3
0
2
WR
RD
AD0–7
A8–15
T0 T1 INT0 INT1
3 3 3 3
T0, T1
TWO 16-BIT
TIMER/EVENT
COUNTERS
80C51 CORE
PARALLEL I/O
PORTS AND
EXTERNAL BUS
EXCLUDING
ROM/RAM
CPU
SERIAL
UART
PORT
V
DD
PROGRAM
MEMORY
8k x 8 ROM
(83C562)
8-BIT
PORT
V
8-BIT INTERNAL BUS
16
FOUR
16-BIT
CAPTURE
LATCHES
SS
DATA
MEMORY
256 x 8 RAM
16-BIT
TIMER/
EVENT
COUNTERS
PWM0 PWM1
DUAL
PWM
T2
16
COMPARATORS
REGISTERS
T2
16-BIT
WITH
AV
SS
AV
DD
COMPARATOR
AV
REF
–+
STADC
ADC
OUTPUT
SELECTION
ADC0–7
5
T3
WATCHDOG
TIMER
P0 P1 P2 P3 TxD RxD P5 P4 CT0I–CT3I T2 RT2 CMSR0–CMSR5
ALTERNATE FUNCTION OF PORT 0
0
1
ALTERNATE FUNCTION OF PORT 1
2
ALTERNATE FUNCTION OF PORT 2
3 3
3
ALTERNATE FUNCTION OF PORT 3
4
ALTERNATE FUNCTION OF PORT 4
5
ALTERNATE FUNCTION OF PORT 5
1 1 1 4
CMT0, CMT1
RST EW
SU00226
1992 Jan 08
4
Philips Semiconductors Product specification
80C562/83C562Single-chip 8-bit microcontroller
PIN DESCRIPTION
MNEMONIC PIN NO. TYPE NAME AND FUNCTION
V
DD
STADC 3 I Start ADC Operation: Input starting analog to digital conversion (ADC operation can also be started
PWM0 4 O Pulse Width Modulation: Output 0.
PWM1 5 O Pulse Width Modulation: Output 1.
EW 6 I Enable Watchdog Timer: Enable for T3 watchdog timer and disable power-down mode.
P0.0–P0.7 57–50 I/O Port 0: Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written to them float
P1.0–P1.7 16–23 I/O Port 1: 8-bit I/O port. Alternate functions include:
P2.0–P2.7 39–46 I/O Port 2: 8-bit quasi-bidirectional I/O port.
P3.0–P3.7 24–31 I/O Port 3: 8-bit quasi-bidirectional I/O port. Alternate functions include:
P4.0–P4.7 7–14 I/O Port 4: 8-bit quasi-bidirectional I/O port. Alternate functions include:
P5.0–P5.7 68–62,
RST 15 I/O Reset: Input to reset the 87C552. It also provides a reset pulse as output when timer T3 overflows.
XTAL1 35 I Crystal Input 1: Input to the inverting amplifier that forms the oscillator, and input to the internal clock
XTAL2 34 O Crystal Input 2: Output of the inverting amplifier that forms the oscillator. Left open–circuit when an
V
SS
PSEN 47 O Program Store Enable: Active-low read strobe to external program memory.
ALE 48 O Address Latch Enable: Latches the low byte of the address during accesses to external memory. It is
EA 49 I External Access: When EA is held at TTL level high, the CPU executes out of the internal program
AV
REF–
AV
REF+
AV
SS
AV
DD
NOTE:
1. To avoid “latch-up” effect at power-on, the voltage on any pin at any time must not be higher or lower than V
respectively.
2 I Digital Power Supply: +5V power supply pin during normal operation, idle and power-down mode.
by software).
and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data
bus during accesses to external program and data memory. In this application it uses strong internal
pull-ups when emitting 1s.
16–23 I/O (P1.0–P1.7): Quasi-bidirectional port pins.
16–19 I/O CT0I–CT3I (P1.0–P1.3): Capture timer input signals for timer T2.
20 I T2 (P1.4): T2 event input
21 I RT2 (P1.5): T2 timer reset signal. Rising edge triggered.
Alternate function: High-order address byte for external memory (A08–A15).
24 RxD(P3.0): Serial input port.
25 TxD (P3.1): Serial output port.
26 INT0 (P3.2): External interrupt.
27 INT1 (P3.3): External interrupt.
28 T0 (P3.4): Timer 0 external input.
29 T1 (P3.5): Timer 1 external input.
30 WR (P3.6): External data memory write strobe.
31 RD (P3.7): External data memory read strobe.
7–12 O CMSR0–CMSR5 (P4.0–P4.5): Timer T2 compare and set/reset outputs on a match with timer T2.
13, 14 O CMT0, CMT1 (P4.6, P4.7): Timer T2 compare and toggle outputs on a match with timer T2.
I Port 5: 8-bit input port.
1
ADC0–ADC7 (P5.0–P5.7): Alternate function: Eight input channels to ADC.
generator. Receives the external clock signal when an external oscillator is used.
external clock is used.
36, 37 I Digital ground.
activated every six oscillator periods. During an external data memory access, one ALE pulse is
skipped. ALE can drive up to eight LS TTL inputs and handles CMOS inputs without an external
pull-up.
ROM provided the program counter is less than 8192. When EA
executes out of external program memory. EA
is not allowed to float.
is held at TTL low level, the CPU
58 I Analog to Digital Conversion Reference Resistor: Low-end.
59 I Analog to Digital Conversion Reference Resistor: High-end.
60 I Analog Ground
61 I Analog Power Supply
+0.5V or VSS – 0.5V,
DD
1992 Jan 08
5
Philips Semiconductors Product specification
80C562/83C562Single-chip 8-bit microcontroller
OSCILLATOR
CHARACTERISTICS
XTAL1 and XTAL2 are the input and output,
respectively, of an inverting amplifier. The
pins can be configured for use as an on-chip
oscillator, as shown in the logic symbol.
To drive the device from an external clock
source, XTAL1 should be driven while XTAL2
is left unconnected. There are no
requirements on the duty cycle of the
external clock signal, because the input to
the internal clock circuitry is through a
divide-by-two flip-flop. However, minimum
and maximum high and low times specified in
the data sheet must be observed.
RESET
A reset is accomplished by holding the RST
pin high for at least two machine cycles (24
oscillator periods), while the oscillator is
running. To ensure a good power-on reset,
the RST pin must be high long enough to
allow the oscillator time to start up (normally
a few milliseconds) plus two machine cycles.
At power-on, the voltage on V
must come up at the same time for a proper
start-up.
and RST
DD
IDLE MODE
In the idle mode, the CPU puts itself to sleep
while all of the on-chip peripherals stay
active. The instruction to invoke the idle
mode is the last instruction executed in the
normal operating mode before the idle mode
is activated. The CPU contents, the on-chip
RAM, and all of the special function registers
remain intact during this mode. The idle
mode can be terminated either by any
enabled interrupt (at which time the process
is picked up at the interrupt service routine
and continued), or by a hardware reset which
starts the processor in the same manner as a
power-on reset.
POWER-DOWN MODE
In the power-down mode, the oscillator is
stopped and the instruction to invoke
power-down is the last instruction executed.
Only the contents of the on-chip RAM are
preserved. A hardware reset is the only way
to terminate the power-down mode. the
control bits for the reduced power modes are
in the special function register PCON. Table 1
shows the state of the I/O ports during low
current operating modes.
Table 1. External Pin Status During Idle and Power-Down Modes
MODE
Idle Internal 1 1 Data Data Data Data Data High
Idle External 1 1 Float Data Address Data Data High
Power-down Internal 0 0 Data Data Data Data Data High
Power-down External 0 0 Float Data Data Data Data High
PROGRAM
MEMORY
ALE PSEN PORT 0 PORT 1 PORT 2 PORT 3 PORT 4
PWM0/
PWM1
ABSOLUTE MAXIMUM RATINGS
Voltage on any other pin to V
Input, output DC current on any single I/O pin 5.0 mA
Power dissipation (based on package heat transfer limitations, not device power consumption) 1.0 W
Storage temperature range –65 to +150 °C
NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section
of this specification is not implied.
2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima.
3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V
noted.
SS
1, 2, 3
PARAMETER RATING UNIT
–0.5 to +6.5 V
unless otherwise
SS
1992 Jan 08
6
Philips Semiconductors Product specification
80C562/83C562Single-chip 8-bit microcontroller
DC ELECTRICAL CHARACTERISTICS
VSS, AVSS = 0V
TEST LIMITS
SYMBOL PARAMETER CONDITIONS MIN MAX UNIT
V
DD
I
DD
I
ID
I
PD
Inputs
V
IL
V
IL1
V
IH
V
IH1
I
IL
I
TL
+I
IL1
Outputs
V
OL
V
OL1
V
OH
V
OH1
V
OH2
R
RST
C
IO
Supply voltage
PCB8XC562 4.0 6.0 V
PCF8XC562 4.0 6.0 V
PCA8XC562 4.5 5.5 V
Supply current operating: See notes 1 and 2
PCB8XC562 f
PCF8XC562 f
PCA8XC562 f
= 16MHz 45 mA
OSC
= 12MHz 34 mA
OSC
= 12MHz 30 mA
OSC
Idle mode: See notes 1 and 3
PCB8XC562 f
PCF8XC562 f
PCA8XC562 f
= 16MHz 10 mA
OSC
= 12MHz 8 mA
OSC
= 12MHz 7 mA
OSC
Power-down current: See notes 1 and 4;
2V < V
< VDD max
PD
PCB8XC562 50 µA
PCF8XC562 50 µA
PCA8XC562 100 µA
Input low voltage, except EA –0.5 0.2VDD–0.1 V
Input low voltage to EA –0.5 0.2VDD–0.3 V
Input high voltage, except XTAL1, RST 0.2VDD+0.9 VDD+0.5 V
Input high voltage, XTAL1, RST 0.7V
DD
VDD+0.5 V
Logical 0 input current, ports 1, 2, 3, 4 VIN = 0.45V –50 µA
Logical 1-to-0 transition current, ports 1, 2, 3, 4 See note 5 –650 µA
Input leakage current, port 0, EA, STADC, EW 0.45V < V
Output low voltage, ports 1, 2, 3, 4 IOL = 1.6mA
Output low voltage, port 0, ALE, PSEN, PWM0, PWM1 IOL = 3.2mA
I
< V
6
6
DD
10 µA
0.45 V
0.45 V
Output high voltage, ports 1, 2, 3, 4 VDD + 5V+10%
–IOH = 60µA 2.4 V
Output high voltage (port 0 in external bus mode, ALE,
, PWM0, PWM1)
PSEN
7
–IOH = 25µA 0.75V
–IOH = 10µA 0.9V
VDD + 5V+10%
DD
DD
–IOH = 400µA 2.4 V
–IOH = 150µA 0.75V
–IOH = 40µA 0.9V
DD
DD
Output high voltage (RST) –IOH = 400µA 2.4 V
–IOH = 120µA 0.8V
DD
Internal reset pull-down resistor 50 150 kΩ
Pin capacitance Test freq = 1MHz,
= 25°C
T
amb
10 pF
V
V
V
V
V
1992 Jan 08
7
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