Philips 74LV109PW, 74LV109N, 74LV109DB, 74LV109D Datasheet

INTEGRATED CIRCUITS

74LV109

Dual JK

flip-flop with set and reset;

positive-edge trigger

Product specification Supersedes data of 1997 Jun 06 IC24 Data Handbook

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1998 Apr 20

Philips Semiconductors Product specification

74L V109Dual JK flip-flop with set and reset; positive-edge trigger

FEA TURES

•Optimized for low voltage applications: 1.0 to 3.6 V

•Accepts TTL input levels between V

•Typical V

amb

•Typical V

amb

(output ground bounce) < 0.8 V at V

OLP

= 25°C

(output VOH undershoot) > 2 V at V

OHV

= 25°C

= 2.7 V and V

= 3.3 V,

•Output capability: standard

•I

category: flip-flops

QUICK REFERENCE DATA

GND = 0 V; T

= 25°C; tr =t

amb

SYMBOL

Propagation delay

PHL/tPLH

nCP to nQ, nQ nSD to nQ, nQ nRD to nQ, nQ

max

Maximum clock frequency 77 MHz Input capacitance 3.5 pF Power dissipation capacitance per flip-flop VI = GND to V

NOTE:

is used to determine the dynamic power dissipation (PD in µW)

1. C

= CPD × V

= input frequency in MHz; CL = output load capacitance in pF;

= output frequency in MHz; VCC = supply voltage in V;

Σ (C

× V

× fi Σ (CL × V

× fo) = sum of the outputs.

≤ 2.5 ns

PARAMETER CONDITIONS TYPICAL UNIT

× fo) where:

= 3.6 V

CL = 15 pF; VCC = 3.3 V

DESCRIPTION

The 74LV109 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT109.

The 74LV109 is a dual positive-edge triggered JK featuring individual J, K

) inputs; also complementary Q and Q outputs.

inputs, clock (CP) inputs, set (SD) and reset

The set and reset are asynchronous active LOW inputs and operate independently of the clock input.

The J and K

inputs control the state changes of the flip-flops as described in the mode select function table. The J and K be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation.

The JK

design allows operation as a D-type flip-flop by tying the

J and K

inputs together.

Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.

14 12 12

20 pF

-type flip-flop

inputs must

ORDERING INFORMATION

PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA PKG. DWG. #

16-Pin Plastic DIL –40°C to +125°C 74LV109 N 74LV109 N SOT38-4 16-Pin Plastic SO –40°C to +125°C 74LV109 D 74LV109 D SOT109-1 16-Pin Plastic SSOP Type II –40°C to +125°C 74LV109 DB 74LV109 DB SOT338-1 16-Pin Plastic TSSOP Type I –40°C to +125°C 74LV109 PW 74LV109PW DH SOT403-1

PIN CONFIGURATION

1CP 1S

GND

1998 Apr 20 853-1986 19255

16 15 14 13 12 11 10

SV00517

V 2R

2J 2K 2CP

2S 2Q

PIN DESCRIPTION

NUMBER

1, 15 1RD, 2R

2, 14, 3, 13

4, 12 1CP, 2CP

5, 11 1S 6, 10 1Q, 2Q True flip-flop outputs

7, 9 1Q, 2Q Complement flip-flop outputs 8 GND Ground (0 V) 16 V

SYMBOL FUNCTION

Asynchronous reset input

(active LOW)

1J, 2J, 1K, 2K

Synchronous inputs; flip-flops 1 and 2 Clock input (LOW-to-HIGH,

edge-triggered) Asynchronous set inputs

(active LOW)

Positive supply voltage

Philips Semiconductors Product specification

Dual JK

flip-flop with set and reset; positive-edge trigger

LOGIC SYMBOL (IEEE/IEC)

(a) (b)

610

LOGIC SYMBOL

74LV109

FUNCTIONAL DIAGRAM

SV00519

1CP

2CP

FF1

FF2

SV00520

14 2J

4 1CP

12 2CP

13 2K

LOGIC DIAGRAM

2 1J

3 1K

1Q 6

2Q 10

SV00518

1998 Apr 20

SV00521

Philips Semiconductors Product specification

OPERATING MODES

Dual JK

flip-flop with set and reset; positive-edge trigger

74LV109

FUNCTION TABLE

INPUTS OUTPUTS

nCP nJ nK nQ nQ

Asynchronous set L H X X X H L Asynchronous reset H L X X X L H Undetermined L L X X X H H

Toggle H H ↑ h l q q Load “0” (reset) H H ↑ l l L H

Load “1” (set) H H ↑ h h H L Hold “no change” H H ↑ l h q q

NOTES:

H = HIGH voltage level h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition L = LOW voltage level I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition q = lower case letters indicate the state of the referenced output one set-up time prior to the LOW-to-HIGH CP transition. X = don’t care ↑ = LOW-to-HIGH CP transition

RECOMMENDED OPERATING CONDITIONS

SYMBOL PARAMETER CONDITIONS MIN TYP. MAX UNIT

amb

tr, t

NOTE:

1. The LV is guaranteed to function down to V

DC supply voltage See Note 1 1.0 3.3 3.6 V

Input voltage 0 – V

Output voltage 0 – V

Operating ambient temperature range in free air

Input rise and fall times except for

Schmitt-trigger inputs

See DC and AC

characteristics

VCC = 1.0V to 2.0V VCC = 2.0V to 2.7V VCC = 2.7V to 3.6V

= 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC = 3.6V.

-40

-40 –

– –

– – –

CC CC

+85

+125

500 200 100

ns/V

V V

°C

ABSOLUTE MAXIMUM RATINGS

1, 2

In accordance with the Absolute Maximum Rating System (IEC 134). Voltages are referenced to GND (ground = 0V).

SYMBOL

GND

stg

TOT

DC supply voltage –0.5 to +4.6 V DC input diode current VI < –0.5 or VI > VCC + 0.5V 20 mA DC output diode current VO < –0.5 or VO > VCC + 0.5V 50 mA DC output source or sink current

– standard outputs DC VCC or GND current for types with

– standard outputs 50 Storage temperature range –65 to +150 °C

Power dissipation per package – plastic DIL – plastic mini-pack (SO) – plastic shrink mini-pack (SSOP and TSSOP)

PARAMETER CONDITIONS RATING UNIT

–0.5V < VO < VCC + 0.5V

for temperature range: –40 to +125°C above +70°C derate linearly with 12 mW/K above +70°C derate linearly with 8 mW/K above +60°C derate linearly with 5.5 mW/K

750 500 400

NOTE:

1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability .

2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

1998 Apr 20

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