Philips 74HCT6323AU, 74HCT6323AD, 74HC6323AU Datasheet

DATA SH EET

Product specification
Supersedes data of December 1990
File under Integrated Circuits, IC06

September 1993

INTEGRATED CIRCUITS

74HC/HCT6323A

Programmable ripple counter with
oscillator; 3-state

For a complete data sheet, please also download:

•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

September 1993 2

Philips Semiconductors Product specification

Programmable ripple counter with
oscillator; 3-state

74HC/HCT6323A

FEATURES

• 8-pin space saving package

• Programmable 3-stage ripple

counter

• Suitable for over-tone crystal
application up to 50 MHz
(VCC=5V±10%)

• 3-state output buffer

• Two internal capacitors

• Recommended operating range for

use with third overtone crystals
3to6V

• Oscillator stop function (MR)

• Output capability:
bus driver → (15 LSTTL)

• ICC category: MSI.

APPLICATIONS

• Control counters

• Timers

• Frequency dividers

• Time-delay circuits

• CIO (Compact Integrated

Oscillator)

• Third-overtone crystal operation.

GENERAL DESCRIPTION

The HC/HCT6323A are high-speed
Si-gate CMOS devices.

They are specified in compliance with
JEDEC standard no. 7A.

The HC/HCT6323A are oscillators
designed for quartz crystal combined
with a programmable 3-state counter,
a 3-state output buffer and an
overriding asynchronous master
reset (

MR). With the two select inputs
S1 and S2 the counter can be
switched in the divide-by-1, 2, 4 or 8
mode. If left floating the clock is
divided by 8. The oscillator is
designed to operate either in the
fundamental or third overtone mode
depending on the crystal and external
components applied. On-chip

capacitors minimize external
component count for third overtone
crystal applications.

The oscillator may be replaced by an
external clock signal at input X1. In
this event the other oscillator pin (X2)
must be floating. The counter
advances on the negative-going
transition of X1. A LOW level on

MR

resets the counter, stops the oscillator

and sets the output buffer in the
3-state condition. MR can be left
floating since an internal pull-up
resistor will make the MR inactive. In
the HCT version, the MR input and
the two mode select pins S1 and S2
are TTL compatible, but the X1 input
has CMOS input switching levels and
may be driven by a TTL output using
a pull-up resistor connected to VCC.

QUICK REFERENCE DATA

GND = 0 V; T

amb

= 25 °C; tr = tf = 6 ns.

Notes

1. C

PD

is used to determine the dynamic power dissipation (PD in µW):

PD = (CPD x V

CC

2

x fi) + (CL + V

CC

2

x fo) + (I

pull-up

x VCC)

where:

fi = input frequency in MHz; fo = output frequency in MHz.
VCC = supply voltage in V; CL = output load capacitance in pF.
I

pull-up

= pull-up currents in µA.

2. For HC and HCT an external clock is applied to X1 with:
tr = tf≤ 6 ns, Vi is GND to VCC, MR = HIGH
I

pull-up

is the summation of −II (µA) of S1 and S2 inputs at the LOW state.

ORDERING INFORMATION

SYMBOL PARAMETER CONDITIONS

TYP.

UNIT

HC HCT

t

PHL/tPLH

propagation delay
X1 to OUT
(S1 = S2 = LOW)

CL = 15 pF;
VCC = 5 V

17 17 ns

f

max

maximum clock
frequency

90 90 MHz

C

I

input capacitance
except X1 and X2

3.5 3.5 pF

C

PD

power dissipation
capacitance per
package

+1; notes 1 and 2 54 54 pF
+2; notes 1 and 2 42 42 pF
+4; notes 1 and 2 36 36 pF
+8; notes 1 and 2 33 33 pF

EXTENDED TYPE

NUMBER

PACKAGE

PINS PIN POSITION MATERIAL CODE

74HC/HCT6323AD 8 SO plastic SOT96

September 1993 3

Philips Semiconductors Product specification

Programmable ripple counter with
oscillator; 3-state

74HC/HCT6323A

PINNING

SYMBOL PIN DESCRIPTION

OUT 1 counter output
S1 - S2 3, 2 mode select inputs for divide

by 1, 2, 4 or 8
GND 4 ground (0 V)
MR 5 master reset (active LOW)
X2 6 oscillator pin
X1 7 clock input/oscillator pin
V

CC

8 positive supply

FUNCTION TABLE

INPUTS OUTPUTS

S1 S2 OUT

00 f

i

01 f

i

/2

10 f

i

/4

11 f

i

/8

Fig.1 Pin configuration.

handbook, halfpage

MBA343

1
2
3
4

8
7
6
5

OUT

GND

V

CC

X1
X2

MR

6323A

S2
S1

Fig.2 IEC logic symbol.

handbook, halfpage

MBA344

X2

CP

MR

7
5

3

21

6

OUT

C

D

X1

S1
S2

Fig.3 Functional diagram.

handbook, full pagewidth

MBA350

X2

X1

OUTS1 S2MR

C

D

CP

3 - STAGE BINARY COUNTER

AND DECODER

7

5

6

32 1

September 1993 4

Philips Semiconductors Product specification

Programmable ripple counter with
oscillator; 3-state

74HC/HCT6323A

Fig.4 Logic diagram.

Internal capacitors typical 7 pF each. Including
stray capacitors on pin X1 and X2, total capacitance
will be typical 12 pF per pin.

handbook, full pagewidth

MBA349

QCP

FF

R

(1)

V

CC

7 pF

(1)

V

7 pF

CC

QCP

FF

R

QCP

FF

R

X2
X1

DECODER

V

CC

OUT

V

CC

MR

V

CC

S1 S2

September 1993 5

Philips Semiconductors Product specification

Programmable ripple counter with
oscillator; 3-state

74HC/HCT6323A

DC CHARACTERISTICS FOR 74HC

For the DC characteristics see

“74HC/HCT/HCU/HCMOS Logic Family Specifications”

.
Output capability: non-standard; bus driver (except for X2)
ICC category: MSI.
Voltages are referenced to GND (ground = 0 V).

DC CHARACTERISTICS FOR 74HC

SYMBOL PARAMETER

T

amb

(°C)

UNIT

TEST CONDITION

25 −40 to 85 −40 to 125

V

CC

(V)

V

I

OTHER

MIN TYP MAX MIN MAX MIN MAX

V

IH

HIGH level
input voltage
MR, X1 input

1.5

3.15

4.2

1.2

2.4

3.2

−

−

−

1.5

3.15

4.2

−

−

−

1.50

3.15

4.20

−

−

−

V
V
V

2.0

4.5

6.0

V

IL

LOW level
input voltage
MR, X1 input

−

−

−

0.8

2.1

2.8

0.5

1.35

1.80

−

−

−

0.5

1.35

1.8

−

−

−

0.5

1.35

1.8

V
V
V

2.0

4.5

6.0

V

OH

HIGH level
output voltage
X2 output

3.98

5.48−−−−

3.84

5.34−−

3.7

5.2−−

V
V

4.5

6.0

X1 = GND
and
MR = V

CC

IO = −2.6 mA
IO = −3.3 mA

3.98

5.48−−−−

3.84

5.34−−

3.7

5.2−−

V
V

4.5

6.0

X1 = V

CC

and
MR = GND

IO = −2.6 mA
IO = −3.3 mA

1.9

4.4

5.9

2.0

4.5

6.0

−

−

−

1.9

4.4

5.9

−

−

−

1.9

4.4

5.9

−

−

−

V
V
V

2.0

4.5

6.0

X1 = GND
and
MR = V

CC

−IO = 20 µA
IO = −20 µA
IO = −20 µA

1.9

4.4

5.9

2.0

4.5

6.0

−

−

−

1.9

4.4

5.9

−

−

−

1.9

4.4

5.9

−

−

−

V
V
V

2.0

4.5

6.0

X1 = V

CC

and
MR = GND

IO = −20 µA
IO = −20 µA
IO = −20 µA

V

OH

HIGH level
output voltage
OUT

1.9

4.4

5.9

2.0

4.5

6.0

−

−

−

1.9

4.4

5.9

−

−

−

1.9

4.4

5.9

−

−

−

V
V
V

2.0

4.5

6.0

VIH or V

ILIO

= −20 µA
IO = −20 µA
IO = −20 µA

V

OH

HIGH level
output voltage
OUT

3.98

5.48−−−−

3.84

5.34−−

3.7

5.2−−

V
V

4.5

6.0

VIH or V

ILIO

= −6 mA
IO = −7.8 mA

V

OL

LOW level
output voltage
X2 output

−

−

−−0.26

0.26−−

0.33

0.33−−

0.4

0.4VV

4.5

6.0

X1 = V

CC

and
MR = V

CC

IO = 2.6 mA
IO = 3.3 mA

−

−

−

0
0
0

0.1

0.1

0.1

−

−

−

0.1

0.1

0.1

−

−

−

0.1

0.1

0.1

V
V
V

2.0

4.5

6.0

X1 = V

CC

and
MR = V

CC

IO = 20 µA
IO = 20 µA
IO = 20 µA

V

OL

LOW level
output voltage
OUT

−

−

−

0
0
0

0.1

0.1

0.1

−

−

−

0.1

0.1

0.1

−

−

−

0.1

0.1

0.1

V
V
V

2.0

4.5

6.0

VIH or V

ILIO

= 20 µA
IO = 20 µA
IO = 20 µA