Philips 74HCT597U, 74HCT597N, 74HCT597DB, 74HC597U, 74HC597PW Datasheet

INTEGRATED CIRCUITS

DATA SHEET

For a complete data sheet, please also download:

∙The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

∙The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

∙The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT597

8-bit shift register with input flip-flops

Product specification			December 1990
File under Integrated Circuits, IC06

Philips Semiconductors	Product specification
8-bit shift register with input flip-flops	74HC/HCT597

FEATURES

·8-bit parallel storage register inputs

·Shift register has direct overriding load and clear

·Output capability: standard

·ICC category: MSI

QUICK REFERENCE DATA

GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns

GENERAL DESCRIPTION

The 74HC/HCT597 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.

The 74HC/HCT597 consist each of an 8-bit storage register feeding a parallel-in, serial-out 8-bit shift register. Both the storage register and the shift register have positive edge-triggered clocks. The shift register also has direct load (from storage) and clear inputs.

SYMBOL				PARAMETER	CONDITIONS	TYPICAL		UNIT
						HC	HCT
tPHL/ tPLH		propagation delay			CL = 15 pF; VCC = 5 V
			SHCP to Q			17	20	ns
			STCP to Q			25	29	ns
						21	26	ns
			PL	to Q
fmax		maximum clock frequency SHCP				96	83	MHz
CI		input capacitance				3.5	3.5	pF
CPD		power dissipation capacitance per package			notes 1 and 2	29	32	pF
Notes
1. CPD is used to determine the dynamic power dissipation (PD in mW):
PD = CPD ´ VCC2 ´ fi + å (CL ´ VCC2 ´ fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
å (CL ´ VCC2 ´ fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC	the condition is VI = GND to VCC

For HCT the condition is VI = GND to VCC - 1.5 V

ORDERING INFORMATION

See “74HC/HCT/HCU/HCMOS Logic Package Information”.

December 1990

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Philips Semiconductors						Product specification
8-bit shift register with input flip-flops						74HC/HCT597
PIN DESCRIPTION
PIN NO.		SYMBOL			NAME AND FUNCTION
8	GND				ground (0 V)
9	Q				serial data output
10					asynchronous reset input (active LOW)
		MR
11		SHCP			shift clock input (LOW-to-HIGH, edge-triggered)
12	STCP				storage clock input (LOW-to-HIGH, edge-triggered)
13		PL			parallel load input (active LOW)
14		DS			serial data input
15, 1, 2, 3, 4, 5, 6, 7		D0 to D7			parallel data inputs
16	VCC				positive supply voltage

Fig.1 Pin configuration.		Fig.2 Logic symbol.		Fig.3 IEC logic symbol.

December 1990

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Philips Semiconductors	Product specification
8-bit shift register with input flip-flops	74HC/HCT597

Fig.4 Functional diagram.

FUNCTION TABLE

STCP	SHCP		PL			MR		FUNCTION
−	X		X			X		data loaded to input latches
−	X		L			H		data loaded from inputs to shift register
no clock edge	X		L			H		data transferred from input flip-flops to shift register
X	X		L			L		invalid logic, state of shift register indeterminate when signals removed
X	X		H			L		shift register cleared
X	−		H			H		shift register clocked Qn = Qn−1, Q0 = DS
Notes

1.H = HIGH voltage level L = LOW voltage level

X = don’t care

− = LOW-to-HIGH CP transition

December 1990

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