Philips 74HCT595N, 74HCT595DB, 74HCT595D, 74HCT595PW, 74HC595U Datasheet

INTEGRATED CIRCUITS

DATA SHEET

For a complete data sheet, please also download:

∙The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

∙The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

∙The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT595

8-bit serial-in/serial or parallel-out shift register with output latches; 3-state

Product specification

1998 Jun 04

Supersedes data of September 1993

File under Integrated Circuits, IC06

Philips Semiconductors	Product specification

8-bit serial-in/serial or parallel-out shift

74HC/HCT595

register with output latches; 3-state

FEATURES

·8-bit serial input

·8-bit serial or parallel output

·Storage register with 3-state outputs

·Shift register with direct clear

·100 MHz (typ) shift out frequency

·Output capability:

–parallel outputs; bus driver

–serial output; standard

·ICC category: MSI.

APPLICATIONS

·Serial-to-parallel data conversion

·Remote control holding register.

QUICK REFERENCE DATA

GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns.

DESCRIPTION

The 74HC/HCT595 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.

The “595” is an 8-stage serial shift register with a storage register and 3-state outputs. The shift register and storage register have separate clocks.

Data is shifted on the positive-going transitions of the SHCP input. The data in each register is transferred to the storage register on a positive-going transition of the STCP input. If both clocks are connected together, the shift register will always be one clock pulse ahead of the storage register.

The shift register has a serial input (DS) and a serial standard output (Q7’) for cascading. It is also provided with asynchronous reset (active LOW) for all 8 shift register stages. The storage register has 8 parallel 3-state bus driver outputs. Data in the storage register appears at the output whenever the output enable input (OE) is LOW.

SYMBOL	PARAMETER			CONDITIONS		TYP.		UNIT
					HC		HCT
tPHL/tPLH	propagation delay			CL = 15 pF; VCC = 5 V
		SHCP to Q7’			16		21	ns
		STCP to Qn			17		20	ns
					14		19	ns
		MR	to Q7’
fmax	maximum clock frequency SHCP, STCP				100		57	MHz
CI	input capacitance				3.5		3.5	pF
CPD	power dissipation capacitance per package			notes 1 and 2	115		130	pF

Notes

1. CPD is used to determine the dynamic power dissipation (PD in mW): PD = CPD ´ VCC2 ´ fi + å (CL ´ VCC2 ´ fo) where:

fi = input frequency in MHz fo = output frequency in MHz

å(CL ´ VCC2 ´ fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V

2. For HC the condition is VI = GND to VCC; for HCT the condition is VI = GND to VCC - 1.5 V.

1998 Jun 04

2

Philips Semiconductors	Product specification

8-bit serial-in/serial or parallel-out shift

74HC/HCT595

register with output latches; 3-state

ORDERING INFORMATION

	TYPE NUMBER		PACKAGE
		NAME	DESCRIPTION	VERSION
	74HC595N	DIP16	plastic dual in-line package; 16 leads (300 mil); long body	SOT38-1
	74HC595D	SO16	plastic small outline package; 16 leads; body width 3.9 mm	SOT109-1
	74HC595DB	SSOP16	plastic shrink small outline package; 16 leads; body width 5.3 mm	SOT338-1
	74HC595PW	TSSOP16	plastic thin shrink small outline package; 16 leads; body width 4.4 mm	SOT403-1
	74HCT595N	DIP16	plastic dual in-line package; 16 leads (300 mil); long body	SOT38-1
	74HCT595D	SO16	plastic small outline package; 16 leads; body width 3.9 mm	SOT109-1

PINNING

			SYMBOL	PIN	DESCRIPTION
Q0 to Q7				15, 1 to 7	parallel data output
	GND			8	ground (0 V)
	Q7’			9	serial data output
				10	master reset (active LOW)
	MR
	SHCP			11	shift register clock input
	STCP			12	storage register clock input
				13	output enable (active LOW)
	OE
	DS			14	serial data input
	VCC			16	positive supply voltage

									handbook, halfpage				11				12
handbook, halfpage	1										SHCP STCP
Q1				16	VCC
Q2					Q0												Q7'		9
	2			15															15
Q3					DS												Q0
	3			14															1
																	Q1
																			2
Q4	4			13	OE												Q
			595							14						2			3
Q5	5			12	STCP						DS						Q3
																			4
					SHCP												Q4
Q6	6			11															5
Q7																	Q5
	7			10	MR														6
																	Q6
GND					Q7'														7
	8			9													Q
																7
			MLA001
												MR				OE
														10			13
																			MLA002
Fig.1			Pin configuration.							Fig.2 Logic symbol.

1998 Jun 04

3

Philips Semiconductors	Product specification

8-bit serial-in/serial or parallel-out shift

74HC/HCT595

register with output latches; 3-state

OE	13		EN3
	12
STCP			C2
	10
MR		R	SRG8
	11
SHCP			C1/
DS	14	1D	2D	3	15	Q0
					1	Q1
					2	Q2
					3	Q3
					4	Q4
					5	Q5
					6	Q6
					7	Q7
					9	Q7'
				MSA698

Fig.3 IEC logic symbol.

14	DS
11	SHCP							8-STAGE SHIFT REGISTER
10	MR
																Q7'	9
12	STCP
							8-BIT STORAGE REGISTER
																Q0	15
																Q1	1
																Q2	2
13																Q3	3
			OE
									3-STATE OUTPUTS							Q4	4
																Q5	5
																Q6	6
																Q7	7

MLA003

Fig.4 Functional diagram.

1998 Jun 04

4

Philips Semiconductors	Product specification

8-bit serial-in/serial or parallel-out shift

74HC/HCT595

register with output latches; 3-state

handbook, full pagewidth	STAGE 0			STAGES 1 TO 6	STAGE 7
DS	D Q		D	Q	D Q		Q7'
	FF0				FF7
	CP				CP
	R				R
SHCP
MR
	D	Q			D	Q
	LATCH				LATCH
	CP				CP
STCP
OE
		Q0	Q1	Q2 Q3 Q4 Q5 Q6		Q7	MLA010
			Fig.5	Logic diagram.

1998 Jun 04

5

Philips Semiconductors	Product specification

8-bit serial-in/serial or parallel-out shift

74HC/HCT595

register with output latches; 3-state

FUNCTION TABLE

INPUTS

OUTPUTS

FUNCTON

SHCP

STCP

OE

MR

DS

Q7’

QN

X

X

L

L

X

L

NC

a LOW level on

only affects the shift registers

MR

X

−

L

L

X

L

L

empty shift register loaded into storage register

X

X

H

L

X

L

Z

shift register clear. Parallel outputs in high-impedance

OFF-state

−

X

L

H

H

Q6’

NC

logic high level shifted into shift register stage 0. Contents

of all shift register stages shifted through, e.g. previous

state of stage 6 (internal Q6’) appears on the serial output

(Q7’)

X

−

L

H

X

NC

Qn’

contents of shift register stages (internal Qn’) are

transferred to the storage register and parallel output

stages

−

−

L

H

X

Q6’

Qn’

contents of shift register shifted through. Previous

contents of the shift register is transferred to the storage

register and the parallel output stages.

Notes

1.H = HIGH voltage level; L = LOW voltage level

− = LOW-to-HIGH transition; ↓ = HIGH-to-LOW transition Z = high-impedance OFF-state; NC = no change

X = don’t care.

1998 Jun 04

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