Philips 74HC595, 74HCT595 DATA SHEET

INTEGRATED CIRCUITS

DATA SH EET

74HC595; 74HCT595

8-bit serial-in, serial or parallel-out
shift register with output latches;
3-state

Product specification
Supersedes data of 1998 Jun 04

2003 Jun 25

Philips Semiconductors Product specification

8-bit serial-in, serial or parallel-out shift
register with output latches; 3-state

FEATURES

• 8-bit serial input

• 8-bit serial or parallel output

• Storage register with 3-state outputs

• Shift register with direct clear

• 100 MHz (typical) shift out frequency

• ESD protection:

HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.

APPLICATIONS

• Serial-to-parallel data conversion

• Remote control holding register.

74HC595; 74HCT595

DESCRIPTION

The74HC/HCT595arehigh-speedSi-gateCMOSdevices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.

The 74HC/HCT595 is an 8-stage serialshift register witha
storage register and3-state outputs. The shift register and
storage register have separate clocks.

Data is shifted on the positive-going transitions of the
SH_CP input. The data in each register is transferred to
the storage register on a positive-going transition of the
ST_CP input. If both clocks are connected together, the
shift register will always be one clock pulse ahead of the
storage register.

The shift register has a serial input (DS) and a serial
standard output (Q7’) for cascading. It is also provided
with asynchronous reset (active LOW) for all 8 shift
register stages. The storage register has 8 parallel 3-state
bus driver outputs. Data in the storage register appears at
the output whenever the output enable input (OE) is LOW.

QUICK REFERENCE DATA

GND = 0 V; T

=25°C; tr=tf= 6 ns.

amb

SYMBOL PARAMETER CONDITIONS

t

PHL/tPLH

propagation delay CL= 50 pF; VCC= 4.5 V

SH_CP to Q7’ 19 25 ns
SH_CP to Qn 20 24 ns
MR to Q7’ 100 52 ns

f

max

C
C

I
PD

maximum clock frequency SH_CPand ST_CP 100 57 MHz
input capacitance 3.5 3.5 pF
power dissipation capacitance per package notes 1 and 2 115 130 pF

Notes

1. C

is used to determine the dynamic power dissipation (PDin µW).

PD

PD=CPD× V

2

× fi× N+Σ(CL× V

CC

2

× fo) where:

CC

fi= input frequency in MHz;
fo= output frequency in MHz;
CL= output load capacitance in pF;
VCC= supply voltage in Volts;
N = total load switching outputs;
Σ(CL× V

2

× fo) = sum of the outputs.

CC

2. For 74HC595 the condition is VI= GND to VCC.
For 74HCT595 the condition is VI= GND to VCC− 1.5 V.

TYPICAL

UNIT

74HC 74HCT

2003 Jun 25 2

Philips Semiconductors Product specification

8-bit serial-in, serial or parallel-out shift

74HC595; 74HCT595

register with output latches; 3-state

FUNCTION TABLE

See note 1.

INPUT OUTPUT

SH_CP ST_CP

X X L L X L n.c. a LOW level on
X ↑ L L X L L empty shift register loaded into storage register
X X H L X L Z shift register clear; parallel outputs in high-impedance

↑ X L H H Q6’ n.c. logic high level shifted into shift register stage 0;

X ↑ L H X n.c. Qn’ contents of shift register stages (internal Qn’) are

↑↑L H X Q6’ Qn’ contents of shift register shifted through; previous

OE MR DS Q7’ Qn

OFF-state

contents of allshift registerstages shifted through, e.g.
previous state of stage 6 (internal Q6’) appears on the
serial output (Q7’)

transferred to the storage register and parallel output
stages

contents of the shift register is transferred to the
storage register and the parallel output stages

FUNCTION

MR only affects the shift registers

Note

1. H = HIGH voltage level;
L = LOW voltage level;

↑ = LOW-to-HIGH transition;
↓ = HIGH-to-LOW transition;

Z = high-impedance OFF-state;
n.c. = no change;
X = don’t care.

ORDERING INFORMATION

PACKAGE

TYPE NUMBER

74HC595N −40 to +125 °C 16 DIP16 plastic SOT38-4
74HCT595N −40 to +125 °C 16 DIP16 plastic SOT38-4
74HC595D −40 to +125 °C 16 SO16 plastic SOT109-1
74HCT595D −40 to +125 °C 16 SO16 plastic SOT109-1
74HC595DB −40 to +125 °C 16 SSOP16 plastic SOT338-1
74HCT595DB −40 to +125 °C 16 SSOP16 plastic SOT338-1
74HC595PW −40 to +125 °C 16 TSSOP16 plastic SOT403-1
74HCT595PW −40 to +125 °C 16 TSSOP16 plastic SOT403-1
74HC595BQ −40 to +125 °C 16 DHVQFN16 plastic SOT763-1
74HCT595BQ −40 to +125 °C 16 DHVQFN16 plastic SOT763-1

TEMPERATURE

RANGE

PINS PACKAGE MATERIAL CODE

2003 Jun 25 3

Philips Semiconductors Product specification

8-bit serial-in, serial or parallel-out shift
register with output latches; 3-state

PINNING

PIN SYMBOL DESCRIPTION

1 Q1 parallel data output
2 Q2 parallel data output
3 Q3 parallel data output
4 Q4 parallel data output
5 Q5 parallel data output
6 Q6 parallel data output
7 Q7 parallel data output
8 GND ground (0 V)

9 Q7’ serial data output
10
11 SH_CP shift register clock input
12 ST_CP storage register clock input
13
14 DS serial data input
15 Q0 parallel data output
16 V

MR master reset (active LOW)

OE output enable (active LOW)

CC

positive supply voltage

74HC595; 74HCT595

handbook, halfpage

Q1
Q2
Q3
Q4
Q5
Q6
Q7

GND

1
2
3
4

595

5
6
7
8

MLA001

16
15
14
13
12
11
10

9

V
Q0
DS
OE
ST_CP
SH_CP
MR
Q7'

Fig.1 Pin configuration DIP16, SO16 and

(T)SSOP16.

CC

V

handbook, halfpage

2

Q2

3

Q3

Q4

4

5

Q5

611

Q6

7

Q7

Top view

(1) The die substrate is attached to this pad using conductive die

attach material. It can not be used as a supply pin or input.

Q1

CC

116

(1)

GND

9

8

GND

Q7'

MBL893

15

Q0

14

DS

13

OE

12

ST_CP

SH_CP

10

MR

Fig.2 Pin configuration DHVQFN16.

2003 Jun 25 4

Philips Semiconductors Product specification

8-bit serial-in, serial or parallel-out shift
register with output latches; 3-state

handbook, halfpage

14

SH_CP

DS

11 12

ST_CP

Q7'

OEMR

1310

Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7

9

15

1
2
3
4
5
6
7

MLA002

handbook, halfpage

OE

ST_CP

MR

SH_CP

DS

13
12
10

R

11

14

1D 2D

74HC595; 74HCT595

EN3

C2

SRG8

C1/

15

3

MSA698

Q0

1

Q1

2

Q2

3

Q3

4

Q4

5

Q5

6

Q6

7

Q7

9

Q7'

handbook, full pagewidth

Fig.3 Logic symbol.

Fig.4 IEC logic symbol.

14

DS
SH_CP

11
10

MR

ST_CP

12

OE

13

8-STAGE SHIFT REGISTER

8-BIT STORAGE REGISTER

3-STATE OUTPUTS

Q7'

Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7

9

15
1
2
3
4
5
6
7

Fig.5 Functional diagram.

2003 Jun 25 5

MLA003

Philips Semiconductors Product specification

8-bit serial-in, serial or parallel-out shift
register with output latches; 3-state

handbook, full pagewidth

DS

SH_CP

MR

STAGE 0 STAGES 1 to 6 STAGE 7

DCPQ

FF0

R

DCPQ

LATCH

DQ

74HC595; 74HCT595

DCPQ

FF7

R

DCPQ

LATCH

Q7'

ST_CP

OE

Q0

Q1 Q2 Q3 Q4 Q5 Q6 Q7

Fig.6 Logic diagram.

MLA010

2003 Jun 25 6

Philips Semiconductors Product specification

8-bit serial-in, serial or parallel-out shift
register with output latches; 3-state

handbook, full pagewidth

SH_CP

DS

ST_CP

MR

74HC595; 74HCT595

Q0

Q1

Q6

Q7

Q7'

OE

high-impedance OFF-state

MLA005-1

Fig.6 Timing diagram.

2003 Jun 25 7

Philips Semiconductors Product specification

8-bit serial-in, serial or parallel-out shift

74HC595; 74HCT595

register with output latches; 3-state

RECOMMENDED OPERATING CONDITIONS

SYMBOL PARAMETER CONDITIONS

MIN. TYP. MAX. MIN. TYP. MAX.

V
V
V
T
t

r,tf

CC
I
O
amb

supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V
input voltage 0 − V
output voltage 0 − V
ambient temperature −40 − +125 −40 − +125 °C
input rise and fall time VCC= 2.0 V −−1000 −−−ns

V

= 4.5 V − 6.0 500 − 6.0 500 ns

CC

V

= 6.0 V −−400 −−−ns

CC

LIMITED VALUES

In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

CC

I

IK

I

OK

I

O

supply voltage −0.5 +7.0 V
input diode current VI< −0.5 V to VI>VCC+ 0.5 V −±20 mA
output diode current VO< −0.5 V to VO>VCC+ 0.5 V −±20 mA
output source or sink current VO= −0.5 V to VCC+ 0.5 V

Q7’ standard output −±25 mA
Qn bus driver outputs −±35 mA

I

, I

CC

T

stg

P

tot

GNDVCC

or GND current −±70 mA
storage temperature −65 +150 °C
power dissipation T

= −40 to +125 °C; note 1 − 500 mW

amb

74HC 74HCT

0 − V

CC

0 − V

CC

CC
CC

UNIT

V
V

Note

1. For DIP16 packages: above 70 °C derate linearly with 12 mW/K.
For SO16 packages: above 70 °C derate linearly with 8 mW/K.
For SSOP16 packages: above 60 °C derate linearly with 5.5 mW/K.
For TSSOP16 packages: above 60 °C derate linearly with 5.5 mW/K.
For DHVQFN16 packages: above 60 °C derate linearly with 4.5 mW/K.

2003 Jun 25 8

Philips Semiconductors Product specification

8-bit serial-in, serial or parallel-out shift

74HC595; 74HCT595

register with output latches; 3-state

DC CHARACTERISTICS
Type 74HC

At recommended operating conditions; voltages are referenced to GND (ground=0V).

SYMBOL PARAMETER

T

= −40 to +85 °C; note 1

amb

V

IH

HIGH-level input
voltage

V

IL

LOW-level input
voltage

V

OH

HIGH-level output
voltage

V

OL

LOW-level output
voltage

I

LI

I

OZ

input leakage current VI=VCCor GND 6.0 −−±1.0 µA
3-state output

OFF-state current

I

CC

quiescent supply
current

TEST CONDITIONS

MIN. TYP. MAX. UNIT

OTHER V

CC

(V)

2.0 1.5 1.2 − V

4.5 3.15 2.4 − V

6.0 4.2 3.2 − V

2.0 − 0.8 0.5 V

4.5 − 2.1 1.35 V

6.0 − 2.8 1.8 V

VI=VIH or V

IL

all outputs

I

= −20 µA 2.0 1.9 2.0 − V

O

4.5 4.4 4.5 − V

6.0 5.9 6.0 − V

Q7’ standard output

I

= −4.0 mA 4.5 3.84 4.32 − V

O

I

= −5.2 mA 6.0 5.34 5.81 − V

O

Qn bus driver outputs

I

= −6.0 mA 4.5 3.84 4.32 − V

O

I

= −7.8 mA 6.0 5.34 5.81 − V

O

VI=VIH or V

IL

all outputs

I

=20µA 2.0 − 0 0.1 V

O

4.5 − 0 0.1 V

6.0 − 0 0.1 V

Q7’ standard output

IO= 4.0 mA 4.5 − 0.15 0.33 V
I

= 5.2 mA 6.0 − 0.16 0.33 V

O

Qn bus driver outputs

I

= 6.0 mA 4.5 − 0.16 0.33 V

O

= 7.8 mA 6.0 − 0.16 0.33 V

I

O

VI=VIHor VIL;

6.0 −−±5.0 µA

VO=VCCor GND
VI=VCCor GND;

6.0 −−80 µA

IO=0

2003 Jun 25 9