Page 1
INTEGRATED CIRCUITS
DATA SH EET
74HCT7273
Octal D-type flip-flop with reset;
positive edge-trigger; open drain
outputs
Product specification
File under Integrated Circuits, IC06
1999 Oct 01
Page 2
Philips Semiconductors Product specification
Octal D-type flip-flopwith reset; positive
edge-trigger; open drain outputs
FEATURES
• ESD protection:
HBM EIA/JESD22-A114-A
Exceeds 2000 V
MM EIA/JESD22-A115-A
Exceeds 200 V
• Ideal buffer for MOS
microprocessor or memory
• Eight positive edge-triggered
D-type flip-flops
• Common clock and master reset
• Output capability: standard (open
drain)
• ICC category: MSI.
DESCRIPTION
The 74HCT7273 is a high-speed SI-gate CMOS device and is pin compatible
with Low power Schottky TTL (LSTTL). It is specified in compliance with
JEDEC standard no 7A.
The 74HCT7273 has eight edge-triggered D-type flip-flops with individual D
inputs and Q outputs. The common Clock (CP)andMaster Reset (MR) inputs
load and reset (clear) all flip-flops simultaneously.
The state of each D input, one set-up time before the LOW-to-HIGH clock
transition, is transferred to the corresponding output (Qn) of the flip-flop.
ALOWlevelontheMRinputforcesalloutputsLOW,independentlyoftheclock
or data inputs.
The device is useful for applications requiring true outputs only and clock and
master reset inputs that are common to all storage elements.
The 74HCT7273 has open-drain N-outputs, which are clamped by a diode
connected to VCC. When a HIGH is clocked in the flip-flop, the output comes in
the high-impedance OFF-state. The output may now be pulled to any voltage
betweenGND and V
or HIGH-to-LOW level shifter. For digital operation and OR-tied output
applications, the device must have a pull-up resistor to establish a logic HIGH
level.
74HCT7273
.This allows the device to be used asa LOW-to-HIGH
Omax
QUICK REFERENCE DATA
Ground = 0 V; T
=25°C; tr=tf= 6.0 ns.
amb
SYMBOL PARAMETER CONDITIONS TYPICAL UNIT
t
PZL/tPLZ
f
max
C
I
C
PD
propagation delay CL= 50 pF; VCC= 4.5 V
CP to Q
MR to Q
n
n
16 ns
23 ns
maximum clock frequency 56 MHz
input capacitance 3.5 pF
power dissipation capacitance CL= 50 pF; f = 1 MHz; notes 1 and 2 37 pF
Notes
1. C
is used to determine the dynamic power dissipation (PDin µW).
PD
PD=CPD× V
= input frequency in MHz;
f
i
2
× fi+ ∑ (CL× V
CC
2
× fo)+∑(V
CC
2
/RL) × duty factor LOW where:
0
fo= output frequency in MHz;
∑ (CL× V
2
× fo) = sum of outputs;
CC
CL= output load capacitance in pF;
RL= pull-up resistor in MΩ;
VCC= supply voltage in Volts.
2. The condition is VI= GND to VCC− 1.5 V.
1999 Oct 01 2
Page 3
Philips Semiconductors Product specification
Octal D-type flip-flop with reset; positive
edge-trigger; open drain outputs
FUNCTION TABLE
See note 1.
INPUTS OUTPUTS
OPERATING MODES
MR CP D
Reset (clear) L X X L
Load ‘1’ H ↑ hZ
Load ‘0’ H ↑ lL
Note
1. H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition;
L = LOW voltage level.
l = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition;
Z = high-impedance OFF-state;
X = don’t care;
↑ = LOW-to-HIGH CP transition.
74HCT7273
n
Q
n
ORDERING INFORMATION
OUTSIDENORTH
AMERICA
74HCT7273D 74HCT7273D −40 to +125 °C 20 SO plastic SOT163-1
74HCT7273N 74HCT7273N 20 DIP plastic SOT146-1
NORTH AMERICA
TEMPERATURE
RANGE
PINS PACKAGE MATERIAL CODE
PACKAGE
1999 Oct 01 3
Page 4
Philips Semiconductors Product specification
Octal D-type flip-flop with reset; positive
edge-trigger; open drain outputs
PINNING
PIN SYMBOL DESCRIPTION
1
2, 5, 6, 9, 12, 15, 16, 19 Q
3, 4, 7, 8, 13, 14, 17, 18 D
10 GND ground (0 V)
11 CP clock input (LOW-to-HIGH, edge triggered)
20 V
handbook, halfpage
MR
Q
D
D
Q
Q
D
D
Q
GND
1
2
0
3
0
4
1
5
1
6
2
7
2
8
3
9
3
10
MR asynchronous master reset (active LOW)
7273
to Q
0
to D
0
CC
MNA380
7
7
V
20
CC
Q
19
7
D
18
7
D
17
6
Q
16
6
Q
15
5
D
14
5
D
13
4
Q
12
4
CP
11
flip-flop outputs
data inputs
DC supply voltage
handbook, halfpage
11
1
D0D1D2D3D4D5D6D
CP
MR
Q0Q1Q2Q3Q4Q5Q6Q
74HCT7273
181714138743
7
7
191615129652
MNA381
Fig.1 Pin configuration.
1999 Oct 01 4
Fig.2 Logic symbol.
Page 5
Philips Semiconductors Product specification
Octal D-type flip-flop with reset; positive
edge-trigger; open drain outputs
handbook, halfpage
11
C1
1
R
3
1D
4
7
8
13
14
17
18
74HCT7273
2
5
6
9
12
15
16
19
MNA382
handbook, full pagewidth
D
0
CP
11
MR
1
D
CP
FF1
R
Fig.3 IEC logic symbol.
181714138743
D
1
Q
D
D
FF2
CP
R
D
Q
0
D
2
Q
D
FF3
CP
R
D
Q
1
D
3
Q
D
FF4
CP
R
D
Q
2
D
4
Q
D
FF5
CP
R
D
Q
3
D
5
Q
D
FF6
CP
R
D
Q
4
D
6
Q
D
FF7
CP
R
D
Q
5
D
7
Q
D
Q
FF8
CP
R
D
Q
6
Q
7
191615129652
MNA383
Fig.4 Functional diagram.
1999 Oct 01 5
Page 6
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1999 Oct 01 6
handbook, full pagewidth
Philips Semiconductors Product specification
Octal D-type flip-flop with reset; positive
edge-trigger; open drain outputs
CP
MR
D
0
D
FF1
CP
R
D
1
Q
D
D
FF2
CP
R
V
CC
D
2
Q
D
Q
0
D
FF3
CP
R
V
CC
D
3
Q
D
Q
1
D
FF4
CP
R
V
CC
D
4
Q
D
Q
2
D
FF5
CP
R
V
CC
D
5
Q
D
Q
3
D
FF6
CP
R
V
CC
D
6
Q
D
Q
4
D
FF7
CP
R
V
CC
D
7
Q
D
Q
5
D
Q
FF8
CP
R
D
V
CC
Q
6
MNA384
V
CC
Q
7
74HCT7273
Fig.5 Logic diagram.
Page 7
Philips Semiconductors Product specification
Octal D-type flip-flop with reset; positive
74HCT7273
edge-trigger; open drain outputs
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER CONDITIONS
MIN. TYP. MAX.
V
CC
V
I
V
O
T
amb
t
(∆t/∆f) input rise and fall times
r,tf
DC supply voltage 4.5 5.0 5.5 V
input voltage 0 − V
output voltage 0 − V
operating ambient
temperature
see DC and AC characteristics
per device
−40 − +85 °C
−40 − +125 °C
VCC= 2.0 V − 6.0 500 ns/V
except for Schmitt-trigger
inputs
V
= 4.5 V − 6.0 500
CC
V
= 6.0 V − 6.0 500
CC
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134); voltages are referenced to GND (ground = 0 V).
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
CC
V
O
I
IK
I
OK
I
O
I
CC
T
stg
P
D
DC supply voltage −0.5 +7.0 V
output voltage −0.5 +7.0 V
DC input diode current VI< −0.5 Vor VI>VCC+ 0.5 V − 20 mA
DC output diode current VO< −0.5 Vor VO>VCC+ 0.5 V −±20 mA
DC output source or sink current −0.5V < VO<VCC+ 0.5 V − 25 mA
DC VCC or GND current −±50 mA
storage temperature −65 +150 °C
power dissipation per package for temperature range: −40 to +125 °C
plastic DIP note 1 − 750 mW
plastic mini-pack (SO) note 2 − 500 mW
TYPE
CC
CC
UNIT
V
V
Note
1. For DIP package: above 70 °C the value of P
derates linearly with 12 mW/K.
D
2. For SO package: above 70 °C the value of PDderates linearly with 8 mW/K.
1999 Oct 01 7
Page 8
Philips Semiconductors Product specification
Octal D-type flip-flop with reset; positive
edge-trigger; open drain outputs
DC CHARACTERISTICS
Over recommended operating conditions; voltages are referenced to GND (ground=0V).
SYMBOL PARAMETER
V
IH
HIGH-levelinput
voltage
V
IL
LOW-level input
voltage
V
OL
LOW-level
output voltage
I
I
input leakage
current
I
OZ
HIGH level
output leakage
current
I
CC
quiescentsupply
current
∆I
CC
additional
quiescentsupply
current per input
pin
TEST CONDITIONS T
25 −40 to +85 −40 to +125
OTHER VCC (V)
MIN. TYP. MAX. MIN. MAX. MIN. MAX.
4.5 to 5.5 2.0 1.6 − 2.0 − 2.0 − V
4.5 to 5.5 − 1.2 0.8 − 0.8 − 0.8 V
VI=VIHor VIL;
4.5 − 0 0.1 − 0.1 − 0.1 V
IO=20µA
V
I=VIH
or VIL;
4.5 − 0.15 0.26 − 0.33 − 0.4 V
IO= 4.0 mA
VI=VIHor V
VI=VIL;
IL
5.5 −−0.1 − 1.0 − 1.0 µA
4.5 to 5.5 −−±0.5 −±5.0 −±10.0 µA
VO=VCCor GND
VI=VCCor GND;
5.5 −−8.0 − 80 − 160 µA
IO=0
VI=VCC− 2.1 V
4.5 to 5.5 − 100 360 − 450 − 490 µA
other inputs at
VCCor GND;
IO= 0; note 1
amb
(°C)
74HCT7273
UNIT
Note
1. The value off additional quiescent supply current(∆I
) for a unit load of 1 isgiven in the specifications. To determine
CC
∆ICC per input, multiply this value by the unit load coefficient shown in Table 1.
Table 1
INPUT UNIT LOAD COEFFICIENT
MR 1.50
CP 1.50
D
n
0.40
1999 Oct 01 8
Page 9
Philips Semiconductors Product specification
Octal D-type flip-flop with reset; positive
edge-trigger; open drain outputs
AC CHARACTERISTICS
Ground = 0 V; tr=tf≤6.0 ns; CL=50pF.
TEST CONDITIONS T
SYMBOL PARAMETER
t
PZL/tPLZ
t
PZL
t
THL
propagationdelay
CP to Q
n
propagationdelay
MR to Q
n
output transition
time
t
TLH
output transition
time
t
W
clock pulse width
HIGH or LOW
t
W
master reset
pulse width; LOW
t
rem
removal time
MR to CP
t
su
set-up time
Dnto CP
t
h
hold time
Dnto CP
f
max
maximum clock
pulse frequency
WAVEFORMS V
CC
see Figs 6 and 9 4.5 − 16 30 − 38 − 45 ns
see Figs 6 and 9 4.5 − 23 34 − 43 − 51 ns
see Figs 6 and 9 4.5 − 715−19 − 22 ns
see Figs 7 and 9 4.5 −−110 − 110 − 110 ns
see Figs 6 and 9 4.5 16 9 − 20 − 24 − ns
see Figs 7 and 9 4.5 16 8 − 20 − 24 − ns
see Figs 7 and 9 4.5 10 −2 − 13 − 15 − ns
see Figs 8 and 9 4.5 12 5 − 15 − 18 − ns
see Figs 8 and 9 4.5 3 −4 − 3 − 3 − ns
see Figs 6 and 9 4.5 30 56 − 24 − 20 − MHz
(°C)
amb
25 −40 to +85 −40 to +125
(V)
MIN. TYP. MAX. MIN. MAX. MIN. MAX.
74HCT7273
UNIT
1999 Oct 01 9
Page 10
Philips Semiconductors Product specification
Octal D-type flip-flop with reset; positive
edge-trigger; open drain outputs
AC WAVEFORMS
andbook, full pagewidth
V
I
CP input
Qn output
GND
V
OH
V
OL
V
M
t
W
t
PZL
90%
1/f
max
V
M
10% 10%
t
THL
t
74HCT7273
PLZ
MNA385
VM= 1.3 V; VI= GND to 3 V.
Fig.6 The clock (CP) to output (Qn) propagation delays, the clock pulse width, the output transition times and
maximum clock pulse frequency.
handbook, full pagewidth
MR input
CP input
Qn output
V
CC
GND
V
CC
GND
V
OH
V
OL
V
M
t
PHL
t
W
V
M
t
rem
10%
V
M
t
TLH
90%
MNA386
VM= 1.3 V; VI= GND to 3 V.
Fig.7 Master reset (MR) pulse width, the master reset to output (Qn) propagation delays and the master reset
to clock (CP).
1999 Oct 01 10
Page 11
Philips Semiconductors Product specification
Octal D-type flip-flop with reset; positive
edge-trigger; open drain outputs
GND
GND
V
OH
V
OL
V
I
V
M
t
su
V
I
V
M
handbook, full pagewidth
CP input
Dn input
Qn output
74HCT7273
t
su
t
h
t
h
MNA387
VM= 1.3 V; VI= GND to 3 V.
The shaded areas indicate when the input is permitted to change for predicable output performance.
Fig.8 Data set-up and hold times for the data input (Dn).
handbook, full pagewidth
V
CC
PULSE
GENERATOR
V
I
R
D.U.T.
T
V
O
C
L
TEST S1
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
open
V
CC
GND
Definitions for test circuit.
CL= load capacitance including jig and probe capacitance (See Chapter “AC characteristics”).
RT= termination resistance should be equal to the output impedance Zo of the pulse generator.
1000 Ω
MNA219
S1
V
CC
open
GND
Fig.9 Load circuit for switching times.
1999 Oct 01 11
Page 12
Philips Semiconductors Product specification
Octal D-type flip-flop with reset; positive
edge-trigger; open drain outputs
PACKAGE OUTLINES
SO20: plastic small outline package; 20 leads; body width 7.5 mm
D
c
y
Z
20
11
74HCT7273
SOT163-1
E
H
E
A
X
v M
A
pin 1 index
1
e
0 5 10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
mm
A
max.
2.65
0.10
A
1
0.30
0.10
0.012
0.004
A2A
2.45
2.25
0.096
0.089
0.25
0.01
b
0.49
0.36
p
cD
0.32
0.23
0.013
0.009
3
0.019
0.014
UNIT
inches
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
10
w M
b
p
scale
(1)E(1) (1)
13.0
12.6
0.51
0.49
eHELLpQ
7.6
1.27
7.4
0.30
0.050
0.29
10.65
10.00
0.419
0.394
A
2
0.055
A
1.4
Q
1
detail X
1.1
1.1
1.0
0.4
0.043
0.043
0.039
0.016
(A )
L
p
L
0.25
0.01
A
3
θ
0.25 0.1
0.01
0.004
ywv θ
Z
0.9
0.4
0.035
0.016
o
8
o
0
OUTLINE
VERSION
SOT163-1
IEC JEDEC EIAJ
075E04 MS-013AC
REFERENCES
1999 Oct 01 12
EUROPEAN
PROJECTION
ISSUE DATE
95-01-24
97-05-22
Page 13
Philips Semiconductors Product specification
Octal D-type flip-flop with reset; positive
edge-trigger; open drain outputs
DIP20: plastic dual in-line package; 20 leads (300 mil)
D
seating plane
L
Z
20
e
b
74HCT7273
SOT146-1
M
E
A
2
A
A
1
w M
b
1
11
c
(e )
1
M
H
pin 1 index
1
0 5 10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
UNIT
mm
inches
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
max.
OUTLINE
VERSION
SOT146-1
A
min.
A
1 2
max.
IEC JEDEC EIAJ
b
1.73
1.30
0.068
0.051
b
0.53
0.38
0.021
0.015
1
cD E e M
0.36
0.23
0.014
0.009
REFERENCES
(1) (1)
26.92
26.54
1.060
1.045
SC603
6.40
6.22
0.25
0.24
E
10
(1)
M
e
L
1
3.60
8.25
3.05
7.80
0.14
0.32
0.12
0.31
EUROPEAN
PROJECTION
H
E
10.0
0.2542.54 7.62
8.3
0.39
0.010.10 0.30
0.33
ISSUE DATE
92-11-17
95-05-24
Z
w
max.
2.04.2 0.51 3.2
0.0780.17 0.020 0.13
1999 Oct 01 13
Page 14
Philips Semiconductors Product specification
Octal D-type flip-flop with reset; positive
edge-trigger; open drain outputs
SOLDERING
Introduction to soldering surface mount packages
Thistextgivesaverybriefinsighttoacomplextechnology.
A more in-depth account of soldering ICs can be found in
our
“Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering isnot always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.
Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
totheprinted-circuitboardbyscreen printing, stencilling or
pressure-syringe dispensing before package placement.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
Wave soldering
Conventional single wave soldering is not recommended
forsurfacemountdevices(SMDs)orprinted-circuitboards
with a high component density, as solder bridging and
non-wetting can present major problems.
To overcome these problems the double-wave soldering
method was specifically developed.
74HCT7273
If wave soldering is used the following conditions must be
observed for optimal results:
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The footprint must incorporate solder thieves at the
downstream end.
• Forpackageswithleadsonfoursides,the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Manual soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
1999 Oct 01 14
Page 15
Philips Semiconductors Product specification
Octal D-type flip-flop with reset; positive
74HCT7273
edge-trigger; open drain outputs
Suitability of surface mount IC packages for wave and reflow soldering methods
PACKAGE
BGA, SQFP not suitable suitable
HLQFP, HSQFP, HSOP, SMS not suitable
(3)
PLCC
LQFP, QFP, TQFP not recommended
SSOP, TSSOP, VSO not recommended
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
, SO, SOJ suitable suitable
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
The package footprint must incorporate solder thieves downstream and at the side corners.
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”
WAVE REFLOW
(2)
(3)(4)
(5)
SOLDERING METHOD
(1)
suitable
suitable
suitable
.
Introduction to soldering through-hole mount packages
This text gives a brief insight to wave, dip and manual soldering. A more in-depth account of soldering ICs can be found
in our
“Data Handbook IC26; Integrated Circuit Packages”
Wave soldering is the preferred method for mounting of through-hole mount IC packages on a printed-circuit board.
Soldering by dipping or by solder wave
The maximum permissible temperature of the solder is 260 °C; solder at this temperature must not be in contact with the
joints for more than 5 seconds.
The total contact time of successive solder waves must not exceed 5 seconds.
The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the
specified maximum storage temperature (T
be necessary immediately after soldering to keep the temperature within the permissible limit.
Manual soldering
Applythe soldering iron (24 V or less) to the lead(s) of the package,eitherbelow the seating plane or not more than 2 mm
above it. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to 10 seconds. If
the bit temperature is between 300 and 400 °C, contact may be up to 5 seconds.
). If the printed-circuit board has been pre-heated, forced cooling may
stg(max)
(document order number 9398 652 90011).
1999 Oct 01 15
Page 16
Philips Semiconductors Product specification
Octal D-type flip-flop with reset; positive
74HCT7273
edge-trigger; open drain outputs
Suitability of through-hole mount IC packages for dipping and wave soldering methods
PACKAGE
DIPPING WAVE
DBS, DIP, HDIP, SDIP, SIL suitable suitable
Note
1. For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board.
DEFINITIONS
Data sheet status
Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
SOLDERING METHOD
(1)
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1999 Oct 01 16
Page 17
Philips Semiconductors Product specification
Octal D-type flip-flop with reset; positive
edge-trigger; open drain outputs
NOTES
74HCT7273
1999 Oct 01 17
Page 18
Philips Semiconductors Product specification
Octal D-type flip-flop with reset; positive
edge-trigger; open drain outputs
NOTES
74HCT7273
1999 Oct 01 18
Page 19
Philips Semiconductors Product specification
Octal D-type flip-flop with reset; positive
edge-trigger; open drain outputs
NOTES
74HCT7273
1999 Oct 01 19
Page 20
Philips Semiconductors – a w orldwide compan y
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For all other countries apply to: Philips Semiconductors,
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
© Philips Electronics N.V. SCA
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
1999
Internet: http://www.semiconductors.philips.com
68
Printed in The Netherlands 245002/01/pp20 Date of release: 1999 Oct 01 Document order number: 9397750 05733
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