Philips 74HCT540DB, 74HCT540D, 74HCT540U, 74HCT540N, 74HC540U Datasheet

DATA SH EET

Product specification
File under Integrated Circuits, IC06

December 1990

INTEGRATED CIRCUITS

74HC/HCT540

Octal buffer/line driver; 3-state;
inverting

For a complete data sheet, please also download:

•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

December 1990 2

Philips Semiconductors Product specification

Octal buffer/line driver; 3-state;
inverting

74HC/HCT540

FEATURES

• Inverting outputs

• Output capability: bus driver

• ICC category: MSI

GENERAL DESCRIPTION

The 74HC/HCT540 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.

The 74HC/HCT540 are octal inverting buffer/line drivers
with 3-state outputs. The 3-state outputs are controlled by
the output enable inputs

OE1and OE2.
A HIGH on OEncauses the outputs to assume a high
impedance OFF-state.
The “540” is identical to the “541” but has inverting outputs.

QUICK REFERENCE DATA

GND = 0 V; T

amb

= 25 °C; tr= tf= 6 ns

Notes

1. C

PD

is used to determine the dynamic power dissipation (PDin µW):

PD= CPD× V

CC

2

× fi+∑(CL× V

CC

2

× fo) where:
fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× V

CC

2

× fo) = sum of outputs
CL= output load capacitance in pF
VCC= supply voltage in V

2. For HC the condition is VI= GND to V

CC

For HCT the condition is VI= GND to VCC− 1.5 V

ORDERING INFORMATION

See

“74HC/HCT/HCU/HCMOS Logic Package Information”

.

SYMBOL PARAMETER CONDITIONS

TYPICAL

UNIT

HC HCT

t

PHL

/ t

PLH

propagation delay Anto Y

n

CL= 15 pF; VCC= 5 V 9 11 ns

C

I

input capacitance 3.5 3.5 pF

C

PD

power dissipation capacitance per buffer notes 1 and 2 39 44 pF

December 1990 3

Philips Semiconductors Product specification

Octal buffer/line driver; 3-state; inverting 74HC/HCT540

PIN DESCRIPTION

PIN NO. SYMBOL NAME AND FUNCTION

1, 19

OE1, OE

2

output enable input (active LOW)

2, 3, 4, 5, 6, 7, 8, 9 A

0

to A

7

data inputs
10 GND ground (0 V)
18, 17, 16, 15, 14, 13, 12, 11

Y0to Y

7

bus outputs
20 V

CC

positive supply voltage

Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.