Philips 74HCT534U, 74HCT534N, 74HCT534D, 74HC534U, 74HC534N Datasheet

INTEGRATED CIRCUITS

DATA SHEET

For a complete data sheet, please also download:

∙The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

∙The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

∙The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT534

Octal D-type flip-flop; positive edge-trigger; 3-state; inverting

Product specification

1998 Apr 10

Supersedes data of September 1993

File under Integrated Circuits, IC06

Philips Semiconductors	Product specification

Octal D-type flip-flop; positive edge-trigger;

74HC/HCT534

3-state; inverting

FEATURES

·3-state inverting outputs for bus oriented applications

·8-bit positive, edge-triggered register

·Common 3-state output enable input

·Output capability: bus driver

·ICC category: MSI.

GENERAL DESCRIPTION

The 74HC/HCT534 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.

QUICK REFERENCE DATA

GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns

The 74HC/HCT534 are octal D-type flip-flops featuring separate D-type inputs for each flip-flop and inverting 3-state outputs for bus oriented applications. A clock (CP) and an output enable (OE) input are common to all flip-flops.

The 8 flip-flops will store the state of their individual D-inputs that meet the set-up and hold times requirements on the LOW-to-HIGH CP transition. When OE is LOW, the contents of the 8 flip-flops are available at the outputs. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops.

The “534” is functionally identical to the “374”, but has inverted outputs.

	SYMBOL	PARAMETER			CONDITIONS	TYPICAL		UNIT
						HC	HCT
	tPHL/ tPLH	propagation delay CP to		n	CL = 15 pF; VCC = 5 V	12	13	ns
			Q
	fmax	maximum clock frequency				61	40	MHz
	CI	input capacitance				3.5	3.5	pF
	CPD	power dissipation capacitance per flip-flop			notes 1 and 2	19	19	pF

Notes

1. CPD is used to determine the dynamic power dissipation (PD in mW): PD = CPD ´ VCC2 ´ fi + å (CL ´ VCC2 ´ fo) where:

fi = input frequency in MHz.

fo = output frequency in MHz.

å (CL ´ VCC2 ´ fo) = sum of outputs.

CL = output load capacitance in pF.

VCC = supply voltage in V.

2. For HC the condition is VI = GND to VCC; for HCT the condition is VI = GND to VCC - 1.5 V.

ORDERING INFORMATION

TYPE		PACKAGE
NUMBER	NAME	DESCRIPTION	VERSION
74HC534	SO20	plastic small outline package; 20 leads; body width 7.5 mm	SOT163-1
74HC534	DIP20	plastic dual in-line package; 20 leads (300 mil)	SOT146-1
74HCT534	SO20	plastic small outline package; 20 leads; body width 7.5 mm	SOT163-1
74HCT534	DIP20	plastic dual in-line package; 20 leads (300 mil)	SOT146-1

1998 Apr 10

2

Philips Semiconductors	Product specification

Octal D-type flip-flop; positive edge-trigger;

74HC/HCT534

3-state; inverting

PIN DESCRIPTION

PIN NO.					SYMBOL			NAME AND FUNCTION
1								3-state output enable input (active LOW)
			OE
2, 5, 6, 9, 12, 15, 16, 19							7	3-state outputs
		Q		0 to		Q
3, 4, 7, 8, 13, 14, 17, 18			D0 to D7					data inputs
10		GND						ground (0 V)
11		CP						clock input (LOW-to-HIGH, edge-triggered)
20		VCC						positive supply voltage

page

OE			1			20 VCC													page		1
																						EN
									page						11					11
Q0			2	19			Q7																	C1
											3		CP					2
	D0		3			18	D7					D0				Q0				3								2
											4							5
																						1D
												D1				Q1
	D1		4	17			D6			7							6			4								5
												D2				Q2
Q1			5	16			Q6				8	D3				Q3		9		7								6
				534
										13							12
Q2 6						15	Q5					D4				Q4				8								9
											14							15
	D2 7						D5					D5				Q5				13								12
						14				17							16
	D3		8				D4					D6				Q6				14								15
				13						18							19
												D7				Q7
			9										OE							17								16
Q3				12			Q4
															1		MGM955			18								19
GND 10							CP
					11
																										MGM956
				MGM954
	Fig.1			Pin configuration.						Fig.2 Logic symbol.										Fig.3		IEC logic symbol.

1998 Apr 10

3

Philips Semiconductors	Product specification

Octal D-type flip-flop; positive edge-trigger;

74HC/HCT534

3-state; inverting

handbook, halfpage

	D0
3										Q0			2
	D1
4											Q	1	5
	D2
7										Q2			6
	D3
8				FF1			3-STATE			Q3			9
	D4			to
13							OUTPUTS			Q4			12
				FF8
	D5
14											Q	5	15
	D6
17											Q	6	16
	D7
18											Q	7	19
11	CP
1	OE

MGM957

Fig.4

Functional diagram.

FUNCTION TABLE

OPERATING MODES

INPUTS

INTERNAL FLIP-FLOPS

OUTPUTS

OE

CP

Dn

Q

0 to

Q

7

load and read register

L

−

l

L

H

L

−

h

H

L

load register and disable outputs

H

−

l

L

Z

H

−

h

H

Z

Note

1.H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition

L = LOW voltage level; I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition Z = high impedance OFF-state; − = LOW-to-HIGH clock transition.

1998 Apr 10

4