Philips 74HCT4538U, 74HCT4538N, 74HCT4538DB, 74HCT4538D, 74HC4538DB Datasheet

INTEGRATED CIRCUITS

DATA SHEET

For a complete data sheet, please also download:

∙The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

∙The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

∙The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT4538

Dual retriggerable precision monostable multivibrator

Product specification			September 1993
File under Integrated Circuits, IC06

Philips Semiconductors	Product specification

Dual retriggerable precision monostable

74HC/HCT4538

multivibrator

FEATURES

·Separate reset inputs

·Triggering from leading or trailing edge

·Output capability: standard

·ICC category: MSI

·Power-on reset on-chip

GENERAL DESCRIPTION

The 74HC/HCT4538 are high-speed Si-gate CMOS devices and are pin compatible with “4538” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A.

The 74HC/HCT4538 are dual retriggerable-resettable monostable multivibrators. Each multivibrator has an active LOW trigger/retrigger input (nA0), an active HIGH

QUICK REFERENCE DATA

GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns

trigger/retrigger input (nA1) , an overriding active LOW

direct reset input (nRD), an output (nQ) and its complement

(nQ), and two pins (nCTC and nRCTC) for connecting the external timing components Ct and Rt. Typical pulse width variation over temperature range is ± 0.2%.

The “4538” may be triggered by either the positive or the negative edges of the input pulse. The duration and accuracy of the output pulse are determined by the external timing components Ct and Rt. The output pulse width (T) is equal to 0.7 ´ Rt ´ Ct. The linear design techniques guarantee precise control of the output pulse width.

A LOW level at nRD terminates the output pulse immediately.

Schmitt-trigger action in the trigger inputs makes the circuit highly tolerant to slower rise and fall times.

	SYMBOL	PARAMETER					CONDITIONS	TYPICAL		UNIT
								HC	HCT
	tPHL/ tPLH
		propagation delay nA		0, nA1 to nQ, nQ			CL = 15 pF; VCC = 5 V	27	30	ns
	CI	input capacitance						3.5	3.5	pF
	CPD	power dissipation capacitance per multivibrator					notes 1 and 2	136	138	pF

Notes

1. CPD is used to determine the dynamic power dissipation (PD in mW):

PD = CPD ´ VCC2 ´ fi + å (CL ´ VCC2 ´ fo) +

+ 0.48 ´ CEXT ´ VCC2 ´ fo + D ´ 0.8 ´ VCC where:

fi = input frequency in MHz

fo = output frequency in MHz

å (CL ´ VCC2 ´ fo) = sum of outputs

CL = output load capacitance in pF

VCC = supply voltage in V

D = duty factor in %

CEXT = timing capacitance in pF

2.For HC the condition is VI = GND to VCC

For HCT the condition is VI = GND to VCC - 1.5 V

ORDERING INFORMATION

See “74HC/HCT/HCU/HCMOS Logic Package Information”.

September 1993

2

Philips Semiconductors	Product specification

Dual retriggerable precision monostable

74HC/HCT4538

multivibrator

PIN DESCRIPTION

PIN NO.	SYMBOL									NAME AND FUNCTION
1, 15	1CTC, 2CTC									external capacitor connections
2, 14	1RCTC, 2RCTC									external resistor/capacitor connections
3, 13
	1R		D, 2RD							direct reset inputs (active LOW)
4, 12	1A1, 2A1									trigger inputs (LOW-to-HIGH, edge-triggered)
5, 11
	1A		0, 2A0							trigger inputs (HIGH-to-LOW, edge-triggered)
6, 10	1Q, 2Q									pulse outputs
7, 9										complementary pulse outputs
	1Q,			2Q
8	GND									ground (0 V)
16	VCC									positive supply voltage

Fig.1 Pin configuration.		Fig.2 Logic symbol.		Fig.3 IEC logic symbol.

September 1993

3

Philips Semiconductors	Product specification

Dual retriggerable precision monostable

74HC/HCT4538

multivibrator

Fig.4 Functional diagram.

FUNCTION TABLE

INPUTS

OUTPUTS

nA

0

nA1

nRD

nQ

nQ

↓

L

H

H

−

H

X

X

L

L

H

Notes

1.H = HIGH voltage level L = LOW voltage level X = don’t care

− = LOW-to-HIGH transition ↓ = HIGH-to-LOW transition

= one HIGH level output pulse = one LOW level output pulse

(1) Connect CTC (pins 1 and 15) to GND (pin 8).

Fig.5 Connection of the external timing components Rt and Ct.

(1)Positive edge triggering.

(2)Positive edge retriggering (pulse lengthening).

(3)Negative edge triggering.

(4)Reset (pulse shortening).

(5)Vref1 and Vref2 are internal reference voltages.

(6)T = 0.7 × Rt × Ct (see also Fig.5).

Fig.6 Timing diagram.

September 1993

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