Philips 74HCT4020N, 74HCT4020D, 74HCT4020U, 74HCT4020PW, 74HC4020U Datasheet
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INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
∙The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
∙The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
∙The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT4020
14-stage binary ripple counter
Product specification |
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September 1993 |
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File under Integrated Circuits, IC06 |
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Philips Semiconductors |
Product specification |
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14-stage binary ripple counter |
74HC/HCT4020 |
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FEATURES
·Output capability: standard
·ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT4020 are high-speed Si-gate CMOS devices and are pin compatible with the “4020” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
The 74HC/HCT4020 are 14-stage binary ripple counters with a clock input (CP), an overriding asynchronous master reset input (MR) and twelve fully buffered parallel outputs (Q0, Q3 to Q13).
The counter is advanced on the HIGH-to-LOW transition of CP.
A HIGH on MR clears all counter stages and forces all outputs LOW, independent of the state of CP.
Each counter stage is a static toggle flip-flop.
SYMBOL |
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PARAMETER |
CONDITIONS |
TYPICAL |
UNIT |
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HC |
HCT |
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tPHL/ tPLH |
propagation delay |
CL = 15 pF; VCC = 5 V |
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CP |
to Q0 |
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11 |
15 |
ns |
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Qn to Qn+1 |
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6 |
6 |
ns |
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MR to Qn |
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17 |
19 |
ns |
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fmax |
maximum clock frequency |
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101 |
52 |
MHz |
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CI |
input capacitance |
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3.5 |
3.5 |
pF |
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CPD |
power dissipation capacitance per package |
notes 1 and 2 |
19 |
20 |
pF |
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Notes
1. CPD is used to determine the dynamic power dissipation (PD in mW): PD = CPD ´ VCC2 ´ fi + å (CL ´ VCC2 ´ fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
å (CL ´ VCC2 ´ fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC - 1.5 V
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
September 1993 |
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Philips Semiconductors |
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Product specification |
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14-stage binary ripple counter |
74HC/HCT4020 |
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PIN DESCRIPTION |
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PIN NO. |
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SYMBOL |
NAME AND FUNCTION |
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9, 7, 5, 4, 6, 13, 12, 14, 15, 1, 2, 3 |
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Q0, Q3 to Q13 |
parallel outputs |
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8 |
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GND |
ground (0 V) |
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10 |
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clock input (HIGH-to-LOW, edge-triggered) |
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CP |
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11 |
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MR |
master reset input (active HIGH) |
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16 |
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VCC |
positive supply voltage |
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page |
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RCTR14 |
9 |
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0 |
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7 |
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3 |
5 |
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CT=0 |
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4 |
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6 |
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13 |
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CT |
12 |
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14 |
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15 |
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1 |
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2 |
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13 |
3 |
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MGA829 |
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Fig.1 Pin configuration. |
Fig.2 Logic symbol. |
Fig.3 IEC logic symbol. |
September 1993 |
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