INTEGRATED CIRCUITS
DATA SH EET
For a complete data sheet, please also download:
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC4050
Hex high-to-low level shifter
Product specification
File under Integrated Circuits, IC06
December 1990
Philips Semiconductors Product specification
Hex high-to-low level shifter 74HC4050
FEATURES
• Output capability: standard
• ICC category: SSI
therefore be used. This feature enables the non-inverting
buffers to be used as logic level translators, which will
convert high level logic to low level logic, while operating
from a low voltage power supply. For example 15 V logic
(“4000B series”) can be converted down to 2 V logic.
GENERAL DESCRIPTION
The 74HC4050 is a high-speed Si-gate CMOS device and
The actual input switch level remains related to the V
and is the same as mentioned in the family characteristics.
is pin compatible with the “4050” of the “4000B” series. It
is specified in compliance with JEDEC standard no. 7A.
The 74HC4050 provides six non-inverting buffers with a
APPLICA TIONS
• Converting 15 V logic (“4000B” series) down to 2 V logic.
modified input protection structure, which has no diode
connected to V
. Input voltages of up to 15 V may
CC
QUICK REFERENCE DATA
GND = 0 V; T
=25°C; tr=tf= 6 ns
amb
SYMBOL PARAMETER CONDITIONS
t
PHL
C
C
I
PD
/ t
PLH
propagation delay nA to nY CL= 15 pF; VCC= 5 V 7 ns
input capacitance 3.5 pF
power dissipation capacitance per buffer note 1 14 pF
CC
TYPICAL
UNIT
HC
Notes
1. C
is used to determine the dynamic power dissipation (PD in µW):
PD
PD=CPD× V
2
× fi+∑ (CL× V
CC
2
× fo) where:
CC
fi= input frequency in MHz
fo= output frequency in MHz
CL= output load capacitance in pF
VCC= supply voltage in V
∑ (CL× V
2
× fo) = sum of outputs
CC
ORDERING INFORMATION
“74HC/HCT/HCU/HCMOS Logic Package Information”
See
.
December 1990 2
Philips Semiconductors Product specification
Hex high-to-low level shifter 74HC4050
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION
1V
2, 4, 6, 10, 12, 15 1Y to 6Y data outputs
3, 5, 7, 9, 11, 14 1A to 6A data inputs
8 GND ground (0 V)
13, 16 n.c. not connected
CC
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol. Fig.3 IEC logic symbol.
December 1990 3