Philips 74HCT4040U, 74HCT4040PW, 74HCT4040N, 74HCT4040D, 74HC4040U Datasheet

DATA SH EET

Product specification
File under Integrated Circuits, IC06

December 1990

INTEGRATED CIRCUITS

74HC/HCT4040

12-stage binary ripple counter

For a complete data sheet, please also download:

•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

December 1990 2

Philips Semiconductors Product specification

12-stage binary ripple counter 74HC/HCT4040

FEATURES

• Output capability: standard

• ICC category: MSI

GENERAL DESCRIPTION

The 74HC/HCT4040 are high-speed Si-gate CMOS
devices and are pin compatible with “4040” of the “4000B”
series. They are specified in compliance with JEDEC
standard no. 7A.

The 74HC/HCT4040 are 12-stage binary ripple counters
with a clock input (

CP), an overriding asynchronous

master reset input (MR) and twelve parallel outputs

(Q0 to Q11). The counter advances on the HIGH-to-LOW
transition of CP.

A HIGH on MR clears all counter stages and forces all
outputs LOW, independent of the state of CP.

Each counter stage is a static toggle flip-flop.

APPLICATIONS

• Frequency dividing circuits

• Time delay circuits

• Control counters

QUICK REFERENCE DATA

GND = 0 V; T

amb

=25°C; tr=tf= 6 ns

Notes

1. C

PD

is used to determine the dynamic power dissipation (PD in µW):

PD=CPD× V

CC

2

× fi+∑(CL× V

CC

2

× fo) where:
fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× V

CC

2

× fo) = sum of outputs
CL= output load capacitance in pF
VCC= supply voltage in V

2. For HC the condition is VI= GND to V

CC

For HCT the condition is VI= GND to VCC− 1.5 V

ORDERING INFORMATION

See

“74HC/HCT/HCU/HCMOS Logic Package Information”

.

SYMBOL PARAMETER CONDITIONS

TYPICAL

UNIT

HC HCT

t

PHL

/ t

PLH

propagation delay CL= 15 pF; VCC=5 V

CP to Q

0

14 16 ns

Q

n

to Q

n+1

88ns

f

max

maximum clock frequency 90 79 MHz

C

I

input capacitance 3.5 3.5 pF

C

PD

power dissipation capacitance per package notes 1 and 2 20 20 pF

December 1990 3

Philips Semiconductors Product specification

12-stage binary ripple counter 74HC/HCT4040

PIN DESCRIPTION

PIN NO. SYMBOL NAME AND FUNCTION

8 GND ground (0 V)
9, 7, 6, 5, 3, 2, 4, 13, 12, 14, 15, 1 Q

0

to Q

11

parallel outputs

10

CP clock input (HIGH-to-LOW, edge-triggered)
11 MR master reset input (active HIGH)
16 V

CC

positive supply voltage

Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.