December 1990 2
Philips Semiconductors Product specification
Quad bilateral switches 74HC/HCT4016
FEATURES
• Low “ON” resistance:
160 Ω (typ.) at VCC= 4.5 V
120 Ω (typ.) at VCC= 6.0 V
80 Ω (typ.) at VCC= 9.0 V
• Individual switch controls
• Typical “break before make” built in
• Output capability: non-standard
• ICC category: SSI
GENERAL DESCRIPTION
The 74HC/HCT4016 are high-speed Si-gate CMOS
devices and are pin compatible with the “4016” of the
“4000B” series. They are specified in compliance with
JEDEC standard no. 7A.
The 74HC/HCT4016 have four independent analog
switches (transmission gates).
Each switch has two input/output terminals (Y
n,Zn
) and an
active HIGH enable input (En). When Enis connected to
VCC, a low bidirectional path between Ynand Znis
established (ON condition). When Enis connected to
ground (GND), the switch is disabled and a high
impedance between Ynand Znis established (OFF
condition).
Current through a switch will not cause additional
VCCcurrent provided the voltage at the terminals of the
switch is maintained within the supply voltage range;
VCC>> (VY,VZ) >> GND. Inputs Ynand Znare electrically
equivalent terminals.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25 °C; tr= tf= 6 ns
Notes
1. C
PD
is used to determine the dynamic power dissipation (PDin µW):
PD= CPD× V
CC
2
× fi+∑{(CL+CS)×V
CC
2
× fo} where:
fi= input frequency in MHz
fo= output frequency in MHz
∑ {(CL+ CS) × V
CC
2
× fo} = sum of outputs
CL= output load capacitance in pF
CS= max. switch capacitance in pF
VCC= supply voltage in V
2. For HC the condition is VI= GND to V
CC
For HCT the condition is VI= GND to VCC− 1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
SYMBOL PARAMETER CONDITIONS
TYPICAL
UNIT
HC HCT
t
PZH
/ t
PZL
turn “ON” time Ento V
OS
CL= 15 pF; RL=1 kΩ;
VCC= 5 V
16 17 ns
t
PHZ
/ t
PLZ
turn “OFF” time Ento V
OS
14 20 ns
C
I
input capacitance 3.5 3.5 pF
C
PD
power dissipation capacitance per switch notes 1 and 2 12 12 pF
C
S
max. switch capacitance 5 5 pF