Philips 74HCT40105U, 74HCT40105DB, 74HCT40105D, 74HC40105U, 74HC40105PW Datasheet

...

DATA SH EET

Product speciﬁcation Supersedes data of December 1990 File under Integrated Circuits, IC06

1998 Jan 23

INTEGRATED CIRCUITS

74HC/HCT40105

4-bit x 16-word FIFO register

For a complete data sheet, please also download:

•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

1998 Jan 23 2

Philips Semiconductors Product speciﬁcation

4-bit x 16-word FIFO register 74HC/HCT40105

FEATURES

• Independent asynchronous inputs and outputs

• Expandable in either direction

• Reset capability

• Status indicators on inputs and outputs

• 3-state outputs

• Output capability: standard

• ICCcategory: MSI

GENERAL DESCRIPTION

The 74HC/HCT40105 are high-speed Si-gate CMOS devices and are pin compatible with the “40105” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A.

The 74HC/HCT40105 are first-in/first-out (FIFO) “elastic” storage registers that can store sixteen 4-bit words. The “40105” is capable of handling input and output data at

different shifting rates. This feature makes it particularly useful as a buffer between asynchronous systems. Each word position in the register is clocked by a control flip-flop, which stores a marker bit. A “1” signifies that the position’s data is filled and a “0” denotes a vacancy in that position. The control flip-flop detects the state of the preceding flip-flop and communicates its own status to the succeeding flip-flop. When a control flip-flop is in the “0” state and sees a “1” in the preceding flip-flop, it generates a clock pulse that transfers data from the preceding four data latches into its own four data latches and resets the preceding flip-flop to “0”. The first and last control flip-flops have buffered outputs. Since all empty locations “bubble” automatically to the input end, and all valid data ripples through to the output end, the status of the first control flip-flop (data-in ready output - DIR) indicates if the FIFO is full, and the status of the last flip-flop (data-out ready output - DOR) indicates if the FIFO contains data. As the earliest data is removed from the bottom of the data stack (output end), all data entered later will automatically ripple toward the output.

QUICK REFERENCE DATA

GND = 0 V; T

amb

= 25 °C; tr= tf= 6 ns

Notes

1. C

is used to determine the dynamic power dissipation (PDin µW):

PD= CPD× V

× fi+∑(CL× V

× fo) where: fi= input frequency in MHz. fo= output frequency in MHz. ∑ (CL× V

× fo) = sum of outputs CL= output load capacitance in pF VCC= supply voltage in V

2. For HC the condition is VI= GND to V

For HCT the condition is VI= GND to VCC− 1.5

SYMBOL PARAMETER CONDITIONS

TYP.

UNIT

HC HCT

PHL

/ t

PLH

propagation delay CL= 15 pF; VCC=5 V

MR to DIR, DOR 16 15 ns SO to Q

37 35 ns

PHL

propagation delay

SI to DIR 16 18 ns SO to DOR 17 18 ns

max

maximum clock frequency 33 31 MHz

input capacitance 3.5 3.5 pF

power dissipation capacitance per package notes 1 and 2 134 145 pF

1998 Jan 23 3

Philips Semiconductors Product speciﬁcation

4-bit x 16-word FIFO register 74HC/HCT40105

ORDERING INFORMATION

PIN DESCRIPTION

TYPE NUMBER

PACKAGE

NAME DESCRIPTION VERSION

74HC(T)40105N DIP16 plastic dual in-line package; 16 leads (300 mil); long body SOT38-1 74HC(T)40105D SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 74HC(T)40105DB SSOP16 plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1 74HC(T)40105PW TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1

PIN NO. SYMBOL NAME AND FUNCTION

OE output enable input (active LOW) 2 DIR data-in ready output 3 SI shift-in input (LOW-to-HIGH, edge-triggered) 4, 5, 6, 7 D

to D

parallel data inputs 8 GND ground (0 V) 9 MR asynchronous master reset input (active HIGH) 13, 12, 11, 10 Q

to Q

3-state data outputs 14 DOR data-out ready output 15

SO shift-out input (HIGH-to-LOW, edge-triggered)

16 V

positive supply voltage

Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.

1998 Jan 23 4

Philips Semiconductors Product speciﬁcation

4-bit x 16-word FIFO register 74HC/HCT40105

INPUT AND OUTPUTS Data inputs (D

to D3)

As there is no weighting of the inputs, any input can be assigned as the MSB. The size of the FIFO memory can be reduced from the 4 × 16 configuration, i.e. 3 × 16, down to 1 × 16, by tying unused data input pins to V

or GND.

Data outputs (Q

to Q3)

As there is no weighting of the outputs, any output can be assigned as the MSB. The size of the FIFO memory can be reduced from the 4 × 16 configuration as described for data inputs. In a reduced format, the unused data outputs pins must be left open circuit.

Master-reset (MR)

When MR is HIGH, the control functions within the FIFO are cleared, and date content is declared invalid. The data-in ready (DIR) flag is set HIGH and the data-out-ready (DOR) flag is set LOW. The output stage remains in the state of the last word that was shifted out, or in the random state existing at power-up.

Status ﬂag outputs (DIR, DOR)

Indication of the status of the FIFO is given by two status flags, data-in-ready (DIR) and data-out-ready (DOR):

DIR = HIGH indicates the input stage is empty and ready to accept valid data;

DIR = LOW indicates that the FIFO is full or that a previous shift-in operation is not complete (busy);

DOR = HIGH assures valid data is present at the outputs Q

to Q3(does not indicate that new data is awaiting transfer into the output stage);

DOR = LOW indicates the output stage is busy or there is no valid data.

Shift-in control (SI)

Data is loaded into the input stage on a LOW-to-HIGH transition of SI. It also triggers an automatic data transfer process (ripple through). If SI is held HIGH during reset, data will be loaded at the falling edge of the MR signal.

Shift-out control (

SO)

A HIGH-to-LOW transition of SO causes the DOR flags to go LOW. A HIGH-to-LOW transition of SO causes upstream data to move into the output stage, and empty locations to move towards the input stage (bubble-up).

Output enable (

OE)

The outputs Q0to Q3are enabled when OE = LOW. When OE = HIGH the outputs are in the high impedance OFF-state.

FUNCTIONAL DESCRIPTION Data input

Following power-up, the master-reset (MR) input is pulsed HIGH to clear the FIFO memory (see Fig.8). The data-in-ready flag (DIR = HIGH) indicates that the FIFO input stage is empty and ready to receive data. When DIR is valid (HIGH), data present at D

to D3can be shifted-in using the SI control input. With SI = HIGH, data is shifted into the input stage and a busy indication is given by DIR going LOW.

The data remains at the first location in the FIFO until DIR is set to HIGH and data moves through the FIFO to the output stage, or to the last empty location. If the FIFO is not full after the SI pulse, DIR again becomes valid (HIGH) to indicate that space is available in the FIFO. The DIR flag remains LOW if the FIFO is full (see Fig.6). The SI use must be made

LOW in order to complete the shift-in process.

With the FIFO full, SI can be held HIGH until a shift-out (

SO) pulse occurs. Then, following a shift-out of data, an empty location appears at the FIFO input and DIR goes HIGH to allow the next data to be shifted-in. This remains at the first FIFO location until SI goes LOW (see Fig.7).

Data transfer

After data has been transferred from the input stage of the FIFO following SI = LOW, data moves through the FIFO asynchronously and is stacked at the output end of the register. Empty locations appear at the input end of the FIFO as data moves through the device.

Data output

The data-out-ready flag (DOR = HIGH) indicates that there is valid data at the output (Q

to Q3). The initial master-reset at power-on (MR = HIGH) sets DOR to LOW (see Fig.8). After MR = LOW, data shifted into the FIFO moves through to the output stage causing DOR to go HIGH.

As the DOR flag goes HIGH, data can be shifted-out using the SO = HIGH, data in the output stage is shifted out and a busy indication is given by DOR going LOW. When SO is made LOW, data moves through the FIFO to fill the output stage and an empty location appears at the input stage. When the output stage is filled DOR goes HIGH, but if the last of the valid data has been shifted-out leaving the FIFO empty the DOR flag remains LOW (see Fig.9). With the FIFO empty, the last word that was shifted-out is latched at the output Q0to Q3.

With the FIFO empty, the SO input can be held HIGH until the SI control input is used. Following an SI pulse,

1998 Jan 23 5

Philips Semiconductors Product speciﬁcation

4-bit x 16-word FIFO register 74HC/HCT40105

data moves through the FIFO to the output stage, resulting in the DOR flag pulsing HIGH and a shift-out of data occurring. The SO control must be made LOW before additional data can be shifted-out (see Fig.10).

High-speed burst mode

If it is assumed that the shift-in/shift-out pulses are not applied until the respective status flags are valid, it follows that the shift-in/shift-out rates are determined by the status flags. However, without the status flags a high-speed burst mode can be implemented. In this mode, the burst-in/ burst-out rates are determined by the pulse widths of the shift-in/shift-out inputs and burst rates of 35 MHz can be obtained. Shift

pulses can be applied without regard to the status flags but shift-in pulses that would overflow the storage capacity of the FIFO are not allowed (see Figs 11 and 12).

Expanded format

With the addition of a logic gate, the FIFO is easily expanded to increase word length (see Fig.17). The basic operation and timing are identical to a single FIFO, with the exception of an additional gate delay on the flag outputs. If during application, the following occurs:

• SI is held HIGH when the FIFO is empty, some additional logic is required to produce a composite DIR pulse (see Figs 7 and 18).

Due to the part-to-part spread of the ripple through time, the SI signals of FIFOAand FIFOBwill not always coincide and the AND-gate will not produce a composite flag signal. The solution is given in Fig.18.

The “40105” is easily cascaded to increase the word capacity and no external components are needed. In the cascaded configuration, all necessary communications and timing are performed by the FIFOs. The intercommunication speed is determined by the minimum flag pulse widths and the flag delays. The data rate of cascaded devices is typically 25 MHz. Word-capacity can be expanded to and beyond 32-words × 4-bits (see Fig.19).

1998 Jan 23 6

Philips Semiconductors Product speciﬁcation

4-bit x 16-word FIFO register 74HC/HCT40105

Fig.4 Functional diagram.

Fig.5 Logic diagram.

(see control flip-flops) (1) LOW on S input of FF1, and FF5 will set Q output to HIGH independent of state on R input. (2) LOW on R input of FF2, FF3 and FF4 will set Q output to LOW independent of state on S input.

1998 Jan 23 7

Philips Semiconductors Product speciﬁcation

4-bit x 16-word FIFO register 74HC/HCT40105

DC CHARACTERISTICS FOR 74HC

For the DC characteristics see

“74HC/HCT/HCU/HCMOS Logic Family Specifications”

Output capability: standard ICCcategory: MSI

AC CHARACTERISTICS FOR 74HC

GND = 0 V; t

= tf= 6 ns; CL= 50 pF

SYMBOL PARAMETER

amb

(°C)

UNIT

TEST CONDITIONS

74HC

(V)

WAVEFORMS

+25 −40 to +85 −40 to +125

min. typ. max. min. max. min. max.

PHL

/ t

PLH

propagation delay

MR to DIR, DOR

52 175 220 265 ns 2.0 Fig.8 19 35 44 53 4.5 15 30 37 45 6.0

PHL

propagation delay

SI to DIR

52 210 265 315 ns 2.0 Fig.6 19 42 53 63 4.5 15 36 45 54 6.0

PHL

propagation delay

SO to DOR

55 210 265 315 ns 2.0 Fig.9 20 42 53 63 4.5 16 36 45 54 6.0

PHL

/ t

PLH

propagation delay

SO to Q

116 400 500 600 ns 2.0 Fig.14 42 80 100 120 4.5 34 68 85 102 6.0

PLH

propagation delay/

ripple through delay SI to DOR

564 2000 2500 3000 ns 2.0 Fig.10 205 400 500 600 4.5 165 340 425 510 6.0

PLH

propagation delay/

bubble-up delay SO to DIR

701 2500 3125 3750 ns 2.0 Fig.7 255 500 625 750 4.5 204 425 532 638 6.0

PZH

/ t

PZL

3-state output enable time

OE to Q

41 150 190 225 ns 2.0 Fig.16 15 30 38 45 4.5 12 26 33 38 6.0

PHZ

/ t

PLZ

3-state output disable time

OE to Q

41 140 175 210 ns 2.0 Fig.16 15 28 35 42 4.5 12 24 30 36 6.0

THL

/ t

TLH

output transition time 19 75 95 110 ns 2.0 Fig.14

7 15 19 22 4.5 6 13 16 19 6.0

SI pulse width

HIGH or LOW

80 19 100 120 ns 2.0 Fig.6 16 7 20 24 4.5 14 6 17 20 6.0

1998 Jan 23 8

Philips Semiconductors Product speciﬁcation

4-bit x 16-word FIFO register 74HC/HCT40105

SO pulse width

HIGH or LOW

120 39 150 180 ns 2.0 Fig.9 24 14 30 36 4.5 20 11 26 31 6.0

DIR pulse width

HIGH

12 58 180 10 225 10 270 ns 2.0 Fig.7 6 21 36 5 45 5 54 4.5 5 17 31 4 38 4 46 6.0

DOR pulse width

LOW

12 55 170 10 215 10 255 ns 2.0 Fig.9 6 20 34 5 43 5 51 4.5 5 16 29 4 37 4 43 6.0

MR pulse width

HIGH

80 22 100 120 ns 2.0 Fig.8 16 8 20 24 4.5 14 6 17 20 6.0

rem

removal time

MR to SI

50 14 65 75 ns 2.0 Fig.15 10 5 13 15 4.5 9 4 11 13 6.0

set-up time

Dn to SI

−5 −39 −5 −5 ns 2.0 Fig.13

−5 −14 −5 −5 4.5

−5 −11 −5 −5 6.0

hold time

Dnto SI

125 44 155 190 ns 2.0 Fig.13 25 16 31 38 4.5 21 13 26 32 6.0

max

maximum pulse frequency

SI, SO using ﬂags or burst mode

3.6 10 2.8 2.4 MHz 2.0 Fig.6, 9, 11 and 12

18 30 14 12 4.5 21 36 16 14 6.0

max

maximum pulse frequency

SI, SO cascaded

3.6 10 2.8 2.4 MHz 2.0 Figs 6 and 9

18 30 14 12 4.5 21 36 16 14 6.0

SYMBOL PARAMETER

amb

(°C)

UNIT

TEST CONDITIONS

74HC

(V)

WAVEFORMS

+25 −40 to +85 −40 to +125

min. typ. max. min. max. min. max.

+ 17 hidden pages