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I74F109D |
INTEGRATED CIRCUITS |
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74F109
Positive J-K positive edge-triggered flip-flops
Product specification |
1990 Oct 23 |
IC15 Data Handbook
m n r
Philips Semiconductors |
Product specification |
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Postive J- |
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positive edge-triggered flip-flops |
74F109 |
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K |
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FEATURE
•Industrial temperature range available (±40°C to +85°C)
DESCRIPTION
The 74F109 is a dual positive edge-triggered JK-type flip-flop
featuring individual J, K, clock, set, and reset inputs; also true and complementary outputs. Set (SD) and reset (RD) are asynchronous active low inputs and operate independently of the clock (CP) input.
The J and K are edge-triggered inputs which control the state changes of the flip-flops as described in the function table. Clock triggering occurs at a voltage level and is not directly related to the transition time of the positive-going pulse. The J and K inputs must be stable just one setup time prior to the low-to-high transition of the clock for predictable operation. The JK design allows operation as a D flip-flop by tying J and K inputs together. Although the clock input is level sensitive, the positive transition of the clock pulse between the 0.8V and 2.0V levels should be equal to or less than the clock to output delay time for reliable operation.
TYPE |
TYPICAL fmax |
TYPICAL SUPPLY CURRENT |
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(TOTAL) |
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74F109 |
125MHz |
12.3mA |
PIN CONFIGURATION
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RD0 |
1 |
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16 |
VCC |
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J0 |
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2 |
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RD1 |
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J1 |
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K0 |
3 |
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14 |
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CP0 |
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4 |
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13 |
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K1 |
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CP1 |
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SD0 |
5 |
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12 |
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Q0 |
6 |
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11 |
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SD1 |
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Q1 |
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Q0 |
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10 |
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GND |
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8 |
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9 |
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Q1 |
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SF00135 |
ORDERING INFORMATION
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ORDER CODE |
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DESCRIPTION |
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PKG DWG # |
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COMMERCIAL RANGE |
INDUSTRIAL RANGE |
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VCC = 5V ±10%, Tamb = 0°C to +70°C |
VCC = 5V ±10%, Tamb = ±40°C to +85°C |
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16-pin plastic DIP |
N74F109N |
I74F109N |
SOT38-4 |
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16-pin plastic SO |
N74F109D |
I74F109D |
SOT109-1 |
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INPUT AND OUTPUT LOADING AND FAN OUT TABLE
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PINS |
DESCRIPTION |
74F (U.L.) HIGH/LOW |
LOAD VALUE HIGH/LOW |
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J0, |
J1 |
J inputs |
1.0/1.0 |
20μA/0.6mA |
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K inputs |
1.0/1.0 |
20μA/0.6mA |
K0, |
K1 |
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CP0, |
CP1 |
Clock inputs (active rising edge) |
1.0/1.0 |
20μA/0.6mA |
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Set inputs (active Low) |
1.0/3.0 |
20μA/1.8mA |
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SD0, |
SD1 |
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Reset inputs (active Low) |
1.0/3.0 |
20μA/1.8mA |
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RD0, |
RD1 |
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Q0, Q1, |
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Data outputs |
50/33 |
1.0mA/20mA |
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Q0, Q1 |
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NOTE: One (1.0) FAST unit load is defined as: 20μA in the High state and 0.6mA in the Low state. |
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LOGIC SYMBOL |
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IEC/IEEE SYMBOL |
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2 |
14 |
3 |
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13 |
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2 |
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6 |
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1J |
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4 |
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C1 |
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3 |
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4 |
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CP0 |
J0 |
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J1 |
K0 |
K1 |
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1K |
7 |
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5 |
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SD0 |
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1 |
R |
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1 |
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RD0 |
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5 |
S |
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12 |
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CP1 |
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14 |
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10 |
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2J |
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11 |
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SD1 |
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12 |
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15 |
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RD1 |
Q0 |
Q0 |
Q1 Q1 |
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C2 |
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13 |
9 |
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2K |
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15 |
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R |
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11 |
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VCC = Pin 16 |
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6 |
7 |
10 |
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9 |
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S |
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GND = Pin 8 |
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SF00136 |
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SF00137 |
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October 23, 1990 |
2 |
853±0337 00783 |
Philips Semiconductors |
Product specification |
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Postive J- |
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positive edge-triggered flip-flops |
74F109 |
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K |
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LOGIC DIAGRAM
Q |
7, 9 |
6, 10 |
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Q |
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3, 13 |
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K |
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J |
2, 14 |
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4, 12 |
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CP |
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SD |
5, 11 |
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RD |
1, 15 |
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VCC = Pin 16 |
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GND = Pin 8 |
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SF00138 |
FUNCTION TABLE
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INPUTS |
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OUTPUTS |
OPERATING MODE |
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SD |
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RD |
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CP |
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J |
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K |
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Q |
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Q |
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L |
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H |
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X |
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X |
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X |
H |
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L |
Asynchronous set |
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H |
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L |
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X |
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X |
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X |
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L |
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H |
Asynchronous reset |
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L |
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L |
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X |
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X |
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X |
H |
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H |
Undetermined* |
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H |
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H |
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↑ |
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X |
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X |
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q |
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Hold |
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q |
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H |
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H |
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↑ |
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h |
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l |
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q |
Toggle |
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q |
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H |
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H |
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↑ |
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h |
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h |
H |
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L |
Load º1º (set) |
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H |
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H |
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↑ |
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l |
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l |
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L |
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H |
Load º0º (reset) |
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H |
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↑ |
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l |
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h |
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q |
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Hold 'no changeº |
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q |
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NOTES: |
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H |
= |
High-voltage level |
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h |
= |
High-voltage level one setup time prior to low-to-high |
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clock transition |
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L |
= |
Low-voltage level |
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l |
= |
Low-voltage level one setup time prior to low-to-high |
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clock transition |
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q |
= |
Lower case indicate the state of the referenced output |
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prior to the low-to-high clock transition |
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X |
= |
Don't care |
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↑= Low-to-high clock transition
↑= Not low-to-high clock transition
* = Both outputs will be high if both SD and RD go low simultaneously
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free air temperature range.)
SYMBOL |
PARAMETER |
RATING |
UNIT |
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VCC |
Supply voltage |
±0.5 to +7.0 |
V |
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VIN |
Input voltage |
±0.5 to +7.0 |
V |
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IIN |
Input current |
±30 to +5 |
mA |
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VOUT |
Voltage applied to output in High output state |
±0.5 to VCC |
V |
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IOUT |
Current applied to output in Low output state |
40 |
mA |
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Tamb |
Operating free-air temperature range |
Commercial range |
0 to +70 |
°C |
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Industrial range |
±40 to +85 |
°C |
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Tstg |
Storage temperature range |
±65 to +150 |
°C |
RECOMMENDED OPERATING CONDITIONS
SYMBOL |
PARAMETER |
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LIMITS |
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UNIT |
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MIN |
NOM |
MAX |
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VCC |
Supply voltage |
4.5 |
5.0 |
5.5 |
V |
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VIN |
High-level input voltage |
2.0 |
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V |
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VIL |
Low-level input voltage |
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0.8 |
V |
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IIK |
Input clamp current |
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±18 |
mA |
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IOH |
High-level output current |
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±1 |
mA |
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IOL |
Low-level output current |
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20 |
mA |
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Tamb |
Operating free-air temperature range |
Commercial range |
0 |
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+70 |
°C |
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Industrial range |
±40 |
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+85 |
°C |
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October 23, 1990 |
3 |