INTEGRATED CIRCUITS
74ABT574A
Octal D-type flip-flop (3-State)
Product specification |
1995 May 22 |
IC23 Data Handbook
m n r
Philips Semiconductors |
Product specification |
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Octal D-type flip-flop (3-State) |
74ABT574A |
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FEATURES
•74ABT574A is flow-through pinout version of 74ABT374
•Inputs and outputs on opposite side of package allow easy interface to microprocessors
•3-State outputs for bus interfacing
•Power-up 3-State
•Power-up reset
•Common output enable
•Latch-up protection exceeds 500mA per Jedec Std 17
•ESD protection exceeds 2000 V per MIL STD 883 Method 3015 and 200 V per Machine Model
•Live insertion/extraction permitted.
DESCRIPTION
The 74ABT574A high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive.
The 74ABT574A is an 8-bit, edge triggered register coupled to eight
3-State output buffers. The two sections of the device are controlled
independently by the clock (CP) and Output Enable (OE) control gates. The state of each D input (one set-up time before the Low-to-High clock transition) is transferred to the corresponding flip-flop's Q output.
When OE is Low, the stored data appears at the outputs. When OE is High, the outputs are in the High-impedance ªoffº state, which means they will neither drive nor load the bus.
The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS memories, or MOS microprocessors. The active-Low Output Enable (OE) controls all eight 3-State buffers independent of the clock operation.
QUICK REFERENCE DATA
SYMBOL |
PARAMETER |
CONDITIONS |
TYPICAL |
UNIT |
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Tamb = 25°C; GND = 0V |
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tPLH |
Propagation delay |
CL = 50pF; VCC = 5V |
3.0 |
ns |
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tPHL |
CP to Qn |
3.4 |
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CIN |
Input capacitance |
VI = 0V or VCC |
3 |
pF |
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COUT |
Output capacitance |
Outputs disabled; VO = 0V or VCC |
6 |
pF |
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ICCZ |
Total supply current |
Outputs disabled; VCC =5.5V |
100 |
μA |
ORDERING INFORMATION
PACKAGES |
TEMPERATURE RANGE |
OUTSIDE NORTH AMERICA |
NORTH AMERICA |
DWG NUMBER |
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20-Pin Plastic DIP |
±40°C to +85°C |
74ABT574A N |
74ABT574A N |
SOT146-1 |
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20-Pin plastic SO |
±40°C to +85°C |
74ABT574A D |
74ABT574A D |
SOT163-1 |
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20-Pin Plastic SSOP Type II |
±40°C to +85°C |
74ABT574A DB |
74ABT574A DB |
SOT339-1 |
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20-Pin Plastic TSSOP Type I |
±40°C to +85°C |
74ABT574A PW |
7ABT574APW DH |
SOT360-1 |
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PIN CONFIGURATION
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OE |
1 |
20 |
VCC |
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D0 |
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Q0 |
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2 |
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19 |
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D1 |
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Q1 |
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3 |
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18 |
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D2 |
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Q2 |
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4 |
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17 |
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D3 |
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Q3 |
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5 |
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16 |
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D4 |
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Q4 |
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6 |
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15 |
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D5 |
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Q5 |
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7 |
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14 |
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D6 |
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Q6 |
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8 |
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13 |
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D7 |
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Q7 |
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9 |
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12 |
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PIN DESCRIPTION
PIN |
SYMBOL |
FUNCTION |
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NUMBER |
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1 |
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Output enable input (active-Low) |
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OE |
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2, 3, 4, 5, |
D0-D7 |
Data inputs |
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6, 7, 8, 9 |
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19, 18, 17, |
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16, 15, 14, |
Q0-Q7 |
Data outputs |
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13, 12 |
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11 |
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CP |
Clock pulse input (active rising edge) |
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10 |
GND |
Ground (0V) |
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20 |
VCC |
Positive supply voltage |
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GND |
10 |
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11 |
CP |
SA00103
1995 May 22 |
2 |
853-1509 15261 |
Philips Semiconductors |
Product specification |
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Octal D-type flip-flop (3-State) |
74ABT574A |
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LOGIC SYMBOL |
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FUNCTION TABLE |
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INPUTS |
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INTERNAL |
OUTPUTS |
OPERATING |
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CP |
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Dn |
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REGISTER |
Q0 ± Q7 |
MODE |
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OE |
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2 |
3 |
4 |
5 |
6 |
7 |
8 |
9 |
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L |
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↑ |
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l |
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L |
L |
Load and read |
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L |
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↑ |
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h |
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H |
H |
register |
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D0 |
D1 |
D2 |
D3 |
D4 |
D5 |
D6 |
D7 |
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L |
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↑ |
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X |
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NC |
NC |
Hold |
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11 |
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CP |
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H |
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↑ |
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X |
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NC |
Z |
Disable outputs |
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H |
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↑ |
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Dn |
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Dn |
Z |
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1 |
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OE |
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H |
= |
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High voltage level |
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h |
= |
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High voltage level one set-up time prior to the Low±to±High |
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Q0 |
Q1 |
Q2 |
Q3 |
Q4 |
Q5 |
Q6 |
Q7 |
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clock transition |
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L |
= |
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Low voltage level |
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l |
= |
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Low voltage level one set-up time prior to the Low±to±High |
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19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
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clock transition |
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NC= |
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No change |
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X |
= |
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Don't care |
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SA00104 |
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Z |
= |
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High impedance ªoffº state |
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↑ |
= |
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Low-to-High clock transition |
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↑ |
= |
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not a Low-to-High clock transition |
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LOGIC SYMBOL (IEEE/IEC)
1 |
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EN |
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11 |
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C1 |
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2 |
19 |
2D |
1 |
3 |
18 |
4 |
17 |
5 |
16 |
6 |
15 |
7 |
14 |
8 |
13 |
9 |
12 |
SA00105
LOGIC DIAGRAM
D0 |
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D1 |
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D2 |
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D3 |
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D4 |
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D5 |
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D6 |
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D7 |
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2 |
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3 |
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4 |
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5 |
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6 |
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7 |
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8 |
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9 |
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D |
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D |
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D |
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D |
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D |
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D |
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D |
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D |
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CP |
Q |
CP |
Q |
CP |
Q |
CP |
Q |
CP |
Q |
CP |
Q |
CP |
Q |
CP |
Q |
11 |
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CP |
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1 |
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OE |
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19 |
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18 |
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17 |
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16 |
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15 |
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14 |
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13 |
12 |
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Q0 |
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Q1 |
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Q2 |
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Q3 |
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Q4 |
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Q5 |
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Q6 |
Q7 |
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SA00106 |
1995 May 22 |
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3 |
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Philips Semiconductors |
Product specification |
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Octal D-type flip-flop (3-State) |
74ABT574A |
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ABSOLUTE MAXIMUM RATINGS1, 2
SYMBOL |
PARAMETER |
CONDITIONS |
RATING |
UNIT |
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VCC |
DC supply voltage |
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±0.5 to +7.0 |
V |
IIK |
DC input diode current |
VI < 0 |
±18 |
mA |
VI |
DC input voltage3 |
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±1.2 to +7.0 |
V |
IOK |
DC output diode current |
VO < 0 |
±50 |
mA |
V |
DC output voltage3 |
output in Off or High state |
±0.5 to +5.5 |
V |
OUT |
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IOUT |
DC output current |
output in Low state |
128 |
mA |
Tstg |
Storage temperature range |
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±65 to 150 |
°C |
NOTES:
1.Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under ªrecommended operating conditionsº is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2.The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3.The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL |
PARAMETER |
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LIMITS |
UNIT |
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Min |
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Max |
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VCC |
DC supply voltage |
4.5 |
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5.5 |
V |
VI |
Input voltage |
0 |
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VCC |
V |
VIH |
High-level input voltage |
2.0 |
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V |
VIL |
Low-level input voltage |
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0.8 |
V |
IOH |
High-level output current |
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±32 |
mA |
IOL |
Low-level output current |
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64 |
mA |
t/ v |
Input transition rise or fall rate |
0 |
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5 |
ns/V |
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Tamb |
Operating free-air temperature range |
±40 |
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+85 |
°C |
1995 May 22 |
4 |
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