Philips 74ABT544PW, 74ABT544N, 74ABT544DB, 74ABT544D Datasheet
Philips Semiconductors Advanced BiCMOS Products Product specification
74ABT544
Octal latched transceiver with dual enable,
inverting (3-State)
1
June 1, 1993 853–1610 09907
FEATURES
•Combines 74ABT245 and 74ABT373 type
functions in one device
•8-bit octal transceiver with D-type latch
•Back-to-back registers for storage
•Separate controls for data flow in each
direction
•Output capability: +64mA/–32mA
•Live insertion/extraction permitted
•Power-up 3-State
•Power-up reset
•Latch-up protection exceeds 500mA per
Jedec JC40.2 Std 17
•ESD protection exceeds 2000 V per MIL
STD 883 Method 3015 and 200 V per
Machine Model
DESCRIPTION
The 74ABT544 high-performance BiCMOS
device combines low static and dynamic
power dissipation with high speed and high
output drive.
The 74ABT544 Octal Registered Transceiver
contains two sets of D-type latches for
temporary storage of data flowing in either
direction. Separate Latch Enable (LEAB
,
LEBA
) and Output Enable (OEAB, OEBA)
inputs are provided for each register to
permit independent control of data transfer in
either direction. The outputs are guaranteed
to sink 64mA.
FUNCTIONAL DESCRIPTION
The ’ABT544 contains two sets of eight
D–type latches, with separate control pins for
each set. Using data flow from A to B as an
example, when the A-to-B Enable (EAB
)
input and the A-to-B Latch Enable (LEAB
)
input are Low the A-to-B path is transparent.
A subsequent Low-to-High transition of the
LEAB
signal puts the A data into the latches
where it is stored and the B outputs no longer
change with the A inputs. With EAB
and
OEAB
both Low, the 3-State B output buffers
are active and invert the data present at the
outputs of the A latches.
Control of data flow from B to A is similar, but
using the EBA
, LEBA, and OEBA inputs.
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE ORDER CODE DRAWING NUMBER
24-pin plastic DIP –40°C to +85°C 74ABT544N 0410D
24-pin plastic SOL –40°C to +85°C 74ABT544D 0173D
24-pin plastic SSOP Type II –40°C to +85°C 74ABT544DB 1641A
PIN CONFIGURATION
LOGIC SYMBOL LOGIC SYMBOL (IEEE/IEC)
24
23
22
21
20
19
18
17
16
10 15
9
8
7
6
5
4
3
2
1
V
CC
EBA
B0
B1
B2
B3
B4
B5
B6
B7
OEBA
A0
A1
A2
A3
A4
A5
A6
A7
LEBA
2122
B0 B1 B2
1920
B3
3 4 5 6
A0 A1 A2 A3
11
23
1718
B4 B5 B6
1516
B7
7 8 9 10
A4 A5 A6 A7
EAB
EBA
3
14
14
12 13
11
LEAB
OEAB
EAB
GND
14 LEAB
1 LEBA
13OEAB
2OEBA
11
13
1
23
2
(AB)
(BA)
22
∇ 3
4 21
5 20
6 19
7 18
8 17
10 15
9 16
1EN3
G1
1C5
2EN4
G2
2C6
5D
5D
∇ 4
Philips Semiconductors Advanced BiCMOS Products Product specification
74ABT544
Octal latched transceiver with dual enable,
inverting (3-State)
June 1, 1993
2
PIN DESCRIPTION
PIN NUMBER SYMBOL FUNCTION
14, 1 LEAB / LEBA A to B / B to A Latch Enable input (active-Low)
11, 23 EAB / EBA A to B / B to A Enable input (active-Low)
13, 2 OEAB / OEBA A to B / B to A Output Enable input (active-Low)
3, 4, 5, 6,
7, 8, 9, 10
A0 – A7 Port A, 3-State outputs
22, 21, 20, 19,
18, 17, 16, 15
B0 – B7 Port B, 3-State outputs
12 GND Ground (0V)
24 V
CC
Positive supply voltage
QUICK REFERENCE DATA
SYMBOL PARAMETER
CONDITIONS
T
amb
= 25°C; GND = 0V
TYPICAL UNIT
t
PLH
t
PHL
Propagation delay
A
n to Bn or Bn to An
CL = 50pF; VCC = 5V 3.9 ns
C
IN
Input capacitance VI = 0V or V
CC
4 pF
C
I/O
I/O capacitance
Outputs disabled;
V
O
= 0V or V
CC
7 pF
I
CCZ
Total supply current Outputs disabled; VCC = 5.5V 110 µA
Philips Semiconductors Advanced BiCMOS Products Product specification
74ABT544
Octal latched transceiver with dual enable,
inverting (3-State)
June 1, 1993
3
LOGIC DIAGRAM
D
LE
Q
D
LE
Q
DETAIL A
22
B0
21
B1
4
A1
20
B2
5
A2
19
B3
6
A3
18
B4
7
A4
17
B5
8
A5
16
B6
9
A6
15
B7
10
A7
DETAIL A X 7
13
OEAB
11
EAB
14
LEAB
2
OEBA
23
EBA
1
LEBA
3
A0
FUNCTION TABLE
INPUTS OUTPUTS STATUS
OEXX EXX LEXX An or Bn An or Bn
H X X X Z Disabled
X H X X Z Disabled
L
L
↑
↑
L
L
h
l
Z
Z
Disabled + Latch
L
L
L
L
↑
↑
h
l
L
H
Latch + Display
L
L
L
L
L
L
H
L
L
H
Transparent
L L H X NC Hold
H = High voltage level
h = High voltage level one set-up time prior to the Low-to-High clock transition
L = Low voltage level
l = Low voltage level one set-up time prior to the Low-to-High clock transition
X = Don’t care
↑ = Low-to-High clock transition
NC= No change
Z = High impedance or “off” state
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