INTEGRATED CIRCUITS
74ABT543A
Octal latched transceiver with dual enable (3-State)
Product specification |
1998 Sep 24 |
Supersedes data of 1995 Apr 19
IC23 Data Handbook
m n r
Philips Semiconductors |
Product specification |
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Octal latched transceiver with dual enable
74ABT543A
(3-State)
FEATURES
•Combines 74ABT245 and 74ABT373 type functions in one device
•8-bit octal transceiver with D-type latch
•Back-to-back registers for storage
•Separate controls for data flow in each direction
•Output capability: +64mA/±32mA
•Live insertion/extraction permitted
•Power-up 3-State
•Power-up reset
•Latch-up protection exceeds 500mA per Jedec Std 17
•ESD protection exceeds 2000 V per MIL STD 883 Method 3015 and 200 V per Machine Model
The 74ABT543A Octal Registered Transceiver contains two sets of D-type latches for temporary storage of data flowing in either direction. Separate Latch Enable (LEAB, LEBA) and Output Enable (OEAB, OEBA) inputs are provided for each register to permit independent control of data transfer in either direction. The outputs are guaranteed to sink 64mA.
FUNCTIONAL DESCRIPTION
The 74ABT543A contains two sets of eight D-type latches, with separate control pins for each set. Using data flow from A to B as an example, when the A-to-B Enable (EAB) input and the A-to-B Latch Enable (LEAB) input are Low the A-to-B path is transparent. A subsequent Low-to-High transition of the LEAB signal puts the A data into the latches where it is stored and the B outputs no longer
change with the A inputs. With EAB and OEAB both Low, the 3-State B output buffers are active and display the data present at the outputs of the A latches.
DESCRIPTION
The 74ABT543A high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive.
Control of data flow from B to A is similar, but using the EBA, LEBA, and OEBA inputs.
QUICK REFERENCE DATA
SYMBOL |
PARAMETER |
CONDITIONS |
TYPICAL |
UNIT |
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Tamb = 25°C; GND = 0V |
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tPLH |
Propagation delay |
CL = 50pF; VCC = 5V |
2.9 |
ns |
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tPHL |
An to Bn or Bn to An |
3.6 |
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CIN |
Input capacitance |
VI = 0V or VCC |
4 |
pF |
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CI/O |
I/O capacitance |
Outputs disabled; |
7 |
pF |
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VO = 0V or VCC |
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ICCZ |
Total supply current |
Outputs disabled; VCC =5.5V |
110 |
μA |
ORDERING INFORMATION
PACKAGES |
TEMPERATURE RANGE |
OUTSIDE NORTH AMERICA |
NORTH AMERICA |
DWG NUMBER |
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24-Pin Plastic DIP |
±40°C to +85°C |
74ABT543A N |
74ABT543A N |
SOT222-1 |
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24-Pin plastic SO |
±40°C to +85°C |
74ABT543A D |
74ABT543A D |
SOT137-1 |
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24-Pin Plastic SSOP Type II |
±40°C to +85°C |
74ABT543A DB |
74ABT543A DB |
SOT340-1 |
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24-Pin Plastic TSSOP Type I |
±40°C to +85°C |
74ABT543A PW |
7ABT543APW DH |
SOT355-1 |
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PIN CONFIGURATION |
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PIN DESCRIPTION |
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PIN NUMBER |
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SYMBOL |
FUNCTION |
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LEBA |
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1 |
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24 |
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VCC |
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A to B / B to A Latch Enable |
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14, 1 |
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LEAB / LEBA |
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OEBA |
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2 |
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23 |
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EBA |
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input (active-Low) |
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A0 |
3 |
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22 |
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B0 |
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A to B / B to A Enable input |
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11, 23 |
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EAB / EBA |
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(active-Low) |
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A1 |
4 |
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21 |
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B1 |
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A to B / B to A Output Enable |
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A2 |
5 |
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20 |
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B2 |
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13, 2 |
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OEAB |
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OEBA |
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input (active-Low) |
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A3 |
6 |
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19 |
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B3 |
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3, 4, 5, 6, |
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A0 ± A7 |
Port A, 3-State outputs |
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A4 |
7 |
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18 |
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B4 |
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7, 8, 9, 10 |
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A5 |
8 |
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17 |
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B5 |
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22, 21, 20, 19, |
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B0 ± B7 |
Port B, 3-State outputs |
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18, 17, 16, 15 |
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A6 |
9 |
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16 |
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B6 |
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12 |
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GND |
Ground (0V) |
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A7 |
10 |
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15 |
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B7 |
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24 |
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VCC |
Positive supply voltage |
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EAB |
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11 |
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14 |
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LEAB |
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GND |
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12 |
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13 |
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OEAB |
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SA00168 |
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1998 Sep 24 |
2 |
853-1794 20080 |
Philips Semiconductors |
Product specification |
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Octal latched transceiver with dual enable
74ABT543A
(3-State)
LOGIC SYMBOL |
LOGIC SYMBOL (IEEE/IEC) |
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2 |
1EN3 (BA) |
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23 |
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G1 |
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1 |
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1C5 |
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13 |
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2EN4 (AB) |
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22 |
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3 |
4 |
5 |
6 |
7 |
8 |
9 |
10 |
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G2 |
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24 |
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2C6 |
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A0 |
A1 |
A2 |
A3 |
A4 |
A5 |
A6 |
A7 |
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3 |
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22 |
11 |
EAB |
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3 |
5D |
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4 |
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21 |
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6D |
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23 |
EBA |
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OEAB |
13 |
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2 |
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14 |
LEAB |
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OEBA |
2 |
5 |
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20 |
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1 |
LEBA |
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6 |
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19 |
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B0 |
B1 |
B2 |
B3 |
B4 |
B5 |
B6 |
B7 |
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7 |
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18 |
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8 |
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17 |
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22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
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9 |
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16 |
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10 |
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15 |
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SA00169 |
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SA00170 |
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LOGIC DIAGRAM |
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DETAIL A |
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D |
Q |
22 |
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B0 |
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LE |
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A0 |
3 |
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Q |
D |
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LE |
A1 |
4 |
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21 |
B1 |
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20 |
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A2 |
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B2 |
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6 |
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19 |
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A3 |
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B3 |
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7 |
DETAIL A X 7 |
18 |
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A4 |
B4 |
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8 |
17 |
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A5 |
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B5 |
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9 |
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16 |
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A6 |
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B6 |
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10 |
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15 |
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A7 |
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B7 |
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2
OEBA
13
OEAB
23
EBA
11
1 |
EAB |
LEBA
14
LEAB
SA00171
1998 Sep 24 |
3 |
Philips Semiconductors |
Product specification |
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Octal latched transceiver with dual enable
74ABT543A
(3-State)
FUNCTION TABLE
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INPUTS |
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OUTPUTS |
STATUS |
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An or Bn |
Bn or An |
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OEXX |
EXX |
LEXX |
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H |
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X |
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X |
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X |
Z |
Disabled |
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X |
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H |
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X |
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X |
Z |
Disabled |
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L |
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↑ |
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L |
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h |
Z |
Disabled + Latch |
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L |
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↑ |
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L |
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l |
Z |
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L |
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L |
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↑ |
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h |
H |
Latch + Display |
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L |
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L |
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↑ |
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l |
L |
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L |
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L |
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L |
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H |
H |
Transparent |
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L |
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L |
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L |
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L |
L |
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L |
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L |
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H |
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X |
NC |
Hold |
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H |
= |
High voltage level |
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or |
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(XX = AB or BA) |
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h |
= |
High voltage level one set-up time prior to the Low-to-High transition of |
LEXX |
EXX |
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L |
= |
Low voltage level |
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or |
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(XX = AB or BA) |
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l |
= |
Low voltage level one set-up time prior to the Low-to-High transition of |
LEXX |
EXX |
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X |
= |
Don't care |
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↑ |
= |
Low-to-High transition of |
LEXX |
or |
EXX |
(XX = AB or BA) |
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NC= |
No change |
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Z |
= |
High impedance or ªoffº state |
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ABSOLUTE MAXIMUM RATINGS1, 2
SYMBOL |
PARAMETER |
CONDITIONS |
RATING |
UNIT |
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VCC |
DC supply voltage |
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±0.5 to +7.0 |
V |
IIK |
DC input diode current |
VI < 0 |
±18 |
mA |
VI |
DC input voltage3 |
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±1.2 to +7.0 |
V |
IOK |
DC output diode current |
VO < 0 |
±50 |
mA |
V |
DC output voltage3 |
output in Off or High state |
±0.5 to +5.5 |
V |
OUT |
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IOUT |
DC output current |
output in Low state |
128 |
mA |
Tstg |
Storage temperature range |
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±65 to 150 |
°C |
NOTES:
1.Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under ªrecommended operating conditionsº is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2.The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3.The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL |
PARAMETER |
|
LIMITS |
UNIT |
|
|
|
|
|
|
|
|
|
Min |
|
Max |
|
|
|
|
|
|
|
VCC |
DC supply voltage |
4.5 |
|
5.5 |
V |
VI |
Input voltage |
0 |
|
VCC |
V |
VIH |
High-level input voltage |
2.0 |
|
|
V |
VIL |
Low-level input voltage |
|
|
0.8 |
V |
IOH |
High-level output current |
|
|
±32 |
mA |
IOL |
Low-level output current |
|
|
64 |
mA |
Dt/Dv |
Input transition rise or fall rate |
0 |
|
10 |
ns/V |
|
|
|
|
|
|
Tamb |
Operating free-air temperature range |
±40 |
|
+85 |
°C |
1998 Sep 24 |
4 |
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