Philips 74ABT540PW, 74ABT540N, 74ABT540DB, 74ABT540D Datasheet
INTEGRATED CIRCUITS
74ABT540
Octal buffer, inverting (3-State)
Product specification
Supersedes data of 1996 Oct 08
IC23 Data Handbook
1998 Jan 16
Philips Semiconductors Product specification
74ABT540Octal buffer, inverting (3-State)
FEA TURES
•Octal bus interface
•3-State buffers
•Live insertion/extraction permitted
•Efficient pinout to facilitate PC board layout
DESCRIPTION
The 74ABT540 high-performance BiCMOS device combines low
static and dynamic power dissipation with high speed and high
output drive.
The 74ABT540 device is an octal inverting buffer that is ideal for
driving bus lines. The device features input and outputs on opposite
sides of the package to facilitate printed circuit board layout.
•Output capability: +64mA/–32mA
•Latch-up protection exceeds 500mA per Jedec JC40.2 Std 17
•ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
•Power-up 3-State
QUICK REFERENCE DA TA
SYMBOL PARAMETER
C
t
PLH
t
PHL
C
OUT
I
CCZ
IN
Propagation delay
An to Yn
CL = 50pF; VCC = 5V 3.1 ns
Input capacitance VI = 0V or V
Output capacitance Outputs disabled; VO = 0V or V
Total supply current Outputs disabled; VCC = 5.5V 50 µA
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER
20-Pin Plastic DIP –40°C to +85°C 74ABT540 N 74ABT540 N SOT146-1
20-Pin plastic SO –40°C to +85°C 74ABT540 D 74ABT540 D SOT163-1
20-Pin Plastic SSOP Type II –40°C to +85°C 74ABT540 DB 74ABT540 DB SOT339-1
20-Pin Plastic TSSOP Type I –40°C to +85°C 74ABT540 PW 74ABT540PW DH SOT360-1
CONDITIONS
T
= 25°C; GND = 0V
amb
CC
CC
TYPICAL UNIT
3 pF
7 pF
PIN CONFIGURATION
1
OE0
2
A0
3
A1
4
A2
5
A3
6
A4
7
A5
8
A6
9
A7
10 11
GND
1998 Jan 16 853–1609 18864
20
19
18
17
16
15
14
13
12
SA00197
V
OE1
Y
Y
Y
Y
Y
Y
Y
Y
CC
0
1
2
3
4
5
6
7
LOGIC SYMBOL
2
OE
OE
1
0
19
1
2
A0
3
A1
4
A2
5
A3
6
A4
7
A5
8
A6
9
A7
18
17
16
15
14
13
12
11
SA00198
Y
0
1
Y
Y
2
Y
3
Y
4
Y
5
Y
6
Y
7
Philips Semiconductors Product specification
74ABT540Octal buffer, inverting (3-State)
LOGIC SYMBOL (IEEE/IEC)
PIN DESCRIPTION
PIN NUMBER SYMBOL NAME AND FUNCTION
2, 3, 4, 5,
&
1
19
EN
6, 7, 8, 9
18, 17, 16, 15,
14, 13, 12, 11
A0 – A7 Data inputs
Y0 – Y7 Data outputs
1, 19 OE0, OE1 Output enables
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
SA00199
10 GND Ground (0V)
20 V
CC
FUNCTION TABLE
INPUTS OUTPUTS
OE0 OE1 An Yn
L
L
X
H
L
L
H
X
L
H
X
X
Positive supply voltage
H
L
Z
Z
H =High voltage level
L =Low voltage level
X = Don’t care
Z =High impedance ”off” state
ABSOLUTE MAXIMUM RATINGS
SYMBOL
V
CC
I
IK
V
I
I
OK
V
OUT
I
OUT
T
stg
DC supply voltage –0.5 to +7.0 V
DC input diode current VI < 0 –18 mA
DC input voltage
DC output diode current VO < 0 –50 mA
DC output voltage
DC output current output in Low state 128 mA
Storage temperature range –65 to 150 °C
PARAMETER CONDITIONS RATING UNIT
3
3
1, 2
–1.2 to +7.0 V
output in Off or High state –0.5 to +5.5 V
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability .
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
1998 Jan 16
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