Philips 74ABT534PW, 74ABT534N, 74ABT534DB, 74ABT534D, 74ABT534AN Datasheet

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74ABT534A

Octal D-type flip-flop, inverting
(3-State)

Product specification 1997 Feb 03

INTEGRATED CIRCUITS

IC23 Data Handbook

Philips Semiconductors Product specification

74ABT534AOctal D-type flip-flop, inverting (3-State)

2

1997 Feb 03 853-1910 17722

FEA TURES

•8-bit positive edge triggered register

•3-State output buffers

•Output capability: +64mA/–32mA

•Latch-up protection exceeds 500mA per Jedec JC40.2 Std 17

•ESD protection exceeds 2000 V per MIL STD 883 Method 3015

and 200 V per Machine Model

•Power-up 3-State

DESCRIPTION

The 74ABT534A high-performance BiCMOS device combines low
static and dynamic power dissipation with high speed and high
output drive.

The 74ABT534A is an 8-bit, edge triggered register coupled to eight
3-State output buffers. The two sections of the device are controlled
independently by the clock (CP) and Output Enable (OE

) control

gates.
The register is fully edge triggered. The state of each D input, one

set-up time before the Low-to-High clock transition, is transferred to
the corresponding flip-flop’s output.

The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors. The
active-Low Output Enable (OE

) controls all eight 3-State buffers

independent of the clock operation.
When OE

is Low, the stored data appears at the outputs. When OE
is High, the outputs are in the High-impedance “OFF” state, which
means they will neither drive nor load the bus.

QUICK REFERENCE DA TA

SYMBOL PARAMETER

CONDITIONS

T

amb

= 25°C; GND = 0V

TYPICAL UNIT

t

PLH

t

PHL

Propagation delay
CP to Q

n

CL = 50pF; VCC = 5V

3.3

3.6

ns

C

IN

Input capacitance VI = 0V or V

CC

3.5 pF

C

OUT

Output capacitance Outputs disabled; VO = 0V or V

CC

6.5 pF

I

CCZ

Total supply current Outputs disabled; VCC =5.5V 100 µA

ORDERING INFORMATION

PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER

20-Pin Plastic DIP –40°C to +85°C 74ABT534A N 74ABT534A N SOT146-1
20-Pin plastic SO –40°C to +85°C 74ABT534A D 74ABT534A D SOT163-1
20-Pin Plastic SSOP Type II –40°C to +85°C 74ABT534A DB 74ABT534A DB SOT339-1
20-Pin Plastic TSSOP Type I –40°C to +85°C 74ABT534A PW 74ABT534APW DH SOT360-1

PIN CONFIGURATION

20
19
18
17
16
15
14
13
12

10 11

9

8

7

6

5

4

3

2

1

V

CC

Q7
D7
D6
Q

6
Q5
D5
D4
Q

4
CP

Q

0
D0
D1

Q

1

Q2

D2
D3

Q

3

GND

OE

SA00161

PIN DESCRIPTION

PIN NUMBER SYMBOL FUNCTION

1 OE Output enable input (active-Low)

3, 4, 7, 8,

13, 14, 17, 18

D0-D7 Data inputs

2, 5, 6, 9,

12, 15, 16, 19

Q0-Q7 Inverting 3-State outputs

11 CP

Clock pulse input

(active rising edge)
10 GND Ground (0V)
20 V

CC

Positive supply voltage

Philips Semiconductors Product specification

74ABT534AOctal D-type flip-flop, inverting (3-State)

1997 Feb 03

3

LOGIC SYMBOL

52

Q0 Q1 Q296Q3

3478

D0 D1 D2 D3

11

1

1512

Q4 Q5 Q6

1916

Q7

13 14 17 18

D4 D5 D6 D7

CP

OE

SA00162

LOGIC SYMBOL (IEEE/IEC)

1

3

2

4

5

7

6

8

9

EN

11

C1

13

12

14

15

17

16

18

19

1D

SA00163

FUNCTION T ABLE

INPUTS INTERNAL OUTPUTS

OPERATING

MODE

OE CP Dn REGISTER Q0 – Q7

LL↑

↑lh

L
H

H
L

Latch and read

register
L ↑ X NC NC Hold
HH↑↑X

Dn

NC
Dn

Z
Z

Disable

outputs

H = High voltage level
h = High voltage level one set-up time prior to the Low-to-High

clock transition
L = Low voltage level
l = Low voltage level one set-up time prior to the Low-to-High

clock transition
NC= No change
X = Don’t care
Z = High impedance “off” state

↑ = Low-to-High clock transition
↑

= not a Low-to-High clock transition

LOGIC DIAGRAM

2

CP Q

D

3

D0

Q0

CP Q

D

4

D1

CP Q

D

7

D2

CP Q

D

8

D3

CP Q

D

13

D4

CP Q

D

14

D5

CP Q

D

17

D6

CP Q

D

18

D7

Q1

5

Q2

6

Q3

9

Q4

12

Q5

15

Q6

16

Q7

19

11

CP

1

OE

SA00164

Philips Semiconductors Product specification

74ABT534AOctal D-type flip-flop, inverting (3-State)

1997 Feb 03

4

ABSOLUTE MAXIMUM RATINGS

1, 2

SYMBOL

PARAMETER CONDITIONS RATING UNIT

V

CC

DC supply voltage –0.5 to +7.0 V

I

IK

DC input diode current VI < 0 –18 mA

V

I

DC input voltage

3

–1.2 to +7.0 V

I

OK

DC output diode current VO < 0 –50 mA

V

OUT

DC output voltage

3

output in Off or High state –0.5 to +5.5 V

I

OUT

DC output current output in Low state 128 mA

T

stg

Storage temperature range –65 to 150 °C

NOTES:

1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability .

2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.

3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

RECOMMENDED OPERATING CONDITIONS

LIMITS

SYMBOL

PARAMETER

Min Max

UNIT

V

CC

DC supply voltage 4.5 5.5 V

V

I

Input voltage 0 V

CC

V

V

IH

High-level input voltage 2.0 V

V

IL

Low-level Input voltage 0.8 V

I

OH

High-level output current –32 mA

I

OL

Low-level output current 64 mA

∆t/∆v Input transition rise or fall rate 0 5 ns/V

T

amb

Operating free-air temperature range –40 +85 °C