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74ABT16825A
74ABTH16825A
18-bit buffer/line driver; non-inverting
(3-State)
Product specification
Supersedes data of 1995 Jul 14
IC23 Data Handbook
1998 Feb 25
Philips Semiconductors Product specification
18-bit buffer/line driver; non-inverting (3-State)
FEA TURES
•Multiple V
and GND pins minimize switching noise
CC
•Live insertion/extraction permitted
•3-State output buffers
•Power-up 3-State
•74ABTH16825A incorporates bus-hold data inputs which
eliminate the need for external pull-up resistors to hold unused
inputs
•Output capability: +64mA/–32mA
•Latch-up protection exceeds 500mA per Jedec Std 17
•ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model
•Bus-hold data inputs eliminate the need for external pull-up
resistors to hold unused inputs
QUICK REFERENCE DATA
SYMBOL PARAMETER
C
t
PLH
t
PHL
C
OUT
I
CCZ
I
CCL
IN
Propagation delay
nAx to nYx
Input capacitance VI = 0V or V
Output capacitance VO = 0V or VCC; 3-State 6 pF
pp
DESCRIPTION
The74ABT16825A high-performance BiCMOS device combines low
static and dynamic power dissipation with high speed and high
output drive.
The74ABT16825A 18-bit buffers provide high performance bus
interface buffering for wide data/address paths or buses carrying
parity. They have NOR Output Enables (nOE
control flexibility.
Two options are available, 74ABT16825A which does not have the
bus-hold feature and 74ABTH16825A which incorporates the
bus-hold feature.
Outputs disabled; VCC = 5.5V 500 µA
74ABT16825A
74ABTH16825A
1, nOE2) for maximum
CONDITIONS
T
= 25°C; GND = 0V
amb
CL = 50pF; VCC = 5V
CC
Outputs Low; VCC = 5.5V 9 mA
TYPICAL UNIT
1.8
1.4
4 pF
ns
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER
56-pin SSOP Type III –40°C to +85°C 74ABT16825A DL BT16825A DL SOT371-1
56-pin TSSOP Type II –40°C to +85°C 74ABT16825A DGG BT16825A DGG SOT364-1
56-pin SSOP Type III –40°C to +85°C 74ABTH16825A DL BH16825A DL SOT371-1
56-pin TSSOP Type II –40°C to +85°C 74ABTH16825A DGG BH16825A DGG SOT364-1
PIN DESCRIPTION
PIN NUMBER SYMBOL FUNCTION
55, 54, 52, 51, 49, 48, 47, 45, 44,
41, 40, 38, 37, 36, 34, 33, 31, 30
2, 3, 5, 6, 8, 9, 10, 12, 13
16, 17, 19, 20, 21, 23, 24, 26, 27
1, 56
28, 29
4, 11, 14, 15, 18, 25, 32, 39, 42, 43, 46, 53 GND Ground (0V)
7, 22, 35, 50 V
1A0 – 1A9
2A0 – 2A9
1Y0 – 1Y9
2Y0 – 2Y9
1OE0, 1OE1
2OE0, 2OE1
CC
Data inputs
Data outputs
Output enable inputs (active-Low)
Positive supply voltage
1998 Feb 25 853-1804 19018
2
Philips Semiconductors Product specification
18-bit buffer/line driver; non-inverting (3-State)
PIN CONFIGURATION
1
1OE0
2
1Y0
3
1Y1
4
GND
5
1Y2
6
1Y3
7
V
CC
8
1Y4
9
1Y5
10
1Y6
11
GND
1Y7
12
1Y8
13
14
GND
15
GND
16
2Y0
17
2Y1
18
GND
2Y2
19
20
2Y3
21
2Y4
22
V
CC
23
2Y5
24
2Y6
GND
25
2Y7
26
2Y8
27
0
28
2OE
56
1
1OE
55
1A0
54
1A1
53
GND
1A2
52
1A3
51
50
V
CC
1A4
49
1A5
48
1A6
47
GND
46
1A7
45
1A8
44
GND
43
GND
42
2A0
41
2A1
40
GND
39
38
2A2
2A3
37
2A4
36
35
V
CC
34
2A5
33
2A6
32
GND
31
2A7
2A8
30
29
2OE1
LOGIC SYMBOL (IEEE/IEC)
1OE
1OE
2OE
2OE
1A0
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
2A0
2A1
2A2
2A3
2A4
2A5
2A6
2A7
2A8
74ABT16825A
74ABTH16825A
1
0
56
1
28
0
29
1
55
54
52
51
49
48
47
45
44
41
40
38
37
36
34
33
31
30
&
EN1
&
EN2
1 ∇
2 ∇
2
3
5
6
8
9
10
12
13
16
17
19
20
21
23
24
26
27
SA00074
1Y0
1Y1
1Y2
1Y3
1Y4
1Y5
1Y6
1Y7
1Y8
2Y0
2Y1
2Y2
2Y3
2Y4
2Y5
2Y6
2Y7
2Y8
LOGIC DIAGRAM
0
nOE
nOE1
1998 Feb 25
nA0
nY0
SA00073
nA1
nY1
nA2
nY2
nA3
nY3
nA4
nY4
nA5
nY5
nA6
nY6
nA7
nY7
nA8
nY8
SA00075
3