Philips 40PFL8606 Schematic

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Page 1

Colour Television Chassis

19050_000_110505.eps

110809

Q551.2E

Contents Page Contents Page

1. Revision List 2

2. Technical Specifications, Diversity, and Connections2

3. Precautions, Notes, and Abbreviation List 7

4. Mechanical Instructions 11

5. Service Modes, Error Codes, and Fault Finding 22

6. Alignments 44

7. Circuit Descriptions 49

8. IC Data Sheets 63

9. Block Diagrams Wiring diagram Oscar 32" 77 Wiring diagram Oscar 37" 78 Wiring diagram Oscar 46" 79 Wiring diagram Oscar Platinum 58" 81 Wiring diagram Cannes 40 - 46" 82 Wiring diagram Sundance 50" 83 Block Diagram Video 84 Block Diagram Audio 85 Block Diagram Control & Clock Signals 86 Block Diagram I2C 87 Supply Lines Overview 88

10. Circuit Diagrams and PWB Layouts Drawing B01 310431365381 B02 310431365381 103 B03 310431365381 112 B04 310431365381 120 B05 310431365381 125 B06 310431365381 126 B07 310431365381 130 B08 310431365381 131 B09 310431365381 133 B10 310431365381 134 B11 310431365381 135 B01 310431365392 139

Copyright 2011 Koninklijke Philips Electronics N.V. All rights reserved. No part of this publication may be reproduced, stored in a retrieval system or transmitted, in any form or by any means, electronic, mechanical, photocopying, or otherwise without the prior permission of Philips.

B02 310431365392 150 B03 310431365392 159 B04 310431365392 167 B05 310431365392 172 B06 310431365392 173 B07 310431365392 177 B08 310431365392 178 B09 310431365392 180 B10 310431365392 181 B12 310431365392 182 FB01 820400091952 185 FB01 820400091992 208 FB01 820400092112 238 BB 310431364723 255 E 272217190427 IR/LED/Key Board 274 E 272217190459 Leading Edge 276 E 272217190447 Leading Edge 278 UD 310431365083 280 W 310431363282 WiFi Antenna 281 ALD 310431365212 282 ALD 310431365473 284 AL1 820400091574 300 AL3 820400091263 302

11. Styling Sheets Oscar 32" 320 Oscar 37" 321 Oscar 46" 323 Oscar 52" 324 Oscar 58" 325 Cannes 40 - 46" 326 Sundance 50" 327

Published by ER/EL 1169 BU TV Consumer Care, the Netherlands Subject to modification EN 3122 785 19052

2011-Sep-09

Page 2

EN 2 Q551.2E LA1.

Revision List

1. Revision List

Manual xxxx xxx xxxx.0

• First release.

Manual xxxx xxx xxxx.1

• Chapter 2: added CTNs to the table, see Table 2-1

• Chapter 5: modified SSB replacement procedure; see section 5.8.12

• Chapter 7: added section 7.8

Back-End Processing.

Manual xxxx xxx xxxx.2

• Chapter 2: removed 37PFL9606T/12 from the table, see

Table 2-1

• Chapter 4: added mechanical information Cannes, see section 4.5

Assy/Panel Removal Cannes Styling

(xxPFL8xxx/xx series).

• Chapter 7: power supply connector overview, see section

Power Supply.

7.2

2. Technical Specifications, Diversity, and Connections

Index of this chapter:

Technical Specifications

2.1

2.2 Directions for Use

2.3 Connections

2.4 Chassis Overview

Notes:

• Figures can deviate due to the different set executions.

• Specifications are indicative (subject to change).

Table 2-1 Described Model Numbers and Diversity

CTN Styling

32PFL9606H/12 Oscar

32PFL9606K/02 Oscar

32PFL9606M/08 Oscar

37PFL9606H/12 Oscar

37PFL9606K/02 Oscar

37PFL9606M/08 Oscar

40PFL8606H/12 Cannes

40PFL8606H/60 Cannes

40PFL8606K/02 Cannes

40PFL8606M/08 Cannes

40PFL8606T/12 Cannes

46PFL8606H/12 Cannes

46PFL8606H/60 Cannes

46PFL8606K/02 Cannes

46PFL8606M/08 Cannes

46PFL8606T/12 Cannes

46PFL8686H/12 Cannes

46PFL8686K/02 Cannes

11-1

11-2

11-7

SSB 2 4 7 9 10

Mechanics

3104 313 xxxxx

Connection Overview

65381 2.3 4-1 4.3 4.3.8 7.2 7.9 9-1 - 10-49

65392 2.3 4-2 4.3 4.3.8 7.2 7.9 9-2 - 10-49

65392 2.3 4-3 4.5 4.5.2 7.2 7.9 9-6 9-14 10-48

65392 2.3 4-4 4.5 4.5.2 7.2 7.9 9-6 9-14 10-48

Wire Dressing

Descriptions

Assembly Removal

LCD Removal

PSU

AmbiLight

Wiring Diagram

2.1 Technical Specifications

For on-line product support please use the CTN links in Table

2-1. Here is product information available, as well as getting

started, user manuals, frequently asked questions and software & drivers.

Schematics

Block diagram Bolt-on

ALxx (Ambilight) LiteOn

B01 (Tuner)

B02 (PNX85500)

B03 (DC/DC / Class D)

B04 (I/O)

B05 (DDR)

B06 (non-DVBS-LVDS)

B07 (DVBS-FE)

B08 (DVBS-Supp.)

B09 (non-DVBS-conn.)

B10 (DVBT2)

10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 - - -

10-52

10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 - - -

10-52

10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 - - -

10-52

10-1310-14 10-15 10-16 10-17 10-18 10-19 10-20 10-21 10-22 - 10-23 - 10-28

10-53

10-1310-14 10-15 10-16 10-17 10-18 10-19 10-20 10-21 10-22 - 10-23 - 10-28

10-53

10-1310-14 10-15 10-16 10-17 10-18 10-19 10-20 10-21 10-22 - 10-23 - 10-28

10-53

10-1310-14 10-15 10-16 10-17 10-18 10-19 10-20 10-21 10-22 - 10-23 - 10-25

10-50

10-1310-14 10-15 10-16 10-17 10-18 10-19 10-20 10-21 10-22 - 10-23 - 10-25

10-50

10-1310-14 10-15 10-16 10-17 10-18 10-19 10-20 10-21 10-22 - 10-23 - 10-25

10-50

10-1310-14 10-15 10-16 10-17 10-18 10-19 10-20 10-21 10-22 - 10-23 - 10-25

10-50

10-1310-14 10-15 10-16 10-17 10-18 10-19 10-20 10-21 10-22 - 10-23 - 10-25

10-50

10-1310-14 10-15 10-16 10-17 10-18 10-19 10-20 10-21 10-22 - 10-23 - 10-25

10-51

10-1310-14 10-15 10-16 10-17 10-18 10-19 10-20 10-21 10-22 - 10-23 - 10-25

10-51

10-1310-14 10-15 10-16 10-17 10-18 10-19 10-20 10-21 10-22 - 10-23 - 10-25

10-51

10-1310-14 10-15 10-16 10-17 10-18 10-19 10-20 10-21 10-22 - 10-23 - 10-25

10-51

10-1310-14 10-15 10-16 10-17 10-18 10-19 10-20 10-21 10-22 - 10-23 - 10-25

10-51

10-1310-14 10-15 10-16 10-17 10-18 10-19 10-20 10-21 10-22 - 10-23 - 10-25

10-51

10-1310-14 10-15 10-16 10-17 10-18 10-19 10-20 10-21 10-22 - 10-23 - 10-25

10-51

B11 (FPGA)

B12 (DVBS DC/DC)

ALD (DC/DC Board)

10-29 10-30

10-26

FBxx (Bolt-on)

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Technical Specifications, Diversity, and Connections

SSB 2 4 7 9 10

Mechanics

Descriptions

Schematics

EN 3Q551.2E LA 2.

CTN Styling

46PFL9706H/12 Oscar

46PFL9706K/02 Oscar

46PFL9706M/08 Oscar

46PFL9706T/12 Oscar

50PFL7956H/12 Sundance

50PFL7956K/02 Sundance

50PFL7956T/12 Sundance

52PFL9606H/12 Oscar

52PFL9606K/02 Oscar

52PFL9606M/08 Oscar

52PFL9606T/12 Oscar

58PFL9956H/12 Oscar

58PFL9956T/12 Oscar

11-4

11-8

11-5

11-6

3104 313 xxxxx

Connection Overview

Wire Dressing

65392 2.3 4-5 4.3 4.3.8 7.2 7.9 9-3 9-13 10-46-10-1310-14 10-15 10-16 10-17 10-18 10-19 10-20 10-21 10-22 - 10-23 10-42 10-25

65392 2.3 4-6 4.4 4.4.8 7.2 7.9 9-7 9-15 10-48

65392 2.3 4-7 4.3 4.3.8 7.2 7.9 9-4 9-13 10-47-10-1310-14 10-15 10-16 10-17 10-18 10-19 10-20 10-21 10-22 - 10-23 10-42 10-25

65392 2.3 4-8 4.3 4.3.8 7.2 7.9 9-5 9-13 10-49

Assembly Removal

2.2 Directions for Use

You can download this information from the following websites:

http://www.philips.com/support http://www.p4c.philips.com

Wiring Diagram

AmbiLight

Block diagram Bolt-on

ALxx (Ambilight) LiteOn

B01 (Tuner)

B02 (PNX85500)

B03 (DC/DC / Class D)

B04 (I/O)

B05 (DDR)

B06 (non-DVBS-LVDS)

B07 (DVBS-FE)

B08 (DVBS-Supp.)

B09 (non-DVBS-conn.)

B10 (DVBT2)

B11 (FPGA)

10-1310-14 10-15 10-16 10-17 10-18 10-19 10-20 10-21 10-22 - 10-23 - 10-32

10-50

10-1310-14 10-15 10-16 10-17 10-18 10-19 10-20 10-21 10-22 - 10-23 - 10-32

10-50

10-1310-14 10-15 10-16 10-17 10-18 10-19 10-20 10-21 10-22 - 10-23 - 10-32

10-50

10-1310-14 10-15 10-16 10-17 10-18 10-19 10-20 10-21 10-22 - 10-23 10-44 10-25

10-53

10-1310-14 10-15 10-16 10-17 10-18 10-19 10-20 10-21 10-22 - 10-23 10-44 10-25

10-53

B12 (DVBS DC/DC)

ALD (DC/DC Board)

10-26

10-33

10-26

FBxx (Bolt-on)

LCD Removal

PSU

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5 6 7

11 11 12 13 149 10

Bottom

Back

Connections

Side

ECAFRETNI NOMMOCBSUBSUediS IMDH SD CARD

NETWORK HDMI 1AUDIO OUT

ARC

HDMI 2 HDMI 3

OPTICAL

ANTENNA VGA

AUDIO IN

Y Pb Pr - L R

SCART (RGB / CVBS)

DVI / VGA

Connections

Side Back

HDMI SideUSB USB

COMMON INTERFACE

SD CARD SATELLITE

HDMI 1

ARC

HDMI 2 HDMI 3 SCART

NETWORK

AUDIO OUT

ANTENNA

VGA

AUDIO IN

DVI / VGAOPTICAL

Y Pb Pr - L R

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2 2 1 10 11 11 5 8 12

9 14 7 1315 6

2.3 Connections

Technical Specifications, Diversity, and Connections

Figure 2-1 Connection overview

Figure 2-2 Connection overview

2011-Sep-09

Note: The following connector colour abbreviations are used (acc. to DIN/IEC 757): Bk= Black, Bu= Blue, Gn= Green, Gy= Grey, Rd= Red, Wh= White, Ye= Yellow.

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Technical Specifications, Diversity, and Connections

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2.3.1 Back Connections

5 - Video RGB - In, CVBS - In/Out, Audio - In/Out

Figure 2-3 SCART connector

1 -Audio R 0.5 V 2 -Audio R 0.5 V 3 -Audio L 0.5 V 4 -Ground Audio Gnd H

/ 1 kohm k

RMS

/ 10 kohm j

RMS

/ 1 kohm k

RMS

5 -Ground Blue Gnd H 6 -Audio L 0.5 V 7 -Video Blue 0.7 V 8 -Function Select 0 - 2 V: INT

/ 10 kohm j

RMS

/ 75 ohm jk

4.5 - 7 V: EXT 16:9

9.5 - 12 V: EXT 4:3 j 9 - Ground Green Gnd H 10 - n.c. 11 - Video Green 0.7 V 12 - n.c.

/ 75 ohm j

13 - Ground Red Gnd H 14 - Ground P50 Gnd H 15 - Video Red 0.7 V 16 - Status/FBL 0 - 0.4 V: INT

/ 75 ohm j

1 - 3 V: EXT / 75 ohm j 17 - Ground Video Gnd H 18 - Ground FBL Gnd H 19 - Video CVBS/Y 1 V 20 - Video CVBS 1 V 21 - Shield Gnd H

/ 75 ohm k

/ 75 ohm j

10 - HDMI 1: Digital Video - In, Digital Audio with ARC - In/ Out

Figure 2-5 HDMI (type A) connector

1 - D2+ Data channel j 2 - Shield Gnd H 3 - D2- Data channel j 4 - D1+ Data channel j 5 - Shield Gnd H 6 - D1- Data channel j 7 - D0+ Data channel j 8 - Shield Gnd H 9 - D0- Data channel j 10 - CLK+ Data channel j 11 - Shield Gnd H 12 - CLK- Data channel j 13 - Easylink/CEC Control channel jk 14 - ARC Audio Return Channel k 15 - DDC_SCL DDC clock j 16 - DDC_SDA DDC data jk 17 - Ground Gnd H 18 - +5V j 19 - HPD Hot Plug Detect j 20 - Ground Gnd H

11 - HDMI 2 & 3: Digital Video, Digital Audio - In

6 - Cinch: Video YPbPr - In, Audio - In

Gn - Video Y 1 V Bu -Video Pb 0.7 V Rd - Video Pr 0.7 V Rd - Audio - R 0.5 V Wh -Audio - L 0.5 V

/ 75 ohm jq

/ 10 kohm jq

RMS

/ 10 kohm jq

RMS

7 - Cinch: Audio - In (VGA/DVI)

Rd - Audio R 0.5 V Wh -Audio L 0.5 V

/ 10 kohm jq

RMS

/ 10 kohm jq

RMS

8 - RJ45: Ethernet

Figure 2-4 Ethernet connector

1 - TD+ Transmit signal k 2 - TD- Transmit signal k 3 - RD+ Receive signal j 4 - CT Centre Tap: DC level fixation 5 - CT Centre Tap: DC level fixation 6 - RD- Receive signal j 7 - GND Gnd H 8 - GND Gnd H

9 - Cinch: S/PDIF - Out

Bk -Coaxial 0.4 - 0.6V

/ 75 ohm kq

Figure 2-6 HDMI (type A) connector

1 - D2+ Data channel j 2 - Shield Gnd H 3 - D2- Data channel j 4 - D1+ Data channel j 5 - Shield Gnd H 6 - D1- Data channel j 7 - D0+ Data channel j 8 - Shield Gnd H 9 - D0- Data channel j 10 - CLK+ Data channel j 11 - Shield Gnd H 12 - CLK- Data channel j 13 - Easylink/CEC Control channel jk 14 - n.c. 15 - DDC_SCL DDC clock j 16 - DDC_SDA DDC data jk 17 - Ground Gnd H 18 - +5V j 19 - HPD Hot Plug Detect j 20 - Ground Gnd H

12 - Head phone (Output)

Bk -Head phone 32 - 600 ohm / 10 mW ot

13 - Aerial - In

- -IEC-type (EU) Coax, 75 ohm D

14 - VGA: Video RGB - In

Figure 2-7 VGA Connector

1 - Video Red 0.7 V

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/ 75 ohm j

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GND

DAT3/CS

CMD/DI

GND1

VDD

CLOCK

GND2

DAT0/D0

DAT1/IRQ

DAT2/NC

Technical Specifications, Diversity, and Connections

2 - Video Green 0.7 VPP / 75 ohm j 3 - Video Blue 0.7 V

/ 75 ohm j

4-n.c. 5 - Ground Gnd H 6 - Ground Red Gnd H 7 - Ground Green Gnd H 8 - Ground Blue Gnd H 9-+5V

+5 V j

10 - Ground Sync Gnd H 11 - n.c. 12 - DDC_SDA DDC data j 13 - H-sync 0 - 5 V j 14 - V-sync 0 - 5 V j 15 - DDC_SCL DDC clock j

2.3.2 Side Connections

1 - HDMI : Digital Video, Digital Audio - In

See 11 - HDMI 2 & 3: Digital Video, Digital Audio - In

2 - USB2.0

Figure 2-8 USB (type A)

1-+5V k 2 - Data (-) jk 3 - Data (+) jk 4 - Ground Gnd H

3 - SD-Card: Secure Digital Card - In/Out (optional)

Figure 2-9 SD-Card connector

1 - DAT3/CS Signal jk 2 - CMD/DI Signal k 3 - GND1 Gnd H 4 - Vdd Supply k 5 - CLOCK Signal k 6 - GND2 Gnd H 7 - DAT0/D0 Signal jk 8 - DAT1/IRQ Signal jk 9 - DAT2/NC Signal jk 10 - CD Signal j 11 - GND Gnd H 12 - WP Signal j 13 - GND Gnd H 14 - GND Gnd H

2.4 Chassis Overview

Refer to chapter Block Diagrams for PWB/CBA locations.

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4 - Common Interface

68p- See diagram B01A Common Interface

15 - SAT - In (optional)

- -F-type Coax, 75 ohm D

Page 7

Precautions, Notes, and Abbreviation List

3. Precautions, Notes, and Abbreviation List

EN 7Q551.2E LA 3.

Index of this chapter:

Safety Instructions

3.1

3.2 Warnings

3.3 Notes

3.4 Abbreviation List

3.1 Safety Instructions

Safety regulations require the following during a repair:

• Connect the set to the Mains/AC Power via an isolation

transformer (> 800 VA).

• Replace safety components, indicated by the symbol h,

only by components identical to the original ones. Any other component substitution (other than original type) may increase risk of fire or electrical shock hazard.

Safety regulations require that after a repair, the set must be returned in its original condition. Pay in particular attention to the following points:

• Route the wire trees correctly and fix them with the

mounted cable clamps.

• Check the insulation of the Mains/AC Power lead for

external damage.

• Check the strain relief of the Mains/AC Power cord for

proper function.

• Check the electrical DC resistance between the Mains/AC

Power plug and the secondary side (only for sets that have a Mains/AC Power isolated power supply):

1. Unplug the Mains/AC Power cord and connect a wire between the two pins of the Mains/AC Power plug.

2. Set the Mains/AC Power switch to the “on” position (keep the Mains/AC Power cord unplugged!).

3. Measure the resistance value between the pins of the Mains/AC Power plug and the metal shielding of the tuner or the aerial connection on the set. The reading should be between 4.5 MΩ and 12 MΩ.

4. Switch “off” the set, and remove the wire between the two pins of the Mains/AC Power plug.

• Check the cabinet for defects, to prevent touching of any inner parts by the customer.

3.2 Warnings

• All ICs and many other semiconductors are susceptible to electrostatic discharges (ESD w). Careless handling during repair can reduce life drastically. Make sure that, during repair, you are connected with the same potential as the mass of the set by a wristband with resistance. Keep components and tools also at this same potential.

• Be careful during measurements in the high voltage section.

• Never replace modules or other components while the unit is switched “on”.

• When you align the set, use plastic rather than metal tools. This will prevent any short circuits and the danger of a circuit becoming unstable.

3.3 Notes

3.3.1 General

• Measure the voltages and waveforms with regard to the chassis (= tuner) ground (H), or hot ground (I), depending on the tested area of circuitry. The voltages and waveforms shown in the diagrams are indicative. Measure them in the Service Default Mode with a colour bar signal and stereo sound (L: 3 kHz, R: 1 kHz unless stated otherwise) and picture carrier at 475.25 MHz for PAL, or 61.25 MHz for NTSC (channel 3).

• Where necessary, measure the waveforms and voltages with (D) and without (E) aerial signal. Measure the voltages in the power supply section both in normal operation (G) and in stand-by (F). These values are indicated by means of the appropriate symbols.

3.3.2 Schematic Notes

• All resistor values are in ohms, and the value multiplier is often used to indicate the decimal point location (e.g. 2K2 indicates 2.2 k Ω).

• Resistor values with no multiplier may be indicated with either an “E” or an “R” (e.g. 220E or 220R indicates 220 Ω).

• All capacitor values are given in micro-farads (μ=× 10 nano-farads (n =× 10

• Capacitor values may also use the value multiplier as the decimal point indication (e.g. 2p2 indicates 2.2 pF).

• An “asterisk” (*) indicates component usage varies. Refer to the diversity tables for the correct values.

• The correct component values are listed on the Philips Spare Parts Web Portal.

3.3.3 Spare Parts

For the latest spare part overview, consult your Philips Spare Part web portal.

3.3.4 BGA (Ball Grid Array) ICs

Introduction

For more information on how to handle BGA devices, visit this URL: http://www.atyourservice-magazine.com “Magazine”, then go to “Repair downloads”. Here you will find Information on how to deal with BGA-ICs.

BGA Temperature Profiles

For BGA-ICs, you must use the correct temperature-profile. Where applicable and available, this profile is added to the IC Data Sheet information section in this manual.

3.3.5 Lead-free Soldering

Due to lead-free technology some rules have to be respected by the workshop during a repair:

• Use only lead-free soldering tin. If lead-free solder paste is required, please contact the manufacturer of your soldering equipment. In general, use of solder paste within workshops should be avoided because paste is not easy to store and to handle.

• Use only adequate solder tools applicable for lead-free soldering tin. The solder tool must be able: – To reach a solder-tip temperature of at least 400°C. – To stabilize the adjusted temperature at the solder-tip. – To exchange solder-tips for different applications.

• Adjust your solder tool so that a temperature of around 360°C - 380°C is reached and stabilized at the solder joint. Heating time of the solder-joint should not exceed ~ 4 sec. Avoid temperatures above 400°C, otherwise wear-out of tips will increase drastically and flux-fluid will be destroyed. To avoid wear-out of tips, switch “off” unused equipment or reduce heat.

• Mix of lead-free soldering tin/parts with leaded soldering tin/parts is possible but PHILIPS recommends strongly to avoid mixed regimes. If this cannot be avoided, carefully clear the solder-joint from old tin and re-solder with new tin.

3.3.6 Alternative BOM identification

It should be noted that on the European Service website, “Alternative BOM” is referred to as “Design variant”.

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-9

), or pico-farads (p =× 10

. Select

-6

-12

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Precautions, Notes, and Abbreviation List

The third digit in the serial number (example: AG2B0335000001) indicates the number of the alternative B.O.M. (Bill Of Materials) that has been used for producing the specific TV set. In general, it is possible that the same TV model on the market is produced with e.g. two different types of displays, coming from two different suppliers. This will then result in sets which have the same CTN (Commercial Type Number; e.g. 28PW9515/12) but which have a different B.O.M. number. By looking at the third digit of the serial number, one can identify which B.O.M. is used for the TV set he is working with. If the third digit of the serial number contains the number “1” (example: AG1B033500001), then the TV set has been manufactured according to B.O.M. number 1. If the third digit is a “2” (example: AG2B0335000001), then the set has been produced according to B.O.M. no. 2. This is important for ordering the correct spare parts! For the third digit, the numbers 1...9 and the characters A...Z can be used, so in total: 9 plus 26= 35 different B.O.M.s can be indicated by the third digit of the serial number.

Identification: The bottom line of a type plate gives a 14-digit serial number. Digits 1 and 2 refer to the production centre (e.g. SN is Lysomice, RJ is Kobierzyce), digit 3 refers to the B.O.M. code, digit 4 refers to the Service version change code, digits 5 and 6 refer to the production year, and digits 7 and 8 refer to production week (in example below it is 2010 week 10 / 2010 week 17). The 6 last digits contain the serial number.

Figure 3-1 Serial number (example)

3.3.7 Board Level Repair (BLR) or Component Level Repair (CLR)

If a board is defective, consult your repair procedure to decide if the board has to be exchanged or if it should be repaired on component level. If your repair procedure says the board should be exchanged completely, do not solder on the defective board. Otherwise, it cannot be returned to the O.E.M. supplier for back charging!

3.3.8 Practical Service Precautions

• It makes sense to avoid exposure to electrical shock.

While some sources are expected to have a possible dangerous impact, others of quite high potential are of limited current and are sometimes held in less regard.

• Always respect voltages. While some may not be

dangerous in themselves, they can cause unexpected reactions that are best avoided. Before reaching into a powered TV set, it is best to test the high voltage insulation. It is easy to do, and is a good service precaution.

3.4 Abbreviation List

0/6/12 SCART switch control signal on A/V

board. 0 = loop through (AUX to TV), 6 = play 16 : 9 format, 12 = play 4 : 3 format

AARA Automatic Aspect Ratio Adaptation:

algorithm that adapts aspect ratio to remove horizontal black bars; keeps the original aspect ratio

ACI Automatic Channel Installation:

algorithm that installs TV channels directly from a cable network by

means of a predefined TXT page ADC Analogue to Digital Converter AFC Automatic Frequency Control: control

signal used to tune to the correct

frequency AGC Automatic Gain Control: algorithm that

controls the video input of the feature

box AM Amplitude Modulation AP Asia Pacific AR Aspect Ratio: 4 by 3 or 16 by 9 ASF Auto Screen Fit: algorithm that adapts

aspect ratio to remove horizontal black

bars without discarding video

information ATSC Advanced Television Systems

Committee, the digital TV standard in

the USA ATV See Auto TV Auto TV A hardware and software control

system that measures picture content,

and adapts image parameters in a

dynamic way AV External Audio Video AVC Audio Video Controller AVIP Audio Video Input Processor B/G Monochrome TV system. Sound

carrier distance is 5.5 MHz BDS Business Display Solutions (iTV) BLR Board-Level Repair BTSC Broadcast Television Standard

Committee. Multiplex FM stereo sound

system, originating from the USA and

used e.g. in LATAM and AP-NTSC

countries B-TXT Blue TeleteXT C Centre channel (audio) CEC Consumer Electronics Control bus:

remote control bus on HDMI

connections CL Constant Level: audio output to

connect with an external amplifier CLR Component Level Repair ComPair Computer aided rePair CP Connected Planet / Copy Protection CSM Customer Service Mode CTI Color Transient Improvement:

manipulates steepness of chroma

transients CVBS Composite Video Blanking and

Synchronization DAC Digital to Analogue Converter DBE Dynamic Bass Enhancement: extra

low frequency amplification DCM Data Communication Module. Also

referred to as System Card or

Smartcard (for iTV). DDC See “E-DDC” D/K Monochrome TV system. Sound

carrier distance is 6.5 MHz DFI Dynamic Frame Insertion

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Precautions, Notes, and Abbreviation List

EN 9Q551.2E LA 3.

DFU Directions For Use: owner's manual DMR Digital Media Reader: card reader DMSD Digital Multi Standard Decoding DNM Digital Natural Motion DNR Digital Noise Reduction: noise

reduction feature of the set DRAM Dynamic RAM DRM Digital Rights Management DSP Digital Signal Processing DST Dealer Service Tool: special remote

control designed for service

technicians DTCP Digital Transmission Content

Protection; A protocol for protecting

digital audio/video content that is

traversing a high speed serial bus,

such as IEEE-1394 DVB-C Digital Video Broadcast - Cable DVB-T Digital Video Broadcast - Terrestrial DVD Digital Versatile Disc DVI(-d) Digital Visual Interface (d= digital only) E-DDC Enhanced Display Data Channel

(VESA standard for communication

channel and display). Using E-DDC,

the video source can read the EDID

information form the display. EDID Extended Display Identification Data

(VESA standard) EEPROM Electrically Erasable and

Programmable Read Only Memory EMI Electro Magnetic Interference EPG Electronic Program Guide EPLD Erasable Programmable Logic Device EU Europe EXT EXTernal (source), entering the set by

SCART or by cinches (jacks) FDS Full Dual Screen (same as FDW) FDW Full Dual Window (same as FDS) FLASH FLASH memory FM Field Memory or Frequency

Modulation FPGA Field-Programmable Gate Array FTV Flat TeleVision Gb/s Giga bits per second G-TXT Green TeleteXT H H_sync to the module HD High Definition HDD Hard Disk Drive HDCP High-bandwidth Digital Content

Protection: A “key” encoded into the

HDMI/DVI signal that prevents video

data piracy. If a source is HDCP coded

and connected via HDMI/DVI without

the proper HDCP decoding, the

picture is put into a “snow vision” mode

or changed to a low resolution. For

normal content distribution the source

and the display device must be

enabled for HDCP “software key”

decoding. HDMI High Definition Multimedia Interface HP HeadPhone I Monochrome TV system. Sound

C Inter IC bus

D Inter IC Data bus

S Inter IC Sound bus

carrier distance is 6.0 MHz

IF Intermediate Frequency IR Infra Red IRQ Interrupt Request ITU-656 The ITU Radio communication Sector

(ITU-R) is a standards body

subcommittee of the International

Telecommunication Union relating to

radio communication. ITU-656 (a.k.a.

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SDI), is a digitized video format used for broadcast grade video. Uncompressed digital component or digital composite signals can be used. The SDI signal is self-synchronizing, uses 8 bit or 10 bit data words, and has a maximum data rate of 270 Mbit/s, with a minimum bandwidth of 135 MHz.

iTV Institutional TeleVision; TV sets for

hotels, hospitals etc.

LS Last Status; The settings last chosen

by the customer and read and stored in RAM or in the NVM. They are called at start-up of the set to configure it according to the customer's

preferences LATAM Latin America LCD Liquid Crystal Display LED Light Emitting Diode L/L' Monochrome TV system. Sound

carrier distance is 6.5 MHz. L' is Band

I, L is all bands except for Band I LPL LG.Philips LCD (supplier) LS Loudspeaker LVDS Low Voltage Differential Signalling Mbps Mega bits per second M/N Monochrome TV system. Sound

carrier distance is 4.5 MHz MHEG Part of a set of international standards

4. Mechanical Instructions

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Index of this chapter:

Cable Dressing

4.1

4.2 Service Positions

4.3 Assy/Panel Removal Oscar Styling (xxPFL96xx/xx series)

4.4 Assy/Panel Removal Sundance Styling (xxPFL7xxx/xx series)

4.5 Assy/Panel Removal Cannes Styling (xxPFL8xxx/xx series)

4.6 Set Re-assembly

Notes:

4.1 Cable Dressing

• Figures below can deviate slightly from the actual situation, due to the different set executions.

Figure 4-1 Cable dressing 32PFL9606x/xx (Oscar 32")

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Figure 4-2 Cable dressing 37PFL9606x/xx (Oscar 37")

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Figure 4-3 Cable dressing 40PFL8606x/xx (Cannes 40")

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Mechanical Instructions

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Figure 4-4 Cable dressing 46PFL8606x/xx (Cannes 46")

Figure 4-5 Cable dressing 46PFL9706x/xx (Oscar 46")

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Figure 4-6 Cable dressing 50PFL7956x/xx (Sundance 50")

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Figure 4-7 Cable dressing 52PFL9606x/xx (Oscar 52")

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Figure 4-8 Cable dressing 58PFL9956x/xx (Oscar 58")

4.2 Service Positions

For easy servicing of a TV set, the set should be put face down on a soft flat surface, foam buffers or other specific workshop tools. Ensure that a stable situation is created to perform measurements and alignments. When using foam bars take care that these always support the cabinet and never only the display. Caution: Failure to follow these guidelines can seriously damage the display! Ensure that ESD safe measures are taken.

4.3 Assy/Panel Removal Oscar Styling (xxPFL96xx/xx series)

The instructions apply to the 32PFL9606H/12.

Caution

When removing the SSB, the board should not be handled by touching the heatsink of the PNX85500. Refer to section 5.8.11

ceramic heatsink application on the PNX85500.

4.3.1 Rear Cover

Warning: Disconnect the mains power cord before you remove

the rear cover. Refer to Figure 4-9

Additional information for replacing the

for details.

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Mechanical Instructions

1. Remove the stand [1].

2. Remove all screws of the rear cover [2] and [3].

3. Lift the rear cover from the TV. Make sure that wires and flat coils are not damaged while lifting the rear cover from the set.

4.3.2 Speakers

The speakers are located in the stand. When defective, replace the whole unit.

4.3.3 Mains Switch

The mains switch is mounted on a plastic subframe and can be removed without removing the subframe. When defective, replace the whole unit.

4.3.4 Keyboard Control, IR & LED Board

Release the catches and take the board out. When defective, replace the whole unit.

4.3.5 IR Blaster

Release the catches and take the board out. When defective, replace the whole unit.

4.3.6 WiFi antennas

Release the catches and take the board out. When defective, replace the whole unit.

Figure 4-9 Rear cover removal

4.3.7 Ambilight Units

Refer to Figure 4-10

and Figure 4-11 for details.

Figure 4-10 Ambilight units -1-

1. Locate the separator [1].

2. Gently lift the diffusor [2] near the separator [1], slide the diffusor [3] and take the diffusor out.

3. Lift the catches gently [4] while sliding the Ambilight PWB out. Use a dedicated tool such as a screwdriver.

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6 6 6

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When defective, replace the whole unit.

4.3.8 LCD Panel

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Figure 4-11 Ambilight units -2-

Refer to Figure 4-12

and Figure 4-13 for details.

Figure 4-12 LCD panel

1. Remove the AL units as earlier described.

2. Remove the power switch with the power inlet subframe [1].

3. Remove the SSB [2].

4. Remove the PSU [3].

5. Remove the WiFi module [4].

6. Remove the AL subframes [5].

7. Remove the stand and -support as described earlier.

8. Remove all remaining cables and subframes.

9. Remove the clamps [6].

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Figure 4-13 LCD panel -2-

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Figure 4-15 Mains switch

Figure 4-14 LCD panel -3-

4.4 Assy/Panel Removal Sundance Styling (xxPFL7xxx/xx series)

The instructions apply to the 32PFL7406K/02.

4.4.1 Rear Cover

Warning: Disconnect the mains power cord before you remove

the rear cover. Note: it is not necessary to remove the stand while removing the rear cover.

1. Remove all screws of the rear cover.

2. Lift the rear cover from the TV. Make sure that wires and

flat coils are not damaged while lifting the rear cover from the set.

4.4.2 Speakers

Tweeters

Each tweeter unit is mounted with one screw. When defective, replace the whole unit.

Subwoofer

The central subwoofer is located in the centre of the set and is secured by two bosses. When defective, replace the whole unit.

4.4.3 Mains Switch

Refer to Figure 4-15

for details.

The mains switch is mounted on a plastic subframe and can be removed without removing the subframe.

1. Use a screwdriver and push the switch out of its casing [1].

2. Unplug the connectors. When defective, replace the whole unit.

4.4.4 Main Power Supply

Refer to Figure 4-16

for details.

Figure 4-16 Main Power Supply

1. Unplug all connectors [1].

2. Remove the fixation screws [2].

3. Take the board out. When defective, replace the whole unit.

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Refer to Figure 4-17

for details.

Figure 4-17 SSB

1. Unplug all connectors [1].

2. Remove the fixation screws [2].

3. Take the board out. When remounting, ensure that the side shielding is positioned correctly.

Figure 4-19 Keyboard control, IR & LED board [2/2]

1. Remove the stand and the plastic support [1].

2. Unplug the connector [2].

3. Remove the screws [3] and take the board out. When defective, replace the whole unit.

4.4.7 Ambilight Units

The Ambilight units can be lifted from the subframes without the use of tools. Refer to Figure 4-20

for details.

4.4.6 Keyboard Control, IR & LED Board

Refer to Figure 4-18

and Figure 4-19 for details.

Figure 4-20 Ambilight units

1. Unplug the connector [1].

2. Carefully lift the board [2] and take the board out. When defective, replace the whole unit.

Figure 4-18 Keyboard control, IR & LED board [1/2]

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4.4.8 LCD Panel

Mechanical Instructions

Refer to Figure 4-21

and Figure 4-22 for details.

Figure 4-21 LCD panel [1/2]

1. Remove the SSB as described earlier.

2. Remove the PSU as described earlier.

3. Remove the tweeters with their subframes and subwoofer

as described earlier.

4. Remove the stand and -support as described earlier.

5. Remove the cables [1].

6. Remove the stand subframe [2].

7. Remove the mains switch subframe [3].

8. Remove the Ambilight units together with their subframes

as described earlier.

9. Unplug the connector from the keyboard control-, and IR &

LED board as described earlier.

10. Remove all remaining cables and subframes.

11. Use a screwdriver to release the clamps [4] that secure the

panel and take the panel out. Remove the clamps from the panel before sending the panel in for Service.

Figure 4-22 LCD panel [2/2]

4.5 Assy/Panel Removal Cannes Styling (xxPFL8xxx/xx series)

The Cannes styling is similar to the Sundance, except for the removal of the rear cover. Special attention is required to avoid pollution of the glass plate when mounting a new LCD panel.

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4.5.1 Rear Cover

Warning: Disconnect the mains power cord before you remove

the rear cover.

Refer to Figure 4-23

for details.

Figure 4-23 Rear cover

1. Remove all screws of the rear cover.

2. Release the catches from the rear cover using a screwdriver as indicated in Figure 4-23

3. Lift the rear cover from the TV. Make sure that wires and flat coils are not damaged while lifting the rear cover from the set.

4.6 Set Re-assembly

To re-assemble the whole set, execute all processes in reverse order.

Notes:

• While re-assembling, make sure that all cables are placed and connected in their original position.

• Pay special attention not to damage the EMC foams in the set. Ensure that EMC foams are mounted correctly.

4.5.2 LCD Panel

When mounting a new LCD panel, pay attention to clean the inside of the glass plate before mounting a new panel.

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Service Modes, Error Codes, and Fault Finding

5. Service Modes, Error Codes, and Fault Finding

Index of this chapter:

Test Points

5.1

5.2 Service Modes

5.3 Stepwise Start-up

5.4 Service Tools

5.5 Error Codes

5.6 The Blinking LED Procedure

5.7 Protections

5.8 Fault Finding and Repair Tips

5.9 Software Upgrading

5.1 Test Points

As most signals are digital, it will be difficult to measure waveforms with a standard oscilloscope. However, several key ICs are capable of generating test patterns, which can be controlled via ComPair. In this way it is possible to determine which part is defective.

Perform measurements under the following conditions:

• Service Default Mode.

• Video: Colour bar signal.

• Audio: 3 kHz left, 1 kHz right.

5.2 Service Modes

Service Default mode (SDM) and Service Alignment Mode (SAM) offers several features for the service technician, while the Customer Service Mode (CSM) is used for communication between the call centre and the customer.

• All service-unfriendly modes (if present) are disabled, like: – (Sleep) timer. – Child/parental lock. – Picture mute (blue mute or black mute). – Automatic volume levelling (AVL). – Skip/blank of non-favourite pre-sets.

How to Activate SDM

For this chassis there are two kinds of SDM: an analogue SDM and a digital SDM. Tuning will happen according Table 5-1

• Analogue SDM: use the standard RC-transmitter and key in the code “062596”, directly followed by the “MENU” (or “HOME”) button. Note: It is possible that, together with the SDM, the main menu will appear. To switch it “off”, push the “MENU” (or "HOME") button again. Analogue SDM can also be activated by grounding for a moment the solder path on the SSB, with the indication “SDM” (see Service mode pad

• Digital SDM: use the standard RC-transmitter and key in the code “062593”, directly followed by the “MENU” (or "HOME") button. Note: It is possible that, together with the SDM, the main menu will appear. To switch it “off”, push the “MENU” (or "HOME") button again.

This chassis also offers the option of using ComPair, a hardware interface between a computer and the TV chassis. It offers the abilities of structured troubleshooting, error code reading, and software version read-out for all chassis. (see also section “5.4.1

Note: For the new model range, a new remote control (RC) is used with some renamed buttons. This has an impact on the activation of the Service modes. For instance the old “MENU” button is now called “HOME” (or is indicated by a “house” icon).

5.2.1 Service Default Mode (SDM)

Purpose

• To create a pre-defined setting, to get the same measurement results as given in this manual.

• To override SW protections detected by stand-by processor and make the TV start up to the step just before protection (a sort of automatic stepwise start-up). See section “5.3

• To start the blinking LED procedure where only LAYER 2 errors are displayed. (see also section “5.5

Specifications

Table 5-1 SDM default settings

Region Freq. (MHz)

Europe, AP(PAL/Multi) 475.25 PAL B/G Europe, AP DVB-T 546.00 PID

• All picture settings at 50% (brightness, colour, contrast).

• Sound volume at 25%.

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ComPair”).

Stepwise Start-up”.

Video: 0B 06 PID PCR: 0B 06 PID Audio: 0B 07

Error Codes”).

Default system

DVB-T

Figure 5-1 Service mode pad

After activating this mode, “SDM” will appear in the upper right corner of the screen (when a picture is available).

How to Navigate

When the “MENU” (or “HOME”) button is pressed on the RC transmitter, the TV set will toggle between the SDM and the normal user menu.

How to Exit SDM

Use one of the following methods:

• Switch the set to STAND-BY via the RC-transmitter.

• Via a standard customer RC-transmitter: key in “00”sequence.

5.2.2 Service Alignment Mode (SAM)

Purpose

• To perform (software) alignments.

• To change option settings.

• To easily identify the used software version.

• To view operation hours.

• To display (or clear) the error code buffer.

How to Activate SAM

Via a standard RC transmitter: Key in the code “062596” directly followed by the “INFO” or “OK” button. After activating SAM with this method a service warning will appear on the screen, continue by pressing the “OK” button on the RC.

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PHILIPS

MODEL:

32PF9968/10

PROD.SERIAL NO: AG 1A0620 000001

040

39mm

27mm

(CTN Sticker)

Display Option

Code

Service Modes, Error Codes, and Fault Finding

EN 23Q551.2E LA 5.

Contents of SAM

• Hardware Info. – A. SW Version. Displays the software version of the

main software (example: Q555X-1.2.3.4 = AAAAB_X.Y.W.Z).

• AAAA= the chassis name.

• B= the SW branch version. This is a sequential number (this is no longer the region indication, as the software is now multi-region).

• X.Y.W.Z= the software version, where X is the main version number (different numbers are not compatible with one another) and Y.W.Z is the sub version number (a higher number is always compatible with a lower number).

– B. STBY PROC Version. Displays the software

version of the stand-by processor.

– C. Production Code. Displays the production code of

Figure 5-2 Location of Display Option Code sticker

the TV, this is the serial number as printed on the back of the TV set. Note that if an NVM is replaced or is initialized after corruption, this production code has to be re-written to NVM. ComPair will foresee in a possibility to do this.

• Operation Hours. Displays the accumulated total of operation hours (not the stand-by hours). Every time the TV is switched “on/off”, 0.5 hours is added to this number.

• Errors (followed by maximum 10 errors). The most recent error is displayed at the upper left (for an error explanation see section “5.5

Error Codes”).

• Reset Error Buffer. When “cursor right” (or “OK” button) pressed here, followed by the “OK” button, the error buffer is reset.

• Alignments. This will activate the “ALIGNMENTS” submenu. See Chapter 6.

Alignments.

• Dealer Options. Extra features for the dealers.

• Options numbers. Extra features for Service. For more info regarding option codes, see chapter 6.

Alignments.

Note that if the option code numbers are changed, these have to be confirmed with pressing the “OK” button before the options are stored, otherwise changes will be lost.

• Initialize NVM. The moment the processor recognizes a corrupted NVM, the “initialize NVM” line will be highlighted. Now, two things can be done (dependent of the service instructions at that moment): – Save the content of the NVM via ComPair for

development analysis, before initializing. This will give the Service department an extra possibility for diagnosis (e.g. when Development asks for this).

– Initialize the NVM.

• Store - go right. All options and alignments are stored when pressing “cursor right” (or the “OK” button) and then the “OK”-button.

• Operation hours display. Displays the accumulated total of operation hours of the screen itself. In case of a display replacement, reset to “0” or to the consumed operation hours of the spare display.

• SW Maintenance. – SW Events. In case of specific software problems, the

development department can ask for this info.

– HW Events. In case of specific software problems, the

development department can ask for this info :

- Event 26: refers to a power dip, this is logged after the TV set reboots due to a power dip.

- Event 17: refers to the power OK status, sensed even before the 3 x retry to generate the error code.

• Test settings. For development purposes only.

• Development file versions. Not useful for Service purposes, this information is only used by the development department.

• Upload to USB. To upload several settings from the TV to an USB stick, which is connected to the SSB. The items are “Personal settings”, “Option codes”, “Alignments”, “Identification data” (includes the set type and prod code + all 12NC like SSB, display, boards), “History list”. The “All” item supports to upload all several items at once.

A directory “repair\” will be created in the root of the USB stick.

To upload the settings, select each item separately, press “cursor right” (or the “OK” button), confirm with “OK” and

Note: When the NVM is corrupted, or replaced, there is a high possibility that no picture appears because the display code is not correct. So, before initializing the NVM via the SAM, a picture is necessary and therefore the correct display option has to be entered. Refer to Chapter 6.

Alignments for details.

To adapt this option, it’s advised to use ComPair (the correct values for the options can be found in Chapter 6.

Alignments)

or a method via a standard RC (described below). Changing the display option via a standard RC: Key in the code “062598” directly followed by the “MENU” (or "HOME") button and “XXX” (where XXX is the 3 digit decimal display code as mentioned on the sticker in the set). Make sure to key in all three digits, also the leading zero’s. If the above action is successful, the front LED will go out as an indication that the RC sequence was correct. After the display option is changed in the NVM, the TV will go to the Stand-by mode. If the NVM was corrupted or empty before this action, it will be initialized first (loaded with default values). This initializing can take up to 20 seconds.

wait until the message “Done” appears. In case the download to the USB stick was not successful, “Failure” will be displayed. In this case, check if the USB stick is connected properly and if the directory “repair” is present in the root of the USB stick. Now the settings are stored onto the USB stick and can be used to download into another TV or other SSB. Uploading is of course only possible if the software is running and preferably a picture is available. This method is created to be able to save the customer’s TV settings and to store them into another SSB. Important remark : to upload the “channel list”, select “Home” => “Setup” => “TV settings” => “Preferences” => “Channel list copy” => “Copy to USB”.The procedure of “channel map cloning” is clearly described in the (electronic) user manual.

• Download from USB. To download several settings from the USB stick to the TV, same way of working needs to be followed as described in “Upload to USB”. The “All” item supports to download all several items at once.

Important remark : to download the “channel list”, select “Home” => “Setup” => “TV settings” => “Preferences” => “Channel list copy” => “Copy to TV”. The procedure of “channel map cloning” is clearly described in the (electronic) user manual.

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Service Modes, Error Codes, and Fault Finding

• NVM editor. For NET TV the set “type number” must be entered correctly. Also the production code (factory location code) can be entered here via the RC-transmitter. Correct data can be found on the side/rear sticker.

How to Navigate

• In SAM, the menu items can be selected with the “CURSOR UP/DOWN” key on the RC-transmitter. The selected item will be highlighted. When not all menu items fit on the screen, move the “CURSOR UP/DOWN” key to display the next/previous menu items.

• With the “CURSOR LEFT/RIGHT” keys, it is possible to: – (De) activate the selected menu item. – (De) activate the selected sub menu.

• With the “OK” key, it is possible to activate the selected action.

How to Exit SAM

Use one of the following methods:

• Switch the TV set to STAND-BY via the RC-transmitter.

• Via a standard RC-transmitter, key in “00” sequence, or select the “BACK” key.

5.2.3 Customer Service Mode (CSM)

Purpose

When a customer is having problems with his TV-set, he can call his dealer or the Customer Helpdesk. The service technician can then ask the customer to activate the CSM, in order to identify the status of the set. Now, the service technician can judge the severity of the complaint. In many cases, he can advise the customer how to solve the problem, or he can decide if it is necessary to visit the customer. The CSM is a read only mode; therefore, modifications in this mode are not possible.

Provided CSM is activated, a test pattern can be displayed during 5 seconds (1 second Blue, 1 second Green and 1 second Red, then again 1 second Blue and 1 second Green). This test pattern is generated by the PNX51X0 (part of the display). So if this test pattern is shown, it could be determined that the back end video chain (PNX51X0 and display) is working.For TV sets without the PNX51X0 inside, every menu from CSM will be used as check for the back end chain video.

When CSM is activated and there is a USB stick connected to the TV set, the software will dump the CSM content to the USB stick. The file (CSM_model number_serial number.txt) will be saved in the root of the USB stick. This info can be handy if no information is displayed.

Additional in CSM mode (with USB stick connected), pressing “OK” will create an extended CSM dump file on the USB stick. This file (Extended_CSM_model number_serial number.txt) contains:

• The normal CSM dump information,

• All items (from SAM “load to USB”, but in readable format),

• Operating hours,

• Error codes,

• SW/HW event logs.

To have fast feedback from the field, a flashdump can be requested by development. When in CSM, push the “red” button and key in serial digits ‘2679’ (same keys to form the word ‘COPY’ with a cellphone). A file “Dump_model number_serial number.bin” will be written on the connected USB device. This can take 1/2 minute, depending on the quantity of data that needs to be dumped.

Also when CSM is activated, the LAYER 1 error is displayed via blinking LED. Only the latest error is displayed (see also section 5.5

Error Codes).

How to Activate CSM

Key in the code “123654” via the standard RC transmitter. Note: Activation of the CSM is only possible if there is no (user) menu on the screen!

How to Navigate

By means of the “CURSOR-DOWN/UP” knob on the RCtransmitter, can be navigated through the menus.

Contents of CSM

The contents are reduced to 3 pages: General, Software versions and Quality items. The group names itself are not shown anywhere in the CSM menu.

General

• Set Type. This information is very helpful for a helpdesk/ workshop as reference for further diagnosis. In this way, it is not necessary for the customer to look at the rear of the TV-set. Note that if an NVM is replaced or is initialized after corruption, this set type has to be re-written to NVM. ComPair will foresee in a possibility to do this. The update can also be done via the NVM editor available in SAM.

• Production Code. Displays the production code (the serial number) of the TV. Note that if an NVM is replaced or is initialized after corruption, this production code has to be re-written to NVM. ComPair will foresee in a possibility to do this. The update can also be done via the NVM editor available in SAM.

• Installed date. Indicates the date of the first installation of the TV. This date is acquired via time extraction.

• Options 1. Gives the option codes numbers of option group 1 as set in SAM (Service Alignment Mode).

• Options 2. Gives the option codes numbers of option group 2 as set in SAM (Service Alignment Mode).

• 12NC SSB. Gives an identification of the SSB as stored in NVM. Note that if an NVM is replaced or is initialized after corruption, this identification number has to be re-written to NVM. ComPair will foresee in a possibility to do this. This identification number is the 12nc number of the SSB.

• 12NC display. Shows the 12NC of the display.

• 12NC supply. Shows the 12NC of the power supply.

• 12NC 200Hz board. Shows the 12NC of the 200Hz Panel (when present).

• 12NC AV PIP. Shows the 12NC of the AV PIP board (when present).

Software versions

• Current main SW. Displays the build-in main software version. In case of field problems related to software, software can be upgraded. As this software is consumer upgradeable, it will also be published on the Internet. Example: Q55xx1.2.3.4

• Standby SW. Displays the build-in stand-by processor software version. Upgrading this software will be possible via ComPair or via USB (see section 5.9

Software Upgrading).

Example: STDBY_83.84.0.0.

• e-UM version. Displays the electronic user manual SWversion (12NC version number). Most significant number here is the last digit.

• FPGA dimming software.Displays the backlight FPGA software version.Device processes the dimming + scanning and 3D LED.

• AV PIP software. not applicable.

• 3D dongle software version. not applicable.

• FRC-V software.Represence software version for the Frame Rate Convertor(Vx1 - or LVDS version).

• FPGA HDR software.

• FPGA lattice backlight software.

• FPGA C-balancer software.

• FPGA PQ software. Displays the picture quality FPGA software version.Device supports contrast/sharpness improvement, 2D-3D conversion and 3D-3D depth

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100402

Active

Semi St by

St by

Mains

off

GoToProtection

-WakeUp re quested

-Acquisition needed

-Tact switch pushed

- stby requested and no data Acquisition required

- St by requested

-tact SW pushed

WakeUp

requested

Protection

WakeUp

requested

(SDM)

GoToProtection

Hibernate

-Tact switch pushed

-last status is hibernate after mains ON

Tact switch

pushed

EN 25Q551.2E LA 5.

adaptation + 3D IR LED in case of no backlight FPGA present.

Quality items

• Signal quality. Bad / average /good (not for DVB-S).

• Ethernet MAC address. Displays the MAC address present in the SSB.

• Wireless MAC address. Displays the wireless MAC address to support the Wi-Fi functionality.

• BDS key. Indicates if the set is in the BDS status.

• CI module. Displays status if the common interface module is detected.

• CI + protected service. Yes/No.

• Event counter : S : 000X 0000(number of software recoveries : SW EVENT-LOG #(reboots) S : 0000 000X (number of software events : SW EVENTLOG #(events) H : 000X 0000(number of hardware errors) H : 0000 000X (number of hardware events : SW EVENTLOG #(events).

How to Exit CSM

Press “MENU” (or "HOME") / “Back” key on the RC-transmitter.

5.3 Stepwise Start-up

When the TV is in a protection state due to an error detected by standby software (error blinking is displayed) and SDM is activated via shortcutting the SDM solder path on the SSB, the TV starts up until it reaches the situation just before protection. So, this is a kind of automatic stepwise start-up. In combination with the start-up diagrams below, you can see which supplies are present at a certain moment. Caution: in case the start-up in this mode with a faulty FET 7U0X is done, you can destroy all IC’s supplied by the +1V8 and +1v1, due to overvoltage (12V on XVX-line). It is recommended to measure first the FET 7U0X or others FET’s on shortcircuit before activating SDM via the service pads.

The abbreviations “SP” and “MP” in the figures stand for:

• SP: protection or error detected by the Stand-by Processor.

• MP: protection or error detected by the MIPS Main

Processor.

Figure 5-3 Transition diagram

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EN 26 Q551.2E LA5.

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100216

EJTAG probe

connected ?

Yes

Release AVC system reset

Feed warm boot script

Cold boot?

Yes

Set I²C slave address

of Standby µP to (A0h)

An EJTAG probe (e.g . Win dPo w e r ICE pr o be) can be connected for Linux Kernel debugging purposes.

Detect EJTAG debug probe

(pulling pin of the probe interface to

ground by inserting EJTAG probe)

Release AVC system reset

Feed cold boot script

Release AVC system reset Feed initializing boot script

disable alive mechanism

Off

Standby Supply starts running.

All standby supply voltages become available.

st-by µP resets

Stand by or

Protection

Mains is applied

- Switch Audio-Reset high.

It is low in the standby mode if the standby

mode lasted longer than 10s.

start keyboard scanning, RC detection. Wake up reasons are

off.

If the protection state was left by short circuiting the

SDM pins, detection of a protection condition during

startup will stall the startup. Protection conditions in a

playing set will be ignored. The protection mode will

not be entered.

Detect2 is moved to an interrupt. To be checked if the detection on interrupt base is feasible or not or if we should stick to the standard 40ms interval.

+12V, +24Vs, AL and Bolt-on power

isswitched on, followed by the +1V2 DCDC converter

Enable the supply detection algorithm

Switch ON Platform and display supply by switching

LOW the Standby line.

Initialise I/O pins of the st-by µP:

- Switch reset-AVC LOW (reset state)

- Switch reset-system LOW (resetstate)

- Switch reset-Ethernet LOW (reset state)

- Switch reset-USB LOW (reset state)

- Switch reset-DVBs LOW (reset state)

-keep Audio-reset and Audio-Mute-Up HIGH

Enable the DCDC converters

(ENABLE-3V3n LOW)

Detect2 high received

within 2 seconds?

12V error: Layer1: 3

Layer2: 16

Enter protection

Yes

Wait 50ms

Service Modes, Error Codes, and Fault Finding

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Figure 5-4 “Off” to “Semi Stand-by” flowchart (part 1)

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18770_252_100216.eps

100216

Yes

MIPS reads the wake up reason

from standby µP.

Semi-Standby

initialize tuner and channel decoders

Initialize video processing IC’s

Initialize source selection

initialize AutoTV by triggering CHS AutoTV Init interface

3-th try?

Blink Code as

error code

Bootscript ready

in 1250 ms?

Yes

Enable Alive check mechanism

Wait until AVC starts to

communicate

SW initialization

succeeded

within 20s?

Switch StandbyI/O line high

and wait 4 seconds

RPC start (comm. protocol)

Set I²C slave address

of Standby µP to (60h)

Yes

Disable all supply related protections and

switch off the +3V3 +5V DC/DC converter.

switch off the remaining DC/DC

converters

Wait 5ms

Switch AVC PNX85500 in

reset (active low)

Wait 10ms

Flash to Ram

image transfer succeeded

within 30s?

Yes

Code =

Layer1: 2

Layer2: 53

Code =

Layer1: 2

Layer2: 15

Initialize Ambilight with Lights off.

Timing need to be updated if more mature info is available.

Timing needs to be updated if more mature info is available.

Initialize audio

Enter protection

Reset-system is switched HIGH by the

AVC at the end of the bootscript

AVC releases Reset-Ethernet, Reset-USB and

Reset-DVBs when the end of the AVC boot-

script is detected

This cannot be done through the bootscript, the I/O is on the standby µP

Reset-Audio and Audio-Mute-Up are

switched by MIPS code later on in the

startup process

Reset-system is switched HIGH by the

AVC at the end of the bootscript

Reset-Audio and Audio-Mute-Up are

switched by MIPS code later on in the

startup process

Wake up reason

coldboot & not semi-

standby?

85500 sends out startup screen

Startup screen cfg file

present?

85500 starts up the display.

Startup screen visible

yes

To keep this flowchart readable, the exact display turn on description is not copied here. Please see the Semi-standby to On description for the detailed display startup

sequence.

During the complete display time of the Startup screen, the preheat condition of

100% PWM is valid.

Startup screen shall only be visible when there is a coldboot to an active state end situation. The startup screen shall not be visible when waking up for reboot reasons or waking up to semi- standby conditions or waking up to enter Hibernate mode..

The first time after the option turn on of the startup screen or when the set is virgin, the cfg file is not present and hence the startup screen will not be shown.

AVC releases Reset-Ethernet, Reset-USB and

Reset-DVBs when the end of the AVC boot-

script is detected

200Hz set?

yes

85500 sends out startup screen

200Hz Tcon has started up the

display.

Startup screen visible

85500 requests Lamp on

EN 27Q551.2E LA 5.

Figure 5-5 “Off” to “Semi Stand-by” flowchart (part 2)

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18770_253_100216.eps

100216

Active

Semi Standby

Initialize audio and video

processing IC's and functions

according needed use case.

Assert RGB video blanking

and audio mute

Wait until previous on-state is left more than2

secondsago. (to prevent LCD display problems)

The assumption here is that a fast toggle (<2s) can

only happen during ON->SEMI ->ON. In these states,

the AVC is still active and can provide the 2s delay. A

transition ON->SEMI->STBY->SEMI->ON cannot be

made in less than 2s, because the standby state will

be maintained for at least 4s.

Switch Audio-Reset low and wait 5ms

Constraints taken into account:

-Display may only be started when valid LVDS output clock can be delivered by the AVC.

-To have a reliable operation of the EEFL backlight, the backlight should be driven with a maximum PWM duty cycle during the first seconds. Only after this first one or two seconds, the PWM may be set to the required output level (Note that the PWM output should be present before the back

light is switched on). To minimize the artefacts,

the picture should only be unblanked after these first seconds.

Restore dimming backlight feature, PWM and BOOST output

and unblank the video.

Wait until valid and stable audio and video, corresponding to the

requested output is delivered by the AVC

AND

the backlight has been switched on for at least the time which is

indicated in the display file as preheat time.

The higher level requirement is that audio and video should be demuted without transient effects and that the audio should be demuted maximum 1s before or

at the same time as the unblanking of the video.

Release audio mute and wait 100ms before any other audio

handling is done (e.g. volume change)

CPipe already generates a valid output clock in the semi-standby state: display

startup can start immediately when leaving

the semi-standby state.

Switch on LCD backlight (Lamp-ON)

Switch off the dimming backlight feature, set

the BOOST control to nominal and make sure PWM output is set to maximum allowed PWM

Switch on the Ambilight functionality according the last status

settings.

Delay Lamp-on with the sum of the LVDS delay and

the Lamp delay indicated in the display file

Switch on the displaypowerby

switching LCD-PWR-ON low

Wait x ms

Switch on LVDS output in the 85500

The exact timings to

switch on the

display(LVDS

delay, lamp delay)

are defined in the

display file.

Start POK line

detection algorithm

return

Display already on?

(splash screen)

Yes

Display cfg file present

and up to date, according

correct display option?

Startup screen Option and Installation setting

Photoscreen ON?

Yes

Prepare Start screen Display config

file and copy to Flash

Yes

A LED set does not normally need a

preheat time. The preheat remains present

but is set to zero in the display file.

Service Modes, Error Codes, and Fault Finding

Figure 5-6 “Semi Stand-by” to “Active” flowchart (EEFL or LED backlight 50/100 Hz only)

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Service Modes, Error Codes, and Fault Finding

18770_254_100216.eps

100216

Active

Semi Standby

Initialize audio and video

processing IC's and functions

according needed use case.

Assert RGB video blanking

and audio mute

Wait until previous on-state is left more than2

secondsago. (to prevent LCD display problems)

The assumption here is that a fast toggle (<2s)

can only happen during ON->SEMI ->ON. In these states, the AVC is still active and can

provide the 2s delay. If the transition ON->SEMI-

>STBY->SEMI->ON can be made in less than 2s,

we have to delay the semi -> stby transition until

the requirement is met.

Switch Audio-Reset low and wait 5ms

unblank the video.

Wait until valid and stable audio and video, corresponding to

the requested output is delivered by the AVC.

The higher level requirement is that audio and

video should be demuted without transient

effects and that the audio should be demuted

maximum 1s before or at the same time as the

unblanking of the video.

Release audio mute and wait 100ms before any other audio

handling is done (e.g. volume change)

Request Tcon to Switch on the backlight in a

direct LED or

set Lamp-on I/O line in case of a side LED

Switch on the Ambilight functionality according the last status

settings.

There is no need to define the

display timings since the timing

implementation is part of the Tcon.

Start POK line

detection algorithm

return

Display cfg file present

and up to date, according

correct display option?

Startup screen Option

and Installation setting

Photoscreen ON?

Yes

Prepare Start screen Display config

file and copy to Flash

Yes

Backlight already on?

(splash screen)

Yes

EN 29Q551.2E LA 5.

Figure 5-7 “Semi Stand-by” to “Active” flowchart (LED backlight 200 Hz)

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100216

Semi Standby

Active

Wait x ms (display file)

Mute all sound outputs via softmute

Mute all video outputs

switch off LCD backlight

(I/O or I²C)

Force ext audio outputs to ground

(I/O: audio reset)

And wait 5ms

switch off Ambilight

Set main amplifier mute (I/O: audio-mute)

Wait 100ms

Wait until Ambilight has faded out: Output power

Observer should be zero

Switch off the displaypowerby

switching LCD-PWR-ON high

Wait x ms

Switch off LVDS output in 85500

The exact timings to

switch off the

display(LVDS

delay, lamp delay)

are defined in the

display file.

Switch off POK line

detection algorithm

200Hz set?

Yes

Instruct 200Hz

Tcon to turn off

the display

Service Modes, Error Codes, and Fault Finding

2011-Sep-09

Figure 5-8 “Active” to “Semi Stand-by” flowchart

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Service Modes, Error Codes, and Fault Finding

18770_256_100216.eps

100216

transfer Wake up reasons to the Stand by µP.

Stand by

Semi Stand by

Disable all supply related protections and switch off

the DC/DC converters (ENABLE-3V3n)

Switch OFF all supplies by switching HIGH the

Standby I/O line

Switch AVC system in reset state (reset-system and

reset-AVC lines)

Switch reset-USB, Reset-Ethernet and Reset-DVBs

LOW

Important remarks:

release reset audio 10 sec after entering

standby to save power

Also here, the standby state has to be

maintained for at least 4s before starting

another state transition.

Wait 5ms

Wait 10ms

Delay transition until ramping down of ambient light is

finished. *)

If ambientlight functionality was used in semi-standby

(lampadaire mode), switch off ambient light (see CHS

ambilight)

*) If this is not performed and the set is switched to standby when the switch off of the ambilights is still ongoing, the lights will switch off abruptly when the supply is cut.

Switch Memories to self-refresh (this creates a more

stable condition when switching off the power).

EN 31Q551.2E LA 5.

Figure 5-9 “Semi Stand-by” to “Stand-by” flowchart

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10000_036_090121.eps

091118

UART SERVICE

CONNECTOR

UART SERVICE

CONNECTOR

TO I2C SERVICE CONNECTOR

TO TV

HDMI I

C only

Optional power

5V DC

ComPair II Developed by Philips Brugge

RC out

RC in

Optional

Switch

Power ModeLink/

Activity

ComPair II

Multi

function

RS232 /UART

Service Modes, Error Codes, and Fault Finding

5.4 Service Tools

5.4.1 ComPair

Introduction

ComPair (Computer Aided Repair) is a Service tool for Philips Consumer Electronics products and offers the following:

1. ComPair helps to quickly get an understanding on how to repair the chassis in a short and effective way.

2. ComPair allows very detailed diagnostics and is therefore capable of accurately indicating problem areas. No knowledge on I because ComPair takes care of this.

3. ComPair speeds up the repair time since it can automatically communicate with the chassis (when the µP is working) and all repair information is directly available.

4. ComPair features TV software up possibilities.

Specifications

ComPair consists of a Windows based fault finding program and an interface box between PC and the (defective) product. The ComPair II interface box is connected to the PC via an USB cable. For the TV chassis, the ComPair interface box and the TV communicate via a bi-directional cable via the service connector(s). The ComPair fault finding program is able to determine the problem of the defective television, by a combination of automatic diagnostics and an interactive question/answer procedure.

How to Connect

This is described in the chassis fault finding database in ComPair.

Figure 5-10 ComPair II interface connection

Caution: It is compulsory to connect the TV to the PC as

shown in the picture above (with the ComPair interface in between), as the ComPair interface acts as a level shifter. If one connects the TV directly to the PC (via UART), ICs can be blown!

How to Order

ComPair II order codes:

• ComPair II interface: 3122 785 91020.

• Software is available via the Philips Service web portal.

• ComPair UART interface cable for Q55x.x. (using 3.5 mm Mini Jack connector): 3138 188 75051.

Note: When you encounter problems, contact your local support desk.

2011-Sep-09

C or UART commands is necessary,

5.5 Error Codes

5.5.1 Introduction

The error code buffer contains all detected errors since the last time the buffer was erased. The buffer is written from left to right, new errors are logged at the left side, and all other errors shift one position to the right. When an error occurs, it is added to the list of errors, provided the list is not full. When an error occurs and the error buffer is full, then the new error is not added, and the error buffer stays intact (history is maintained). To prevent that an occasional error stays in the list forever, the error is removed from the list after more than 50 hrs. of operation. When multiple errors occur (errors occurred within a short time span), there is a high probability that there is some relation between them.

New in this chassis is the way errors can be displayed:

• If no errors are there, the LED should not blink at all in

CSM or SDM. No spacer must be displayed as well.

• There is a simple blinking LED procedure for board

level repair (home repair) so called LAYER 1 errors

next to the existing errors which are LAYER 2 errors (see

Table 5-2

– LAYER 1 errors are one digit errors. – LAYER 2 errors are 2 digit errors.

• In protection mode. – From consumer mode: LAYER 1. – From SDM mode: LAYER 2.

• Fatal errors, if I2C bus is blocked and the set reboots, CSM and SAM are not selectable. – From consumer mode: LAYER 1. – From SDM mode: LAYER 2.

• In CSM mode. – When entering CSM: error LAYER 1 will be displayed

• In SDM mode. – When SDM is entered via Remote Control code or the

• Error display on screen. – In CSM no error codes are displayed on screen. – In SAM the complete error list is shown.

Basically there are three kinds of errors:

• Errors detected by the Stand-by software which lead to protection. These errors will always lead to protection and an automatic start of the blinking LED LAYER 1 error. (see section “5.6

• Errors detected by the Stand-by software which not lead to protection. In this case the front LED should blink the involved error. See also section “5.5

Error Buffer”. Note that it can take up several minutes

before the TV starts blinking the error (e.g. LAYER 1 error = 2, LAYER 2 error = 15 or 53).

• Errors detected by main software (MIPS). In this case the error will be logged into the error buffer and can be read out via ComPair, via blinking LED method LAYER 1-2 error, or in case picture is visible, via SAM.

5.5.2 How to Read the Error Buffer

Use one of the following methods:

• On screen via the SAM (only when a picture is visible). E.g.: – 00 00 00 00 00: No errors detected – 23 00 00 00 00: Error code 23 is the last and only

– 37 23 00 00 00: Error code 23 was first detected and

– Note that no protection errors can be logged in the

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by blinking LED. Only the latest error is shown.

hardware pins, LAYER 2 is displayed via blinking LED.

detected error.

error code 37 is the last detected error.

error buffer.

The Blinking LED Procedure”).

Error Codes, 5.5.4

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Service Modes, Error Codes, and Fault Finding

EN 33Q551.2E LA 5.

• Via the blinking LED procedure. See section 5.5.3 How to

Clear the Error Buffer.

•Via ComPair.

5.5.3 How to Clear the Error Buffer

Use one of the following methods:

• By activation of the “RESET ERROR BUFFER” command in the SAM menu.

• If the content of the error buffer has not changed for 50+ hours, it resets automatically.

5.5.4 Error Buffer

In case of non-intermittent faults, clear the error buffer before starting to repair (before clearing the buffer, write down the

Table 5-2 Error code overview

Description Layer 1 L ayer 2

C3 2 13 MIPS E BL / EB SSB SSB

C2 2 14 MIPS E BL / EB SSB SSB

I PNX doesn’t boot (HW cause) 2 15 Stby µP P BL PNX8550 SSB 12V 3 16 Stby µP P BL / Supply Inverter or display supply 3 17 MIPS E EB / Supply

C4 2 18 MIPS E BL / EB SSB SSB

I HDMI mux 2 23 MIPS E EB Sil9x87 SSB I2C switch 2 24 MIPS E EB PCA9540 SSB Channel dec DVB-T2 2 27 MIPS E EB CXD2820 SSB Channel dec DVB-S 2 28 MIPS E EB STV0903 SSB Lnb controller 2 31 MIPS E EB LNBH23 SSB FPGA 21/9 Scaler 9 33 MIPS E EB / Backend board Tuner 2 34 MIPS E EB TH 26x3 SSB Main nvm 2 35 MIPS E EB STM24C64 SSB Tuner DVB-S 2 36 MIPS E EB STV6110 SSB I2C switch 9 37 MIPS E EB PCA9540 Backend board FPGA Dimming 9 38 MIPS E EB / Backend board T° sensor SSB/set 2 42 MIPS E EB LM 75 T° sensor T° sensor LED driver/Tcon 7 42 MIPS E EB LM 75 T° sensor FRC-V 9 44 MIPS E EB / Backend board FPGA PQ 9 45 MIPS E EB 6SLX25 Backend board FPGA C-balancer 5 47 MIPS E EB FPGA/ Backend board PNX doesn’t boot (SW cause) 2 53 Stby µP P BL PNX8550 SSB TCON Display 7/9 54 MIPS E EB / Display FPGA HDR 5 61 MIPS E EB / Display FPGA lattice backlight 5 62 MIPS E EB / Display Display 5 64 MIPS E EB / Display

Monitored by

content, as this history can give significant information). This to ensure that old error codes are no longer present. If possible, check the entire contents of the error buffer. In some situations, an error code is only the result of another error code and not the actual cause (e.g. a fault in the protection detection circuitry can also lead to a protection). There are several mechanisms of error detection:

• Via error bits in the status registers of ICs.

• Via polling on I/O pins going to the stand-by processor.

• Via sensing of analog values on the stand-by processor or the PNX8550.

• Via a “not acknowledge” of an I

Take notice that some errors need several minutes before they start blinking or before they will be logged. So in case of problems wait 2 minutes from start-up onwards, and then check if the front LED is blinking or if an error is logged.

Error/

Error Buffer/

Prot

Blinking LED Device Defective Board

C communication.

Extra Info

• Rebooting. When a TV is constantly rebooting due to internal problems, most of the time no errors will be logged or blinked. This rebooting can be recognized via a ComPair interface and Hyperterminal (for Hyperterminal settings, see section “5.8

Fault Finding and Repair Tips, 5.8.6 Logging). It’s shown that the loggings which are generated

by the main software keep continuing. In this case diagnose has to be done via ComPair.

• Error 13 (I

C bus 3, SSB bus blocked). Current situation: when this error occurs, the TV will constantly reboot due to the blocked bus. The best way for further diagnosis here, is to use ComPair.

• Error 14 (I

C bus 2, TV set bus blocked). Current situation: when this error occurs, the TV will constantly reboot due to the blocked bus. The best way for further diagnosis here, is to use ComPair.

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• Error 18 (I

C bus 4, Tuner bus blocked). In case this bus is blocked, short the “SDM” solder paths on the SSB during startup, LAYER error 2 = 18 will be blinked.

• Error 15 (PNX8550 doesn’t boot). Indicates that the main processor was not able to read his bootscript. This error will point to a hardware problem around the PNX8550 (supplies not OK, PNX 8550 completely dead, I between PNX and Stand-by Processor broken, etc...). When error 15 occurs it is also possible that I blocked (NVM). I

C1 can be indicated in the schematics as

C link

C1 bus is

follows: SCL-UP-MIPS, SDA-UP-MIPS. Other root causes for this error can be due to hardware problems regarding the DDR’s and the bootscript reading from the PNX8550.

• Error 16 (12V). This voltage is made in the power supply and results in protection (LAYER 1 error = 3) in case of absence. When SDM is activated we see blinking LED LAYER 2 error = 16.

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EN 34 Q551.2E LA5.

Service Modes, Error Codes, and Fault Finding

• Error 17 (Invertor or Display Supply). Here the status of the “Power OK” is checked by software, no protection will occur during failure of the invertor or display supply (no picture), only error logging. LED blinking of LAYER 1 error = 3 in CSM, in SDM this gives LAYER 2 error = 17.

• Error 23 (HDMI). When there is no I

C communication towards the HDMI mux after start-up, LAYER 2 error = 23 will be logged and displayed via the blinking LED procedure if SDM is switched on.

• Error 24 (I2C switch). When there is no I communication towards the I

C switch, LAYER 2 error = 24 will be logged and displayed via the blinking LED procedure when SDM is switched on. Remark: this only works for TV sets with an I

C controlled screen included.

• Error 28 (Channel dec DVB-S). When there is no I communication towards the DVB-S channel decoder, LAYER 2 error = 28 will be logged and displayed via the blinking LED procedure if SDM is switched on.

• Error 31 (Lnb controller). When there is no I communication towards this device, LAYER 2 error = 31 will be logged and displayed via the blinking LED procedure if SDM is activated.

• Error 34 (Tuner). When there is no I

C communication towards the tuner during start-up, LAYER 2 error = 34 will be logged and displayed via the blinking LED procedure when SDM is switched on.

• Error 35 (main NVM). When there is no I communication towards the main NVM during start-up, LAYER 2 error = 35 will be displayed via the blinking LED procedure when SDM is switched “on”. All service modes (CSM, SAM and SDM) are accessible during this failure, observed in the Uart logging as follows: "<< ERRO >>> PFPOW_.C: First Error (id19, Layer_1= 2 Layer_= 35)".

• Error 36 (Tuner DVB-S). When there is no I communication towards the DVB-S tuner during start-up, LAYER 2 error = 36 will be logged and displayed via the blinking LED procedure when SDM is switched “on”.

• Error 42 (Temp sensor). Only applicable for TV sets equipped with temperature devices.

• Error 53. This error will indicate that the PNX8550 has read his bootscript (when this would have failed, error 15 would blink) but initialization was never completed because of hardware problems (NAND flash, ...) or software initialization problems. Possible cause could be that there is no valid software loaded (try to upgrade to the latest main software version). Note that it can take a few minutes before the TV starts blinking LAYER 1 error = 2 or in SDM, LAYER 2 error = 53.

• Error 64. Only applicable for TV sets with an I screen.

5.6 The Blinking LED Procedure

5.6.1 Introduction

The blinking LED procedure can be split up into two situations:

• Blinking LED procedure LAYER 1 error. In this case the error is automatically blinked when the TV is put in CSM. This will be only one digit error, namely the one that is referring to the defective board (see table “5-2

overview”) which causes the failure of the TV. This

approach will especially be used for home repair and call centres. The aim here is to have service diagnosis from a distance.

• Blinking LED procedure LAYER 2 error. Via this procedure, the contents of the error buffer can be made visible via the front LED. In this case the error contains 2 digits (see table “5-2 displayed when SDM (hardware pins) is activated. This is especially useful for fault finding and gives more details regarding the root cause of the defective board.

Important remark:

For an empty error buffer, the LED should not blink at all in CSM or SDM. No spacer will be displayed.

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Error code overview”) and will be

C controlled

Error code

When one of the blinking LED procedures is activated, the front LED will show (blink) the contents of the error buffer. Error codes greater then 10 are shown as follows:

1. “n” long blinks (where “n” = 1 to 9) indicating decimal digit

2. A pause of 1.5 s

3. “n” short blinks (where “n”= 1 to 9)

4. A pause of approximately 3 s,

5. When all the error codes are displayed, the sequence finishes with a LED blink of 3 s (spacer).

6. The sequence starts again.

Example: Error 12 8 6 0 0. After activation of the SDM, the front LED will show:

1. One long blink of 750 ms (which is an indication of the decimal digit) followed by a pause of 1.5 s

2. Two short blinks of 250 ms followed by a pause of 3 s

3. Eight short blinks followed by a pause of 3 s

4. Six short blinks followed by a pause of 3 s

5. One long blink of 3 s to finish the sequence (spacer).

6. The sequence starts again.

5.6.2 How to Activate

Use one of the following methods:

• Activate the CSM. The blinking front LED will show only the latest layer 1 error, this works in “normal operation” mode or automatically when the error/protection is monitored by the Stand-by processor. In case no picture is shown and there is no LED blinking, read the logging to detect whether “error devices” are mentioned. (see section “5.8

Fault Finding and Repair

Tips, 5.8.6 Logging”).

• Activate the SDM. The blinking front LED will show the entire content of the LAYER 2 error buffer, this works in “normal operation” mode or when SDM (via hardware pins) is activated when the tv set is in protection.

5.7 Protections

5.7.1 Software Protections

Most of the protections and errors use either the stand-by microprocessor or the MIPS controller as detection device. Since in these cases, checking of observers, polling of ADCs, and filtering of input values are all heavily software based, these protections are referred to as software protections. There are several types of software related protections, solving a variety of fault conditions:

• Related to supplies: presence of the +5V, +3V3 and 1V2 needs to be measured, no protection triggered here.

• Protections related to breakdown of the safety check mechanism. E.g. since the protection detections are done by means of software, failing of the software will have to initiate a protection mode since safety cannot be guaranteed any more.

Remark on the Supply Errors

The detection of a supply dip or supply loss during the normal playing of the set does not lead to a protection, but to a cold reboot of the set. If the supply is still missing after the reboot, the TV will go to protection.

Protections during Start-up

During TV start-up, some voltages and IC observers are actively monitored to be able to optimise the start-up speed, and to assure good operation of all components. If these monitors do not respond in a defined way, this indicates a malfunction of the system and leads to a protection. As the

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observers are only used during start-up, they are described in the start-up flow in detail (see section “5.3

Stepwise Start-up”).

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5.7.2 Hardware Protections

The only real hardware protection in this chassis appears in case of an audio problem e.g. DC voltage on the speakers. This protection will only affect the Class D audio amplifier (item 7D10; see diagram B03A) and puts the amplifier in a continuous burst mode (cyclus approximately 2 seconds).

Repair Tip

• There still will be a picture available but no sound. While the Class D amplifier tries to start-up again, the cone of the loudspeakers will move slowly in one or the other direction until the initial failure shuts the amplifier down, this cyclus starts over and over again. The headphone amplifier will also behaves similar.

5.8 Fault Finding and Repair Tips

Read also section “5.5 Error Codes, 5.5.4 Error Buffer, Extra

Info”.

5.8.1 Ambilight

Due to degeneration process of the LED’s fitted on the ambi module, there can be a difference in the colour and/or light output of the spare ambilight modules in comparison with the originals ones contained in the TV set. Via SAM => alignments => ambilight, the spare module can be adjusted.

5.8.2 Audio Amplifier

The Class D-IC 7D10 has a powerpad for cooling. When the IC is replaced it must be ensured that the powerpad is very well pushed to the PWB while the solder is still liquid. This is needed to insure that the cooling is guaranteed, otherwise the Class DIC could break down in short time.

SSB diversities the stabilizer is 7UD2 while for the other diversities 7UC0 is used.

• +3V3 supply voltage (3V3 nominal) for 5000 series SSB diversities, provided by 7UD3; in this case the 12V to 3V3 DC-DC converter is not present.

• +5V-TUN supply voltage (5V nominal) for tuner and IF amplifier.

+3V3-STANDY (3V3 nominal) is the permanent voltage, supplying the Stand-by microprocessor inside PNX855xx.

Supply voltage +1V1 is started immediately when +12V voltage becomes available (+12V is enabled by STANDBY signal when "low"). Supply voltages +3V3, +2V5, +1V8, +1V2 and +5V-TUN are switched "on" by signal ENABLE-3V3 when "low", provided that +12V (detected via 7U40 and 7U41) is present.

+12V is considered OK (=> DETECT2 signal becomes "high", +12V to +1V8, +12V to +3V3, +12V to +5V DC-DC converter can be started up) if it rises above 10V and doesn’t drop below 9V5. A small delay of a few milliseconds is introduced between the start-up of 12V to +1V8 DC-DC converter and the two other DC-DC converters via 7U48 and associated components.

Description DVB-S2:

• LNB-RF1 (0V = disabled, 14V or 18V in normal operation) LNB supply generated via the second conversion channel of 7T03 followed by 7T50 LNB supply control IC. It provides supply voltage that feeds the outdoor satellite reception equipment.

• +3V3-DVBS (3V3 nominal), +2V5-DVBS (2V5 nominal) and +1V-DVBS (1.03V nominal) power supply for the silicon tuner and channel decoder. +1V-DVBS is generated via a 5V to 1V DC-DC converter and is stabilized at the point of load (channel decoder) by means of feedback signal SENSE+1V0-DVBS. +3V3-DVBS and +2V5-DVBS are generated via linear stabilizers from +5V-DVBS that by itself is generated via the first conversion channel of 7T03.

5.8.3 CSM

When CSM is activated and there is a USB stick connected to the TV, the software will dump the complete CSM content to the USB stick. The file (Csm.txt) will be saved in the root of the USB stick. If this mechanism works it can be concluded that a large part of the operating system is already working (MIPS, USB...)

5.8.4 DC/DC Converter

Description basic board

The basic board power supply consists of 4 DC/DC converters and 5 linear stabilizers. All DC/DC converters have +12V input voltage and deliver:

• +1V1 supply voltage (1.15V nominal), for the core voltage of PNX855xx, stabilized close to the point of load; SENSE+1V1 signal provides the DC-DC converter the needed feedback to achieve this.

• +1V8 supply voltage, for the DDR memories and DDR interface of PNX855xx.

• +3V3 supply voltage (3.30V nominal), overall 3.3 V for onboard IC’s, for non-5000 series SSB diversities only.

• +5V (5.15V nominal) for USB, WIFI and Conditional Access Module and +5V5-TUN for +5V-TUN tuner stabilizer.

The linear stabilizers are providing:

• +1V2 supply voltage (1.2V nominal), stabilized close to PNX855xx device, for various other internal blocks of PNX855xx; SENSE+1V2 signal provides the needed feedback to achieve this.

• +2V5 supply voltage (2.5V nominal) for LVDS interface and various other internal blocks of PNX855xx; for 5000 series

At start-up, +24V becomes available when STANDBY signal is "low" (together with +12V for the basic board), when +3V3 from the basic board is present the two DC-DC converters channels inside 7T03 are activated. Initially only the 24V to 5V converter (channel 1 of 7T03 generating +5V-DVBS) will effectively work, while +V-LNB is held at a level around 11V7 via diode 6T55.

03 is initialized, the second channel of 7T03 will start

After 7T and generates a voltage higher then LNB-RF1 with 0V8. +5VDVBS start-up will imply +3V3-DVBS start-up, with a small delay of a few milliseconds => +2V5-DVBS and +1V-DVBS will be enabled.

If +24V drops below +15V level then the DVB-S2 supply will stop, even if +3V3 is still present.

Debugging

The best way to find a failure in the DC/DC converters is to check their start-up sequence at power “on” via the mains cord, presuming that the stand-by microprocessor and the external supply are operational. Take STANDBY signal "high"-to-"low" transition as time reference. When +12V becomes available (maximum 1 second after STANDBY signal goes "low") then +1V1 is started immediately. After ENABLE-3V3 goes "low", all the other supply voltages should rise within a few milliseconds.

Tips

• Behaviour comparison with a reference TV550 platform can be a fast way to locate failures.

• If +12V stays "low", check the integrity of fuse 1U40.

• Check the integrity (at least no short circuit between drain and source) of the power MOS-FETs before starting up the platform in “SDM”, otherwise many components might be damaged. Using a ohmmeter can detect short circuits

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Service Modes, Error Codes, and Fault Finding

between any power rail and ground or between +12V and any other power rail.

• Short circuit at the output of an integrated linear stabilizer (7UC0, 7UD2 or 7UD3) will heat up this device strongly.

• Switching frequencies should be 500 kHz ...600 kHz for 12 V to 1.1 V and 12 V to 1.8 V DC-DC converters, 900 kHz for 12 V to 3.3 V and 12 V to 5 V DC-DC converters. The DVB-S2 supply 24 V to 5 V and 24 V to +V LNB DC-DC converters operates at 300 kHz while for 5 V to 1.1 V DC-DC converter 900 kHz is used.

5.8.5 Exit “Factory Mode”

When an “F” is displayed in the screen’s right corner, this means the set is in “Factory” mode, and it normally happens after a new SSB is mounted. To exit this mode, push the “VOLUME minus” button on the TV’s local keyboard for 10 seconds (this disables the continuous mode). Then push the “SOURCE” button for 10 seconds until the “F” disappears from the screen.

5.8.6 Logging

When something is wrong with the TV set (f.i. the set is rebooting) you can check for more information via the logging in Hyperterminal. The Hyperterminal is available in every Windows application via Programs, Accessories, Communications, Hyperterminal. Connect a “ComPair UART”cable (3138 188 75051) from the service connector in the TV to the “multi function” jack at the front of ComPair II box. Required settings in ComPair before starting to log:

- Start up the ComPair application.

- Select the correct database (open file “Q55X.X”, this will set

the ComPair interface in the appropriate mode).

- Close ComPair

After start-up of the Hyperterminal, fill in a name (f.i. “logging”) in the “Connection Description” box, then apply the following settings:

1. COMx

2. Bits per second = 115200

3. Data bits = 8

4. Parity = none

5. Stop bits = 1

6. Flow control = none

During the start-up of the TV set, the logging will be displayed. This is also the case during rebooting of the TV set (the same logging appears time after time). Also available in the logging is the “Display Option Code” (useful when there is no picture), look for item “DisplayRawNumber” in the beginning of the logging. Tip: when there is no picture available during rebooting you are able to check for “error devices” in the logging (LAYER 2 error) which can be very helpful to determine the failure cause of the reboot. For protection state, there is no logging.

5.8.7 Guidelines Uart logging

Description possible cases:

Uart loggings are displayed:

• When Uart loggings are coming out, the first conclusion we can make is that the TV set is starting up and communication with the flash RAM seems to be supported. The PNX855xx is able to read and write in the DRAMs.

• We can not yet conclude : Flash RAM and DRAMs are fully operational/reliable.There still can be errors in the data transfers, DRAM erros, read/write speed and timing control.

No Uart logging at all:

• In case there is no Uart logging coming out, check if the startup script can be send over the I

C bus (3 trials to

startup) + power supplies are switched on and stable.

• No startup will end up in a blinking LED status : error LAYER 1 = “2”, error LAYER 2 = “53” (startup with SDM solder paths short).

• Error LAYER 2 = “15” (hardware cause) is more related to a supply issue while error LAYER 2 = “53” (software cause) refers more to boot issues.

Uart loggings reporting fault conditions, error messages, error codes, fatal errors:

• Some failures are indicated by error codes in the logging, check with error codes table (see Table “5-2

Error code overview”).e.g. => <<<ERROR>>>PLFPOW_MERR.C :

First Error (id=10,Layer_1=2,Layer_2=23).

C bus error mentioned as e.g.: “ I2C bus 4 blocked”.

• I

• Not all failures or error messages should be interpreted as fault.For instance root cause can be due to wrong option codes settings => e.g. “DVBS2Suppoprted : False/True.

In the Uart log startup script we can observe and check the enabled loaded option codes.

Defective sectors (bad blocks) in the Nand Flash can also be reported in the logging.

Startup in the SW upgrade application and observe the Uart logging:

Starting up the TV set in the Manual Software Upgrade mode will show access to USB, meant to copy software content from USB to the DRAM.Progress is shown in the logging as follows: “cosupgstdcmds_mcmdwritepart: Programming 102400 bytes, 40505344 of 40607744 bytes programmed”.

Startup in Jett Mode:

Check Uart logging in Jet mode mentioned as : “JETT UART READY”.

Uart logging changing preset:

=> COMMAND: calling DFB source = RC6, system=0, key = 4”.

5.8.8 Loudspeakers

Make sure that the volume is set to minimum during disconnecting the speakers in the ON-state of the TV. The audio amplifier can be damaged by disconnecting the speakers during ON-state of the set!

5.8.9 Power Supply

In case of no picture when CSM (test pattern) is activated and backlight doesn’t light up, it’s recommended first to check the inverter on the PSL + wiring (LAYER 2 error = 17 is displayed in SDM).

5.8.10 Display option code

Attention: In case the SSB is replaced, always check the display option code number (group 2, first number e.g. “44855”) in SAM, even when picture is available. Performance with the incorrect display option code can lead to unwanted side-effects for certain conditions.

Also supported in this chassis:

While in the download application (start up in TV mode + “OK” button pressed), the display option code can be changed via 062598 HOME XXX special SAM command (XXX=display option in 3 digits).

5.8.11 Additional information for replacing the ceramic heatsink application on the PNX85500

When replacing the PNX85500, ensure that the ceramic heatsink is replaced as follows:

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• Clean the PNX85500 top side with dust-free and “Isopropanol” or similar cleaning agent.

• Remove liner from double sided tape (inner pad and outer ring).

• Position heatsink on the IC by means of a jig. Tolerances +/- 1 mm in all directions; angle +/- 2 degrees. Orientation and location according to figure 5-11 Dimensions measured from the centre of the heatsink.

• Press the heatsink with a pressure of 4kg during a minimal duration of 5 seconds. Sufficient board support should be present during mounting and pressing.

- Apply force gradually

- Use full heatsink area to apply force.

- Equipment should fulfil strain gage measurement requirements.

• Mount spring and press pushpins through the board. Double check correct mounting of pushpins (touch-up, package operator).

Attention points:

• A removed or touched heatsink should be replaced by a new heatsink or by a cleaned one with new thermal pad. The top side of the IC needs to be cleaned and free of any old glue residues before replacing the heatsink.

• Handling boards by means of the heatsink is never allowed and should be avoided during the entire process.

Heatsink application.

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119.850 mm

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Figure 5-11 Heatsink application

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Blue arrows: traces of friction

Red arrows: damaged components

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Significant risk of damaging the board by the fixation point

SSB fixation points

EN 39Q551.2E LA 5.

5.8.12 SSB Replacement

Follow the instructions in the flowchart in case a SSB has to be exchanged. See table 5-3

Step # Action to do Advise / Attention points / Remarks

1 Ensure ESD protection by using a wristband 2 If SSB is still functional: Go via SAM to “upload to USB” and copy Personal

settings - Option codes - Alignments (Presets) - Set Identification. Advice: because of differences in memor y allocation, it is adv ised to up grade main SW before copying data from existing SSB. Copy of Preset list is

possible from normal user interface. 3 Disconnect set from mains and from antenna. Safety and ESD! 4 Open the set and disconnect LVDS flat cable. Disconnect other cables /

connections. 5 Dismount the (defective) SSB from the set. Do not damage SSB copper tracks with your tools! Do not scratch bottom of SSB (be very ca refu l

6 Place new SSB in the set, and fixate/mount carefully. Do not damage SSB copper tracks with your tools! Do no t scratch bottom o f SSB (be ve ry car eful

7 Connect PSU and other connectors. Insert the optional WiFi module. Make sure that the connectors are correctly plugged-in and locked (click). Special attention for the

8 Connect LVDS connector(s). Be very careful: wrong or bad connection can damage the TCON part on the SSB and damage

9 Connect set to mains and switch TV “On”. Check start-up of the set, backlight switch “On”… 10 If the set does not start (or reboots) check:

- The connectors from the power supply,

- The power supply cable and connection pins,

- LVDS cable connection.

11 Before programming the new SSB, upgrade to latest software. If set is starting

up in software upgrade mode, then first install new software via software

Upgrade Menu or via the autorun.upg file. 12 If set is starting up without picture or menu (OSD), first program the correct

Display Option codes. 13 Go to SAM and program “Set type” and “Serial number”. This is possible via

the NVM editor and virtual keyboard. In case personal settings were

recovered from the defective SSB, you can use an “Upload from USB”. 14 Check if option codes are correct, and keys are present. SSB s with integrated

TCON needs TCON alignment in SAM. 15 Update to latest software (Standby and main software). This ste p is necessary

to make sure that the (optional) 200Hz T-CON board has the latest software.

16 Once the set is playing, check cable connection between PSU and SSB, by

moving the cable if there are no bad connections. 17 Fill in the Electronic DDF (Defect Description Form): Fault symptom, TV type

and TV serial number. 18 Install presets or check if all presets are OK. Check in CSM if Type number,

Serial number, Main and Standby software are correct. 19 Check connectivity to Net TV and DLNA. Check AmbiLight functionality. Only for sets having these functionalities. 20 Inform customer about Memory Card, USB, or Hard drive PVR (Personal

Video Recording) recordings.

SSB replacement instructions.

For a more general overview of steps to follow, refer to figure

SSB replacement flowchart.

5-14

Table 5-3 SSB replacement instructions

Upload to USB: A directory “repair” will be created on the USB, and all data will be copied in this directory. On sets with software before Q552-xx-140-x-x, there was an issue by copying the program map table, so it is advised to reinstall the programs from Virgin mode ins tead of using copy via USB.

Always take care for ESD! Be extra careful when removing connectors!

by moving SSB over SSB supports). See Figure 5-12 and Figure 5-13.

optional WiFi module: a defective WiFi modu le can gi ve rebo ots or no star t-up of the SSB. I n this case do a trial without WiFi module.

the LCD display. Check if flat cables are fitted correctly before closing the connector lock.

Power supply connector must “snap” into the socket.

Some SSB’s will start-up in software upgrade mode, and software needs to be installed before you can program the Display Option codes. It’s adviced to use an autorun.upg file for software upgrade, this in case you have no OSD on the screen.

Use blind service mode “062598” + “Home” button, directly followed by the Display Option code (3 digits). Set will switch to Standby after Display Option code is entered.

Programming “Set type” and “Serial number” is mandatory to have all functionality of the set, like DLNA, Net TV… For certain sets you may need to use ComPair for this.

Validity of HDCP, CI+, Marlin, and WDRM keys can be checked via ComPair.

Even when the SSB already has the latest so ftware, it is man datory to upgrad e again the softw are to update the 200 Hz T-CON part. At the end of the main software update process, a dedicated software is loaded, from the main processor via the LVDS connection, to upgrade the 200 Hz T-CON part. For certain LCD displays, a dedicated Display software patch (autoscript) is available. See General Service info GSC_85590.

Check the two power connectors 1M95 and 1M99. Bad contact or bad connection here can give reboots.

It is mandatory to fill in the E-DDF form (see the “At Your Service” web portal).

Special attention for Standby softw are: check if Stand by software ID i s matching with th e D-RAM’s mounted on the SSB (2 × Elpida = 73, 4 × Elpida = 64, 2 × Hynix = 72, 4 × Hynix = 63).

Inform customer that previous recordings mad e on Memory Card (movie do wnload), USB, or Har d drive will be lost. USB or Hard driv e needs to be re-fo rmatted and match ed with new SSB ( WDRM Keys!).

Figure 5-12 Mounting attention points [1/2] Figure 5-13 Mounting attention points [2/2]

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START

C onnect the U SB stick to the set,

go to SAM and save the current TV settings via “Upload to USB”

Set is still operati n g?

Yes

Dismount the defective SSB.

2. Replace the SSB by a Service SSB.

Set behaviour?

Yes

Instruction note SSB replacem en t Q55x.x

Before starting:

- prepare a USB memory stick with the latest software

- download the latest Main Software (Fus) from www.p4c.philips.com

- unzip this file

- create a folder ”upgrades” in the root of a USB stick (size > 50 MB) and save the autorun.upg file in this "upgrades" folder. Note: it is possible to rename this file, e.g."Q54x_SW_version.upg"; this in case there are more than one "autorun.upg" files on the USB stick.

No picture displayed

Picture displayed

Set is starting up without software upgrade menu appearing on screen

Picture displayed

Set is starting up with software upgrade menu appearing on screen

Due to a possible wrong display option code in the received Service SSB (NVM), it’s possible that no picture is displayed. Due to this

the download application will not be shown either. This tree enables you to load the main software step-by-step via the UART logging on the PC (this for visual feedback).

Start-up the set

1) Start up the TV set, equiped with the Service SSB, and enable the U

ART logging on the PC.

2) The TV set will start-up automatically in the

download application if main TV software is not loaded.

3) Plug the prepared USB stick into the TV set. Follow the

instructions in the UART log file, press “Right” cursor key to enter

the list. Navigate to the “autorun.upg” file in the UART logging

printout via the cursor keys on the remote control. When the

correct file is selected, press “Ok”.

4) Press "Do

wn" cursor and “Ok” to start flashing the main TV software. Printouts like: “L: 1-100%, V: 1-100% and P: 1-100%” should be visible now in the UART logging.

5) Wait until the message “Operation successful !” is logged in

the UART log and remove all inserted media. Restart the TV set.

1) Plug the USB stick into the TV set and select the “autorun .upg” file in the display

ed browser.

2) Now the main software will be loaded automatically,

supported by a progress bar.

3) Wait until the message “Operation successful !” is displayed and remove all inserted media. Restart the TV set.

Set the correct “Display code” via “062598 -HOME- xxx” where

“xxx” is the 3 digit display panel code (see stic

ker on the side

or bottom of the cabinet)

After entering the “Display Option” code, the set is going to

Standby

(= validation of code)

Restart the set

Connect PC via the ComPair interface to Service connector.

Start TV in Jett mode (DVD I + (OSD))

Open ComPair browser Q54x

Program set type number, serial number, and display 12 NC

Prog

ram E - DFU if needed.

Go to SAM and reload settings

via “Download from USB” function.

In case of settings reloaded from USB, the set type, serial number, display 12 NC, are automatically stored when entering display options.

- Check if correct “display option” code is programmed.

- Verify “option codes” according to sticker inside the set.

- Default settings f

or “white drive” > see Service Manual.

Q55x.E SSB Board swap – ER on behalf of VDS Updated 28-07-2011

If not already done:

Check latest software on Service website.

Update main and Stand-by software via USB.

Check and perform alignments in SAM according to the

Service Manual. Option codes, colour temperature, etc.

Final chec

k of all menus in CSM.

Special attention for HDMI Keys and Mac address.

Check if E - D F U is present.

End

Attention point for Net TV: If the set type and serial number are not filled in, the Net TV functionality will not work. It will not be possible to connect to the internet.

Saved settings

on USB stick?

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Figure 5-14 SSB replacement flowchart

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Restart the set

Set is starting up in Factory m ode

Set is starting up in Factor y mod e?

Noisy picture with bands/lines is visible and the

RED LED is continuous on.

An “F” is displayed (and the HDMI 1

input is displayed).

- Press the “volume minus” button on the TVs local keyboard for 5 ~10 seconds

- Press the “SOURCE” button for 10 seconds until the “F” disappears

from the screen or the noise on the screen is replaced by “blue mute”

The noise on the screen is replaced

with the blue mute or the “F” is disappeared!

Unplug the mains cord to verify the correct

disabling of the Factory mode.

Program display option code

via “062598 MENU”, followed by

the 3 digits code of the display

(this code can be found

on a sticker on - or inside - the set).

After entering “display option” code, the set is

going in stand-by mode (= validation of code)

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Figure 5-15 SSB replacement flowchart - Factory mode

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5.9 Software Upgrading

Attention!

Software version numbers for 2011 sets are all defined below number 0.40.x.x. This might confuse servicers who store software versions for more than one set and/or platform on the same storage device (USB stick).

Always check the latest software version on the servicer website in relation to the correct CTN!!!

5.9.1 Introduction

The set software and security keys are stored in a NANDFlash, which is connected to the PNX855xx.

It is possible for the user to upgrade the main software via the USB port. This allows replacement of a software image in a stand alone set, without the need of an E-JTAG debugger. A description on how to upgrade the main software can be found in the electronic User Manual.

Important: When the NAND-Flash must be replaced, a new SSB must be ordered, due to the presence of the security keys! (CI +, MAC address, ...). Perform the following actions after SSB replacement:

1. Set the correct option codes (see sticker inside the TV).

2. Update the TV software => see the eUM (electronic User Manual) for instructions.

3. Perform the alignments as described in chapter 6 (section

Reset of Repaired SSB).

6.5

4. Check in CSM if the CI + key, MAC address.. are valid.

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Figure 5-16 SSB start-up

5.9.2 Main Software Upgrade

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For the correct order number of a new SSB, always refer to the Spare Parts list!

• The “UpgradeAll.upg” file is only used in the factory.

Automatic Software Upgrade

In “normal” conditions, so when there is no major problem with the TV, the main software and the default software upgrade application can be upgraded with the “AUTORUN.UPG” (FUS part of the one-zip file: e.g. 3104 337 05661 _FUS _Q555X_ x.x.x.x_prod.zip). This can also be done by the consumers themselves, but they will have to get their software from the commercial Philips website or via the Software Update Assistant in the user menu (see eUM). The “autorun.upg” file must be placed in the root of the USB stick. How to upgrade:

1. Copy “AUTORUN.UPG” to the root of the USB stick.

2. Insert USB stick in the set while the set is operational. The set will restart and the upgrading will start automatically. As soon as the programming is finished, a message is shown to remove the USB stick and restart the set.

Manual Software Upgrade

In case that the software upgrade application does not start automatically, it can also be started manually. How to start the software upgrade application manually:

1. Disconnect the TV from the Mains/AC Power.

2. Press the “OK” button on a Philips TV remote control or a Philips DVD RC-6 remote control (it is also possible to use

Page 43

Service Modes, Error Codes, and Fault Finding

a TV remote in “DVD” mode). Keep the “OK” button pressed while reconnecting the TV to the Mains/AC Power.

3. The software upgrade application will start.

Attention!

In case the download application has been started manually, the “autorun.upg” will maybe not be recognized. What to do in this case:

1. Create a directory “UPGRADES” on the USB stick.

2. Rename the “autorun.upg” to something else, e.g. to “software.upg”. Do not use long or complicated names, keep it simple. Make sure that “AUTORUN.UPG” is no longer present in the root of the USB stick.

3. Copy the renamed “upg” file into this directory.

4. Insert USB stick into the TV.

5. The renamed “upg” file will be visible and selectable in the upgrade application.

Back-up Software Upgrade Application

If the default software upgrade application does not start (could be due to a corrupted boot sector) via the above described method, try activating the “back-up software upgrade application”. How to start the “back-up software upgrade application” manually:

1. Disconnect the TV from the Mains/AC Power.

2. Press the “CURSOR DOWN”-button on a Philips TV remote control while reconnecting the TV to the Mains/AC Power.

3. The back-up software upgrade application will start.

http://www.p4c.philips.com (Software for servicers only)

• FPGA dimming software.

• FPGA 21/9 Scaler software (no software version

supported in CSM!).

• FRC-V software.

• FPGA HDR software.

• FPGA Lattice backlight software.

• FPGA C-balancer software.

• FPGA PQ software.

5.9.6 UART logging 2K10 (see section “5.8

Repair Tips, 5.8.6 Logging)

EN 43Q551.2E LA 5.

Fault Finding and

5.9.3 Stand-by Software Upgrade via USB

In this chassis it is possible to upgrade the Stand-by software via a USB stick. The method is similar to upgrading the main software via USB. Use the following steps:

1. Create a directory “UPGRADES” on the USB stick.

2. Copy the Stand-by software (part of the one-zip file, e.g. StandbyFactory_88.0.0.0.upg) into this directory.

3. Insert the USB stick into the TV.

4. Start the download application manually (see section “

Manual Software Upgrade”.

5. Select the appropriate file and press the “OK” button to upgrade.

5.9.4 Content and Usage of the One-Zip Software File

Below the content of the One-Zip file is explained, and instructions on how and when to use it.

• AmbiCpld_Q55XX_x.x.x.x_prod.zip. Contains the program instruction and software content, needed to upgrade the ambilight CPLD on the TV550 platform.

• BLCtrlFPGA_Q55X_x.x.x.x_prod.zip. (Only applicable for 32PFL9606X/XX). Contains the BLCtrlFPGA software (sw version nummer can not be retrieved from the set) in “upg” format.Attention : no mains interruption allowed during the upgrade process (upgrade not full proof).

• FUS_Q555X_x.x.x.x_prod.zip. Contains the “autorun.upg” which is needed to upgrade the TV main software and the software download application.

• StandbySW_Q555X_x.x.x.x_prod.zip. Contains the StandbyFactory software in “upg” format.

• ProcessNVM_Q55XX_x.x.x.x_prod.zip. Default NVM content. Must be programmed via ComPair or can be loaded via USB, be aware that all alignments stored in NVM are overwritten here.

5.9.5 FPGA software releases.

You can download all available FPGA software releases according latest updates from the Servicer Network support located on website:

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6. Alignments

Alignments

Index of this chapter:

General Alignment Conditions

6.1

6.2 Hardware Alignments

6.3 Software Alignments

6.4 Option Settings

6.5 Reset of Repaired SSB

6.6 Total Overview SAM modes

6.1 General Alignment Conditions

Perform all electrical adjustments under the following conditions:

• Power supply voltage (depends on region): – AP-NTSC: 120 VAC or 230 V – AP-PAL-multi: 120 - 230 V – EU: 230 V

/ 50 Hz (± 10%).

– LATAM-NTSC: 120 - 230 V – US: 120 V

/ 60 Hz (± 10%).

/ 50 Hz (± 10%).

• Connect the set to the mains via an isolation transformer with low internal resistance.

• Allow the set to warm up for approximately 15 minutes.

• Measure voltages and waveforms in relation to correct ground (e.g. measure audio signals in relation to AUDIO_GND). Caution: It is not allowed to use heat sinks as ground.

• Test probe: Ri > 10 MΩ, Ci < 20 pF.

• Use an isolated trimmer/screwdriver to perform alignments.

6.1.1 Alignment Sequence

• First, set the correct options: – In SAM, select “Option numbers”. – Fill in the option settings for “Group 1” and “Group 2”

according to the set sticker (see also paragraph 6.4

Option Settings).

– Press OK on the remote control before the cursor is

moved to the left.

– In submenu “Option numbers” select “Store” and press

OK on the RC.

•OR: – In main menu, select “Store” again and press OK on

the RC.

– Switch the set to Stand-by.

• Warming up (>15 minutes).

6.2 Hardware Alignments

Not applicable.

6.3 Software Alignments

Put the set in SAM mode (see Chapter 5. Service Modes, Error

Codes, and Fault Finding). The SAM menu will now appear on

the screen. Select ALIGNMENTS and go to one of the sub menus. The alignments are explained below. The following items can be aligned:

• White point

• Ambilight.

To store the data:

• Press OK on the RC before the cursor is moved to the

left

• In main menu select “Store” and press OK on the RC

• Switch the set to stand-by mode.

For the next alignments, supply the following test signals via a video generator to the RF input:

• EU/AP-PAL models: a PAL B/G TV-signal with a signal strength of at least 1 mV and a frequency of 475.25 MHz

• US/AP-NTSC models: an NTSC M/N TV-signal with a signal strength of at least 1 mV and a frequency of 61.25 MHz (channel 3).

• LATAM models: an NTSC M TV-signal with a signal strength of at least 1 mV and a frequency of 61.25 MHz (channel 3).

6.3.1 White Point

• Choose “TV menu”, “Setup”, “More TV Settings” and then “Picture” and set picture settings as follows:

Picture Setting

Contrast 100 Brightness 50 Colour 0 Light Sensor Off Picture format Unscaled

• In menu “Picture”, choose “Pixel Precise HD” and set picture settings as follows:

Picture Setting

Dynamic Contrast Off Dynamic Backlight Off Colour Enhancement Off Gamma 0

• Go to the SAM and select “Alignments”-> “White point”.

White point alignment LCD screens:

• Use a 100% white screen (format: 720p50) to the HDMI input and set the following values: – “Colour temperature”: “Cool”. – All “White point” values to: “127”.

In case you have a colour analyser:

• Measure, in a dark environment, with a calibrated contactless colour analyser (Minolta CA-210 or Minolta CS-200) in the centre of the screen and note the x, y value.

• Change the pattern to 90% white screen. If a Quantum Data generator is used, select the “GreyAll” test pattern at level = 230.

• Adjust the correct x, y coordinates (while holding one of the White point registers R, G or B on 127) by means of decreasing the value of one or two other white points to the correct x, y coordinates (see Table 6-1

White D alignment values - LED - Minolta CA-210, or 6-2 White D alignment values - LED - Minolta CS-200). Tolerance: dx: ± 0.002, dy:

± 0.002.

• Repeat this step for the other colour temperatures that need to be aligned.

• When finished press OK on the RC and then press STORE (in the SAM root menu) to store the aligned values to the NVM.

• Restore the initial picture settings after the alignments.

Table 6-1 White D alignment values - LED - Minolta CA-210

Value Cool (9800K) Normal (8250K) Warm (6190K)

x 0.280 0.291 0.318 y 0.293 0.308 0.341

Table 6-2 White D alignment values - LED - Minolta CS-200

Value Cool (11000K) Normal (9000K) Warm (6500K)

x 0.276 0.287 0.313 y 0.282 0.296 0.329

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Alignments

EN 45Q551.2E LA 6.

If you do not have a colour analyser, you can use the default

values. This is the next best solution. The default values are average values coming from production.

• Select a COLOUR TEMPERATURE (e.g. COOL, NORMAL, or WARM).

• Set the RED, GREEN and BLUE default values according to the values in Table 6-3

• When finished press OK on the RC, then press STORE (in the SAM root menu) to store the aligned values to the NVM.

• Restore the initial picture settings after the alignments.

Table 6-3 White tone default setting 32" (Oscar)

White Tone e.g. 32PFL9606x Colour Temp R G B

Normal 127 116 113 Cool 124. 115. 126 Warm 127 105 72

Table 6-4 White tone default setting 37" (Oscar)

White Tone e.g. 37PFL9606x Colour Temp R G B

Normal t.b.d. t.b.d. t.b.d. Cool t.b.d. t.b.d. t.b.d. Warm t.b.d. t.b.d. t.b.d.

Table 6-5 White tone default setting 46" (Oscar)

White Tone e.g. 46PFL9706x Colour Temp R G B

Normal t.b.d. t.b.d. t.b.d. Cool t.b.d. t.b.d. t.b.d. Warm t.b.d. t.b.d. t.b.d.

Table 6-10 White tone default setting 50" (Sundance)

White Tone e.g. 50PFL7956x Colour Temp R G B

Normal t.b.d. t.b.d. t.b.d. Cool t.b.d. t.b.d. t.b.d. Warm t.b.d. t.b.d. t.b.d.

6.3.2 Ambilight

Every ambient light module is aligned by a matrix and by the brightness. After replacement of a module, the brightness/color can be adjusted with the neighbouring modules. (attention! : this alignment is only supported for modules stuffed with the storage device).

1. Go to SAM.

2. Select “Alignments”.

3. Select “Ambilight”. A white test pattern shall be displayed by the ambilight modules.

4. Select the number of the module that have to be aligned. Module 1 is the first one which will come across according the wiring path, starting at the small signal panel, proceeding towards the ambient light modules.The first module will be attached to the next module 2. Module number 2 to number 3 etc.Herewith the way to define the ambilight module numbering.

5. Align the brightness compaired with the neighbouring modules. The brightness is automatically stored.

6. Select one of 10 matrixes which color matches most with the neighbouring modules, “matrix 0” is the factory alignment and can always be retrieved. (see table “6-11

Overview matrix correction table

7. The alignment is stored automatically (tip : don’t switch off the set immediately after the alignment is done, automatic storage can require a time frame of 10 seconds).

Table 6-6 White tone default setting 52" (Oscar)

White Tone e.g. 52PFL9606x Colour Temp R G B

Normal t.b.d. t.b.d. t.b.d. Cool t.b.d. t.b.d. t.b.d. Warm t.b.d. t.b.d. t.b.d.

Table 6-7 White tone default setting 58" (Oscar)

White Tone e.g. 58PFL9956x Colour Temp R G B

Normal t.b.d. t.b.d. t.b.d. Cool t.b.d. t.b.d. t.b.d. Warm t.b.d. t.b.d. t.b.d.

Table 6-8 White tone default setting 40" (Cannes)

White Tone e.g. 40PFL8606x Colour Temp R G B

Normal t.b.d. t.b.d. t.b.d. Cool t.b.d. t.b.d. t.b.d. Warm t.b.d. t.b.d. t.b.d.

Table 6-9 White tone default setting 46" (Cannes)

White Tone e.g. 46PFL86x6x Colour Temp R G B

Normal t.b.d. t.b.d. t.b.d. Cool t.b.d. t.b.d. t.b.d. Warm t.b.d. t.b.d. t.b.d.

Table 6-11 Overview matrix correction table

Matrix # fR fG fB

Matrix 0 1 1 1 Matrix 1 1 0.95 0.95 Matrix 2 0.95 1 0.95 Matrix 3 0.95 0.95 1 Matrix 4 0.95 1 1 Matrix 5 1 0.95 1 Matrix 6 1 1 0.95 Matrix 7 1 0.97 0.95 Matrix 8 0.97 0.95 1 Matrix 9 0.95 0.97 1

6.3.3 TCON alignment (not applicable)

6.4 Option Settings

6.4.1 Introduction

The microprocessor communicates with a large number of I ICs in the set. To ensure good communication and to make digital diagnosis possible, the microprocessor has to know which ICs to address.

Notes:

• After changing the option number(s), save them by pressing the OK button on the RC before the cursor is moved to the left, select STORE in the SAM root menu and press OK on the RC.

• The new option setting is only active after the TV is switched “off” / “stand-by” and “on” again with the mains switch (the NVM is then read again).

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EN 46 Q551.2E LA6.

Alignments

6.4.2 Dealer Options

For dealer options, in SAM select “Dealer options”. See Table 6-12

6.4.3 (Service) Options

From 2011 onwards, it is not longer possible to change individual option settings in SAM. Options can only be changed all at once by using the option codes as described in section

6.4.4

6.4.4 Opt. No. (Option numbers)

Select this sub menu to set all options at once (expressed in two long strings of numbers). An option number (or “option byte”) represents a number of different options. When you change these numbers directly, you can set all options very quickly. All options are controlled via eight option numbers. When the NVM is replaced, all options will require resetting. To be certain that the factory settings are reproduced exactly, you must set both option number lines. You can find the correct option numbers on a sticker inside the TV set. Example: The options sticker gives the following option numbers:

• 08192 00133 01387 45160

• 12232 04256 00164 00000 The first line (group 1) indicates hardware options 1 to 4, the second line (group 2) indicate software options 5 to 8. Every 5-digit number represents 16 bits (so the maximum value will be 65536 if all options are set). When all the correct options are set, the sum of the decimal values of each Option Byte (OB) will give the option number.

SAM mode overview.

After a SSB repair, the original channel map can be restored, provided that the original channel map was stored on a USB stick before repair was commenced and that basic functionality of the TV, needed for this procedure, was not hampered as a result of the defect. The procedure of “channel map cloning” is clearly described in the (electronic) user manual.

In case of a display replacement, reset the “Operation hours display” to “0”, or to the operation hours of the replacement display.

Diversity

Not all sets with the same Commercial Type Number (CTN) necessarily have the same option code! Use of Alternative BOM => an alternative BOM number usually indicates the use of an alternative display or power supply. This results in another display code thus in another Option code. Refer to Chapter 2.

Connections.

6.4.5 Option Code Overview

Refer to the sticker in the set for the correct option codes. Important: after having edited the option numbers as described above, you must press OK on the remote control before the cursor is moved to the left!

Technical Specifications, Diversity, and

6.5 Reset of Repaired SSB

A very important issue towards a repaired SSB from a Service repair shop (SSB repair on component level) implies the reset of the NVM on the SSB. A repaired SSB in Service should get the service Set type “00PF0000000000” and Production code “00000000000000”. Also the virgin bit needs to be set. To set all this, you can use the ComPair tool or use the “NVM editor” and “Dealer options” items in SAM (do not forget to “store”).

After a repaired SSB has been mounted in the set (set repair on board level), the type number (CTN) and production code of the TV has to be set according to the type plate of the set. For this, you can use the NVM editor in SAM. This action also ensures the correct functioning of the “Net TV” feature and access to the Net TV portals. The loading of the CTN and production code can also be done via ComPair (Model number programming).

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6.5.1 SSB identification

18310_221_090318.eps

090319

Whenever ordering a new SSB, it should be noted that the correct ordering number (12nc) of a SSB is located on a sticker on the SSB. The format is <12nc SSB><serial number>. The ordering number of the correct “Service” SSB is the one preceded by the letter “S” in case 2 or more ordering numbers are present on the bar code sticker.

6.6 Total Overview SAM modes

Table 6-12 SAM mode overview

Alignments

EN 47Q551.2E LA 6.

Figure 6-1 SSB identification

Main Menu Sub-menu 1 Sub-menu 2 Sub-menu 3 Description

Hardware Info A. SW version e.g. “Q5551_0.9.1.0 Display TV & Stand-by SW version and CTN serial

B. Stand-by processor version e.g. “STDBY_83.84.0.0” C. Production code e.g. “see type plate”

Operation hours Displays the accumulated total of operation hours.TV

Errors Displayed the most recent errors Reset error buffer Clears all content in the error buffer Alignment White point Colour temperature Normal 3 different modes of colour temperature can be

Warn

Cool White point red LCD White Point Alignment. For values, White point green White point blue

Ambilight Select module

Brightness Select matrix

Dealer options Virgin mode Off/On Select Virgin mode On/Off. TV starts up / does not

E-sticker Off/On Select E-sticker On/Off (USP’s on-screen) Auto store mode None

PDC/VPS TXT page PDC/VPS/TXT

Option numbers Group 1 e.g. “00008.00001.15421.02239” The first line (group 1) indicates hardware options 1

Group 2 e.g. “44816.34311.33024.00000” The second line (group 2) indicates software options

Store Store after changing Initialise NVM N.A. Store Select Store in the SAM root menu after making any

Operation hours display 0003 In case the display must be swapped for repair, you

Software maintenance Software events Display Display information is for development purposes

Clear Test reboot Test cold reboot Test application crash

Hardware events Display Display information is for development purposes

Clear

number

switched “on/off” & every 0.5 hours is increase one

selected

see Table 6-3

start up (once) with a language selection me nu after the mains switch is turned “on” for the first time (virgin mode)

to 4

5 to 8

changes

can reset the “”Display operation hours” to “0”. So, this one does keeps up the lifetime of the display itself (mainly to compensate the degeneration behaviour)

White tone default setting 32" (Oscar)

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EN 48 Q551.2E LA6.

Main Menu Sub-menu 1 Sub-menu 2 Sub-menu 3 Description

Test setting Digital info Current frequency: 538

Install start frequency 000 Install start frequency from “0” MHz Install end frequency 999 Install end frequency as “999” MHz Default install frequency Installation Digital only Select Digital only or Digital + Analogue before

Development file versions

Upload to USB Channel list Item “Channel list” removed from the user interface

Download from USB Channel list Item “Channel list” removed from the user interface

NVM editor Type number se e type plate NVM editor; re key-in type number and production

Development 1 file version Display parameters DIS PT5.0.9.29 Display information is for development purposes

Development 2 file version 12NC one zip software Display information is for development purposes

Personal settings Option codes Alignments Identification data History list All (options included)

Personal settings Option codes Alignments Identification data All (options included)

Production code see type plate

Alignments

QAM modulation: 64-qam Display information is for development purposes Symbol rate: Original network ID: 12871 Network ID: 12871 Transport stream ID: 2 Service ID: 3 Hierarchical modulation: 0 Selected video PID: 35 Selected main audio PID: 99 Selected 2nd audio PID: 8191

Digital + Analogue

Acoustics parameters ACSTS

5.0.6.20 PQ - TV550 1.0.27.22 PQS- Profile set PQF - Fixed settings PQU - User styles Ambilight parameters PRFAM 5.0. 5.2

Initial main software NVM version Q55x1_0.4.5.0 Flash units software Temp com file version none

installation

code after SSB replacement

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7. Circuit Descriptions

NXP

PNX85500

SOC

Active 3D

DVB-T (EU)

DVB-C (EU+HK)

Ethernet

PHY

CPLD

DVB-S2

Tuner

DVB-S2

Hybrid

Tuner

DDR2

4x 128MB-533

FLASH

512MB

9287

mux

buffer

SD-CARD

USB

CLASS-D

SPIAL

LCD

DVB-T2

Dongle

Back

light

PWM

8x PWM

Backlight dimming

Goggle drive

USB

HUB

Int-USB

Wifi

USB

I2C Enable FRED

19050_078_110506.eps

110506

Index of this chapter:

Introduction

7.1

7.2 Power Supply

7.3 DC/DC Converters

7.4 Front-End Analogue and DVB-T, DVB-C; ISDB-T reception

7.5 Front-End DVB-S(2) reception

7.6 HDMI

7.7 Video and Audio Processing - PNX855xx

7.8 Back-End Processing

Notes:

•Only new circuits (circuits that are not published recently) are described.

• Figures can deviate slightly from the actual situation, due to different set executions.

• For a good understanding of the following circuit descriptions, please use the wiring-, block- (see chapter

Block Diagrams) and circuit diagrams (see chapter

10.

Circuit Diagrams and PWB Layouts).Where necessary,

you will find a separate drawing for clarification.

Circuit Descriptions

7.1 Introduction

The Q551.2E LA chassis comes with the following stylings:

• Cinema 21:9 Gold (series 50PFL8956 & 50PFL7956),

• Cannes (series 4xPFL86x6),

• Design Line Contour (series 46PFL8906),

• Oscar (series xxPFL9606),

• Cinema 21:9 Platinum (58PFL9956).

7.1.1 TV550 2011 Architecture Overview

For details about the chassis block diagrams refer to chapter 9.

Block Diagrams. An overview of the TV550 2011 architecture

can be found in Figure 7-1

EN 49Q551.2E LA 7.

and Figure 7-2.

Figure 7-1 Architecture of TV550 platform 2011 (32" Oscar)

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19070_102_110720.eps

110720

Circuit Descriptions

Figure 7-2 Architecture of TV550 platform 2011 (remaining sets)

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7.1.2 SSB Cell Layout

19050_079_110506.eps

110506

Circuit Descriptions

EN 51Q551.2E LA 7.

Figure 7-3 SSB layout cells (top view) (32" Oscar)

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19051_168_110810.eps

110810

Circuit Descriptions

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Figure 7-4 SSB layout cells (top view) (remaining sets)

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Circuit Descriptions

EN 53Q551.2E LA 7.

7.2 Power Supply

7.2.1 Power Supply Unit

All power supplies are a black box for Service. When defective, a new board must be ordered and the defective one must be returned, unless the main fuse of the board is broken. Always replace a defective fuse with one with the correct specifications! This part is available in the regular market. Consult the Philips Service web portal for the order codes of the boards.

In this manual, no detailed information is available because of design protection issues.

7.2.2 Connector overview

Table 7-1 Connector overview 32" sets

Connector no. 1308 1316 1M95 Descr. Mains to display to SSB Pin CN1 CN2 CN4

1 N A2 +3V3SB 2 L n.c. Standby 3 - pin 5 GND1 4 - n.c. GND1 5 - pin 3 +12V3 6 - n.c. +12V3 7-OCD +Vsnd 8 - n.c. GND1 9 - A1 BL-ON-OFF 10 - n.c. BL-DIM1 11 - pin 13 BL-I-CTRL 12 - n.c. POK 13 - pin 11 +24V 14 - n.c. GND1 15 - GND1 -

Table 7-2 Connector overview 37" sets

Connector no. 1308 1316 1M95 Descr. Mains to display to SSB Pin CN1 CN2 CN4

1 N Anode_R +3V3stdby 2 L n.c. Standby 3 - R5 Cathode GND1 4 - R4 Cathode GND1 5 - R3 Cathode +12V 6 - R2 Cathode +12V 7 - R1 Cathode +Vsnd (+24V) 8 - L1 Cathode GND_SND 9 - L2 Cathode BL-ON-OFF 10 - L3 Cathode BL-DIM1 (Vsync) 11 - L4 Cathode BL-I-CTRL 12 - L5 Cathode POK 13 - n.c. +24V (AL2_DVBS) 14 - Anode_L GND1 15 - - -

Table 7-3 Connector overview 40 - 46" sets

Connector no. 1308 1316 1M95 Descr. Mains to display to SSB Pin CN1 CN2 CN4

1 N Anode 1+ +3V3stdby 2 L n.c. Standby 3 - Cathode 1- GND1 4-n.c. GND1 5 - Anode 2+ +12V 6-n.c. +12V 7 - Cathode 2- +Vsnd (+24V) 8 - n.c. GND_SND 9 - Anode 3+ BL-ON-OFF 10 - n.c. BL-DIM1 (Vsync) 11 - Cathode 3- BL-I-CTRL 12 - n.c. POK 13 - Anode 4+ +24V (AL2_DVBS) 14 - n.c. GND1 15 - Cathode 4- -

Table 7-4 Connector overview 50" Sundance sets

Connector no. 1308 1319 1M95 Descr. Mains to display to SSB Pin CN1 CN3 CN4

1 N 24Vled +3V3stdby 2 - 24Vled Standby 3 L 24Vled GND1 4 - 24Vled GND1 5 - 24Vled +12V 6 - GND1 +12V 7 - GND1 +Vsnd 8 - GND1 GND_SND 9 - GND1 BL-ON-OFF 10 - GND1 BL-DIM1 (Vsync) 11 - n.c. BL-I-CTRL 12 - BL-ON-OFF POK 13 - n.c. +24V (AL2_DVBS) 14 - BL-DIM1 GND1 15 - - -

Table 7-5 Connector overview 52" sets

Connector no. 1308 1316 1319 1M95 Descr. Mains to display to display to SSB Pin CN1 CN2 CN3 CN4

1 N 24V 24V +3V3stdby 2 L 24V 24V Standby 3 - 24V 24V SGND 4 - 24V 24V SGND 5 - 24V 24V +12V 6 - SGND SGND +12V 7 - SGND SGND +24V 8 - SGND SGND SGND 9 - SGND SGND BL-ON 10 - SGND SGND BL-DIM 11 - n.c. n.c. BL-I-CTRL 12 - BL-ON n.c. POK 13 - n.c. - +24V) 14 - n.c. - SGND 15 - - - -

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+5V5-TUN

196 mA

+5V

+5V5-TUN +5V-TUN

2179 mA 196 mA

+12V +3V 3

+3 V3 +2V5

2919 mA 2371 mA 450 mA

+1V8

+1V8 +1V2

2450 mA 550 mA

+1V1

5100 mA

+1V1 dc-dc

+5V

dc-dc

+5V-TUN stabilizer

+3 V3 dc-dc

+2V5

stabilizer

+1V8 dc-dc

+1V2

stabilizer

18770_235_100127.eps

100219

Circuit Descriptions

Table 7-6 Connector overview 58" sets

Connector no. 1308 1316 1319 1M95 Descr. Mains to display to display to SSB Pin CN1 CN4 CN3 CN5

1 N V01 V02 +3V3stdby 2 L V01 V02 PS-ON 3 - V01 V02 SGND 4 - V01 V02 SGND 5 - V01 V02 SGND 6 - V01 V02 +12V3 7 - V01 V02 +12V3 8 - V01 V02 +12V3 9 - V01 V02 24VA 10 - V01 V02 SGND 11 - V01 V02 n.c. 12 - V01 V02 13 - V01 V02 14 - V01 V02 15 - - - -

7.3 DC/DC Converters

The on-board DC/DC converters deliver the following voltages (depending on set execution):

• +3V3-STANDBY, permanent voltage for the Stand-by controller, LED/IR receiver and controls; connector 1M95 pin 1

• +12V, input from the power supply for TV550 common (active mode); connector 1M95 pins 6, 7 and 8

• +24V, input from the power supply for DVB-S2 (in active mode); connector 1M09 pins 1 and 2

• +1V1, core voltage supply for PNX855xx; has to be started up first and switched "off" last (diagram B03B)

• +1V2, supply voltage for analogue blocks inside PNX855xx

• +1V8, supply voltage for DDR2 (diagram B03B)

• +2V5, supply voltage for analogue blocks inside PNX855xx (see diagram B03E)

• +3V3, general supply voltage (diagram B03E)

• +5V, supply voltage for USB and CAM (diagram B03E)

• +5V-TUN, supply voltage for tuner (diagram B03E)

• +V-LNB, input voltage for LNB supply IC (item no. 7T50)

• +5V-DVBS, input intermediate supply voltage for DVB-S2 (diagram B08A)

• +3V3-DVBS, clean voltage for silicon tuner and DVB-S2 channel decoder

• +2V5-DVBS, clean voltage for DVB-S2 channel decoder

• +1V-DVBS, core voltage for DVB-S2 channel decoder.

A +12 V under-voltage detector (see diagram B03C) enables the 12V to 3.3V and 12V to 5V DC/DC converters via the ENABLE-3V3-5V line, and the 12V to 1.8V DC/DC converter via the ENABLE-1V8 line. DETECT2 is the signal going to the Stand-by microcontroller and ENABLE-3V3n is the signal coming from the Stand-by microcontroller.

• the switching frequency of the +5V-DVBS to +1-DVBS switched mode converter is 900 kHz (item no. 7T00)

• a delay line for the +2V5-DVBS and +1V-DVBS lines is created with item no. 3T03 (R=10k) and 2T06 (C=100n)

• a 3.3V to 2.5V linear stabiliser is built around item no. 7T01

• a 5V to 3.3V linear stabiliser is built around item no. 7T02.

Diagram B08B contains the DVB-S2 LNB supply:

• the +V-LNB signal comes from item no. 7T03

• the V0-CTRL signal goes to item no. 7T03

• the LNB-RF1 goes to the LNB.

Figures gives a graphical representation of the DC/DC converters with its current consumptions:

Figure 7-5 DC/DC converters

7.4 Front-End Analogue and DVB-T, DVB-C; ISDB-T reception

7.4.1 European/China region

The Front-End for the European/China region consist of the following key components:

• Hybrid Tuner

• Switchable SAW filter 7/8 MHz (Eur.), or single SAW filter

(8 MHz) (China)

• Bandpass filter

•Amplifier

• PNX855xx SoC TV processor with integrated DVB-T and

DVB-C channel decoder and analogue demodulator.

Below find a block diagram of the front-end application for this region.

Diagram B03D contains the following linear stabilisers:

• +2V5 stabiliser, built around item no. 7UCO

• +5V-TUN stabiliser, built around items no. 7UA6 and 7UA7

• +1V2 stabiliser, built around items no. 7UA3 and 7UA4.

Diagram B08A contains the DVB-S2-related DC/DC converters and -stabilisers:

• a +24V under-voltage detection circuitry is built around item no. 7T04

• the switching frequency of the 24 to 14...20V switched mode converter is 350 kHz (item no. 7T03 and +V-LNB lines)

• the output signal on the +V-LNB line goes to the LNBH23Q (item no. 7T50)

• the LNBH23Q (item no. 7T50) sends a feedback signal via the V0-CNTRL line

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Figure 7-6 Front-End block diagram European/China region

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7.5 Front-End DVB-S(2) reception

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100203

The Front-End for the DVB-S(2) application consist of the following key components:

Circuit Descriptions

EN 55Q551.2E LA 7.

• Satellite Tuner; I decoder)

• Channel decoder; I

• LNB switching regulator; I

C address 0xC6 (bridged via channel

C address 0xD0

C address 0x14

• Amplifier

• PNX855xx SoC TV processor with integrated DVB-T and DVB-C channel decoder and analogue demodulator.

Below find a block diagram of the front-end application for DVB-S(2) reception.

Figure 7-7 Front-End block diagram DVB-S(2) reception

This application supports the following protocols:

• Polarization selection via supply voltage (18V = horizontal, 13V = vertical)

• Band selection via “toneburst” (22 kHz): tone “on” = “high” band, tone “off” = “low” band

• Satellite (LNB) selection via DiSEqC 1.0 protocol

• Reception of DVB-S (supporting QPSK encoded signals) and DVB-S2 (supporting QPSK, 8PSK, 16APSK and 32APSK encoded signals), introducing LDPC low-density parity check techniques.

7.6 HDMI

Figure 7-8 HDMI input configuration

The following multiplexers can be used:

• Sil9187A (does not support “Instaport” technology for fast switching between input signals)

• Sil9287B (supports “Instaport” technology for fast switching between input signals).

The hardware default I

C addresses are:

• Sil9187A: 0xB0/0xB2 (random: software workaround)

• Sil9287B: 0xB2 (fixed).

The Sil9x87 has the following specifications:

• +5V detection mechanism

• Stable clock detection mechanism

• Integrated EDID

• RT control

• HPD control

• Sync detection

• TMDS output control

• CEC control

• EDID stored in Sil9x87, therefore there are no EDID pins on the SSB.

In this platform, the Silicon Image Sil9x87 HDMI multiplexer is implemented. Refer to figure 7-8

HDMI input configuration for

the application.

7.7 Video and Audio Processing - PNX855xx

The PNX855xx is the main audio and video processor (or System-on-Chip) for this platform. It has the following features:

• Multi-standard digital video decoder (MPEG-2, H.264, MPEG-4)

• Integrated DVB-T/DVB-C channel decoder

• Integrated CI+

• Integrated motion accurate picture processing (MAPP2)

• High definition ME/MC

• 2D LED backlight dimming option

• Embedded HDMI HDCP keys

• Extended colour gamut and colour booster

• Integrated USB2.0 host controller

• Improved MPEG artefact reduction compared with PNX8543

• Security for customers own code/settings (secure flash).

The TV550 combines front-end video processing functions, such as DVB-T channel decoding, MPEG-2/H.264 decode, analog video decode and HDMI reception, with advanced back-end video picture improvements. It also includes next generation Motion Accurate Picture Processing (MAPP2). The MAPP2 technology provides state-of-the-art motion artifact reduction with movie judder cancellation, motion sharpness

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TS out/in for

TS input

CVBS, Y/C,

LVDS for

analog CVBS

SPDIF

Low-IF

SSIF, LR

HDMI

CI/CA

MPEG

PRIMARY

LVDS

VIDEO

SECONDARY

MEMORY

VIDEO

3D COMB

DIGITAL IF

AUDIO DEMOD

AUDIO IN

HDMI

SCALER,

AUDIO DSP

AUDIO DACS

AUDIO OUT

450 MHz

560 MHz

I2C

PWM

GPIO IR ADC UART I2C GPIO Flash

analog audio

I2S SPDIF

SYSTEM

USB 2.0

PNX85500x

DVB-T/C

channel decoder

DVB

AV-PIP

SPI

MPEG/H.264

RECEIVER

(8051)

CONTROLLER

AND DECODE

DECODER

PCMCIA

RGB

PROCESSOR

SYSTEM

CONTROLLER

DECODER

VIDEO

24KEf CPU

MIPS32

x 8

AV-DSP

REDUCTION

AND NOISE

DE-INTERLACE

OUTPUT

VIDEO

SUB-PICTURE

ENCODER

OUTPUT

VIDEO

quad channel)

(single, dual or

flat panel display

DRAWING

ENGINE

DMA BLOCK

Motion-accurate pixel processing

Memory

Card

Ethernet

MAC

Circuit Descriptions

and vivid colour management. High flat panel screen resolutions and refresh rates are supported with formats including 1366 × 768 @ 100Hz/120Hz and 1920 × 1080 @ 100Hz/120Hz. The combination of Ethernet, CI+ and H.264 supports new TV experiences with IPTV and VOD. On top of that, optional support is available for 2D dimming in

combination with LED backlights for optimum contrast and power savings up to 50%.

For a functional diagram of the PNX855xx, refer to Figure 7-9

7.8 Back-End Processing

All sets except the 32" Oscar have a back-end board. For the configuration, refer to Figure 7-10

to Figure 7-13.

Figure 7-9 PNX855xx functional diagram

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Circuit Descriptions

19051_169_110810.eps

110810

Back-end Board FPGA + FRC-V

FPGA LX25

2D/3D or 3D/3D

Local Contrast

Int Dongle

DDR2

1 × 64MB-800

Vsync, LR

Trident

FRC-V

DDR3

2 × 128MB-1333

1W35

Sound in stand

detection

I2C

Mux

LCD

8 × Vx1

Backlight

1F53

FPGA

Vx1/LVDS Connector

SPLASH-ON

BL-ON

3D-LED

C-Set

ENABLE-DCDC

Dual LVDS

LVDS Connector

SPI/Vsync

EN 57Q551.2E LA 7.

Figure 7-10 Back-end board Oscar except 37"

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110810

Back-end Board FPGA + FRC-V

Trident

FRC-V

FPGA LX25

2D/3D or 3D/3D

Local Contrast

Int Dongle

Backlight

DDR2

1 × 64MB-800

DDR3

2 × 128MB-1333

Vsync, LR

8 × LVDS

I2C

Mux

5 × BL – PWM

1W35

Sound in stand

detection

LCDBacklight

1M54

PSU

TCON

BL-PWM

SPLASH-ON

BL-ON

3D-LED

C-Set

ENABLE-DCDC

Dual LVDS

LVDS Connector

8 × mini LVDS

FPGA

Backlight

19051_171_110810.eps

110810

Back-end Board FPGA + FRC-V

Trident

FRC-V

FPGA LX25

2D/3D or 3D/3D

Local Contrast

Int Dongle

Backlight

DDR2

1 × 64MB-800

DDR3

2 × 128MB-1333

8 × BL – PWM

Vsync, LR

8 × Vx1

I2C

Mux

1W35

Sound in stand

detection

LCD

Backlight

1M54

PSU

Vx1/LVDS Connector

BL-PWM

SPLASH-ON

BL-ON

3D-LED

C-Set

ENABLE-DCDC

Dual LVDS

LVDS Connector

FPGA

Backlight

Circuit Descriptions

2011-Sep-09

Figure 7-11 Back-end board Oscar 37"

Figure 7-12 Back-end board Cannes

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Circuit Descriptions

19051_172_110810.eps

110810

Back-end Board FPGA + FRC-V

FPGA LX25

2D/3D or 3D/3D

Local Contrast

DDR2

1 × 64MB-800

BL-PWM

Trident

FRC-V+

DDR3

2 × 128MB-1333

Enable LGD 2D Dimming

4 × HS LVDS

I2C

Mux

1M95

1W35

Sound in stand

detection

LCDBacklight

PSU

SPLASH-ON

BL-ON

C-Set

ENABLE-DCDC

Dual LVDS

LVDS Connector

LVDS Connector LVDS Connector

EN 59Q551.2E LA 7.

Figure 7-13 Back-end board Sundance

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110810

I/O

DC/DC

1M99 (10p)

1M85

1F53

DC/DC

DDR

DDR 2

512M

FPGA

Trident FRC-V

27x27

1.0

DDR

GPIO

WX2+

LVDS

TRANS

WX0-

LVDS

TRANS

R×B4+

LVDS

REC

R×A0-

1G51: 51pin1T51: 51pin

1M09

(4p)

1M841M83

1W35 1T011T25

FPGA

1M54

(9p TH)

1T02

1T03

1T20

1SG2

Circuit Descriptions

Figure 7-14 Back-end layout cells (top view) Oscar except 37" & Cannes

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Circuit Descriptions

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110810

I/O

1F53

DC/DC

1L01: 80pin

1M09

1W35

1T25

1L02: 80pin

1G51: 51pin

DDR

DDR 2

512M

FPGA

Trident

FRC-V

27x27

1.0

TCON IC LG

FPGA

1M99 (10p)

1M54

(9p TH)

1T03 1T02

DC/DC +

DC/DC

TCON

1SG2

1T01

DDR

GPIO

WX2+

LVDS

TRANS

WX0-

LVDS

TRANS

R×B4+

LVDS

REC

R×A0-

19051_175_110810.eps

110810

KEEPOUT

DC/DC

1M99

(10p TH) (VDISP)

DC/DC

1W35

FPGA

DDR

1G511T51

DDR

Trident

FRC-V

27x27

1.0

1M09

1T25

1T02

DDR

GPIO

WX2+

LVDS

TRANS

WX0-

LVDS

TRANS

R×B4+

LVDS

REC

R×A0-

EN 61Q551.2E LA 7.

Figure 7-15 Back-end layout cells (top view) Oscar 37"

Figure 7-16 Back-end layout cells (top view) Sundance

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110907

5 9

SSB

Glue logic

Microprocessor

8 3

AmbiLight

8 3

AmbiLight

8 3

AmbiLight

optional

19052_004_110907.eps

110907

7.9 AmbiLight

For the configuration, refer to Figure 7-17 to Figure 7-18.

Figure 7-17 High-level architecture AmbiLight 2-/3-sided (12-V implementation)

Circuit Descriptions

Figure 7-18 Low-level architecture AmbiLight 2-/3-sided (12-V implementation)

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8. IC Data Sheets

18770_301_100217.eps

100217

Block diagram

Pinning information

Note : The LED port indicators only apply to USB2513i.

To Upstream

BUS

3.3 V

Upstream

PHY

Upstream

USB Data

Repeater

Controller

Serial

Interface

Engine

Serial

Interface

To EEPROM or

SMBus Master

SCL

SDA

Port

Controller

Bus-

Power

Detect/

bus

Pulse

PHY#1

USB Data

Downstream

Sense

Switch/

LED

Drivers

USB Data

Downstream

Port

Power

3.3 V

PLL

24 MHz

Crystal

Routing & Port Re-Ordering Logic

Regulator

CRFILT

Port

Power

Regulator

PHY#x

Port #x

OC Sense

Switch Driver/

LED Drivers

TT #1

...

Port #1

OC Sense

Switch Driver/

LED Drivers

OC Sense Switch/

LED

Drivers

...

The ‘x’ indicates the number of available downstream ports: 2, 3, 4, or 7.

Ground Pad

(must be connected to VSS)

SMSC

USB2512/12A/12B

USB2512i/12Ai/12Bi

(Top View QFN-36)

VDD33

RESET_N24HS_IND / CFG_SEL[1]23SCL / SMBCLK / CFG_SEL[0]

SDA / SMBDATA / NON_REM[1]

VBUS_DET

OCS_N[2]

PRTPWR[2] / BC_EN[2]*

OCS_N[1]

VDD33

CRFILT

PRTPWR[1] / BC_EN[1]*

TEST

VDD33

SUSP_IND / LOCAL_PWR / NON_REM[0]

VDD33

USBDP_UP

XTALOUT

XTALIN / CLKIN

RBIAS

VDD33

PLLFILT

USBDM_UP

VDD33

USBDM_DN[1]

USBDP_DN[1]

USBDM_DN[2]

USBDP_DN[2]

5NC6

8NC9

Indicates pins on the bottom of the device.

IC Data Sheets

EN 63Q551.2E LA 8.

This chapter shows the internal block diagrams and pin configurations of ICs that are drawn as “black boxes” in the

8.1 Diagram USB Hub B01C, USB2513B (IC 7F25)

electrical diagrams (with the exception of “memory” and “logic” ICs).

Figure 8-1 Internal block diagram and pin configuration

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Block diagram

Pinning information

LM75B

SDA

SCLA0

DNG1AA2

BIAS

REFERENCE

BAND GAP

TEMP SENSOR

OSCILLATOR

POWER-ON

RESET

11-BIT

SIGMA-DELTA

A-to-D

CONVERTER

POINTER

TIMER

COMPARATOR/

INTERRUPT

COUNTER

LOGIC CONTROL AND INTERFACE

CONFIGURATION

THYST

TOS

TEMPERATURE

LM75BDP

VADS

0ALCS 1ASO

2ADNG

1 2

3 4

6 5

8 7

8.2 Diagram Temperature sensor & AmbiLight B01J, LM75BDP (IC 7FD1)

IC Data Sheets

2011-Sep-09

Figure 8-2 Pin configuration

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8.3 Diagram NANDflash - conditional access B02A, PNX855xx (IC7S00)

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100217

Block diagram

Pinning information

TS out/in for

TS input

CVBS, Y/C,

LVD S for

analog CVBS

SPDIF

Low-IF

SSIF, LR

HDMI

CI/CA

MPEG

PRIMARY

LVD S

VIDEO

SECONDARY

MEMORY

VIDEO

3D COMB

DIGITAL IF

AUDIO DEMOD

AUDIO IN

HDMI

SCALER,

AUDIO DSP

AUDIO DACS

AUDIO OUT

450 MHz

500 MHz

I2C

PWM

Px_x IR ADC UART I2C GPIO Flash

analog audio

I2S

SPDIF

SYSTEM

USB 2.0

PNX8550x

DVB-T/C

channel decoder

DVB

AV-PIP

SPI

RECEIVER

(8051)

CONTROLLER

AND DECODE

DECODER

PCMCIA

RGB

PROCESSOR

SYSTEM

CONTROLLER

MULTI-

STANDARD

VIDEO

DECODER

24KEf CPU

MIPS32

x 10

AV-DSP

REDUCTION

AND NOISE

DE-INTERLACE

OUTPUT

VIDEO

SUB-PICTURE

ENCODER

OUTPUT

VIDEO

quad channel)

(single, dual or

flat panel display

DRAWING

ENGINE

Scatter/Gather

TS Demux

Motion-accurate pixel processing

Memory

Card

Ethernet

MAC

analog Y/C

Direct-IF

PNX8550xE

Transparent top view

2468 10 121314

15 171619

18 20

21 23

22 242526

1 3 57911

ball A1 index area

IC Data Sheets

EN 65Q551.2E LA 8.

Figure 8-3 Internal block diagram and pin configuration

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100402

Block diagram

Pinning information

1 2

4 5 6 7

9 10 11 12

24 23 22 21 20 19 18 17 16 15 14 13

PVCCL

MUTE

LIN

RIN

BYPASS

AGND AGND

PVCCR

VCLAMP

PVCCR

PGNDL PGNDL LOUT BSL AVCC AVCC GAIN0 GAIN1 BSR ROUT PGNDR PGNDR

PWP (TSSOP) PACKAGE

(TOP VIEW)

PVCCL

TPA3120D2

PVCCR

VCLAMP

GAIN1

BYPASS

0.22 F

AGND

}

Control

Shutdown

Control

LIN RIN

BSR

BSL

PGNDR

PGNDL

0.22 F 22 H

22 H

0.68 F

470 F

0.68 F

470 F

GAIN0

AVCC

MUTE

ROUT

LOUT

8.4 Diagram Audio B03A, TPA312xD2PWP (IC7D10)

IC Data Sheets

2011-Sep-09

Figure 8-4 Internal block diagram and pin configuration

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8.5 Diagram DC/DC B03B, TPS53126PW (IC7U03)

18310_300_090319.eps

100416

Block diagram

Pinning information

VBST1

NC EN1 VO1

VFB1

GND

TEST1

VFB2

VO2 EN2

VBST2

DRVH1 LL1 DRVL1

PGND1 TRIP1 VIN

VREG5 V5FILT

TEST2 TRIP2

PGND2

DRVL2

LL2

DRVH2

28 27 26 25 24 23 22 21 20 19 18 17 16

1 2

4 5 6 7

10 11 12 13 14

TPS5 3 124

IC Data Sheets

EN 67Q551.2E LA 8.

Figure 8-5 Internal block diagram and pin configuration

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110601

Block diagram

Pinning information

PowerSO-8

DFN8 (4 × 4)

ST1S10PH

IC Data Sheets

8.6 Diagram DC/DC B03E, ST1S10PH (IC 7UD0)

2011-Sep-09

Figure 8-6 Internal block diagram and pin configuration

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8.7 Diagram DC/DC B03E, LD1117DT25 (IC 7UD2)

F_15710_166.eps

100402

Block diagram

Pinning information

DPAK

LD1117DT

IC Data Sheets

EN 69Q551.2E LA 8.

Figure 8-7 Internal block diagram and pin configuration

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Block diagram

Pinning information

10M Rx

Logic

100M Rx

Logic

DSP System:

Clock

Data Recovery

Equalizer

Analog-to-

Digital

100M PLL

Squelch &

Filters

10M PLL

Receive Section

Central

Bias

HP Auto-MDIX

Management

Control

SMI

RMII / MII Logic

TXP / TXN

TXD[0:3]

TXEN TXER

TXCLK

RXD[0:3]

RXDV RXER

RXCLK

CRS

COL/CRS_DV

MDC

MDIO

LED1 LED2

LED Circuitry

MODE Control

nINT

nRST

RXP / RXN

10M Tx

Logic

10M

Transmitter

100M Tx

Logic

100M

Transmitter

Transmit Se ction

PLL

XTAL1/CLKIN XTAL2

MODE0 MODE1 MODE2

PHY Address Latches

PHYAD[0:2]

Auto-

Negotiation

Interrupt

Generator

RMIISEL

MDIX

Control

Reset

Control

RBIAS

VDD2A LED2 /n INTSEL LED1/REGOFF

XTAL2

XTAL1/CLKIN

VDDCR

RXD3/PHYAD2

RXCLK/PHYAD1

RXD2/RMIISEL

RXD1/MODE1

RXD0/MDE0

VDDIO

RXER/RXD4/PHYAD0

CRS

MDIO

COL/CRS_DV/MODE2

TXD2

MDC

nRST nINT/TXER/TXD4

TXD0 TXEN TXCLK

TXD1

RBIAS

TXD3

TXN

RXDV

RXN

VDD1A

TXP

RXP

1 2 3 4 5 6 7 8

SMSC

LAN8710/LAN8710i

32 PIN QFN

(Top V iew )

22 21 20 19 18 17

2516

24 23

VSS

IC Data Sheets

8.8 Diagram Ethernet & Service B04C, LAN8710A-EZKH (IC 7E10)

2011-Sep-09

Figure 8-8 Internal block diagram and pin configuration

back to

div. table

Page 71

8.9 Diagram HDMI B04D, SII9x87B (IC 7EC1)

18770_303_100217.eps

100217

Block diagram

Pinning information

IC Data Sheets

EN 71Q551.2E LA 8.

Figure 8-9 Internal block diagram and pin configuration

back to

div. table

2011-Sep-09

Page 72

EN 72 Q551.2E LA8.

18770_309_100217.eps

110602

Block diagram

Pinning information

Bias

Control

IN1−

BYP

TPA6111A2

ASS

SHUTDOWN

IN2−

−

1 2 3 4

8 7 6 5

IN1−

BYPASS

GND

IN2− SHUTDOWN

D OR DGN PACKAGE

(TOP VIEW)

8.10 Diagram Headphone B04E, TPA6111A2DGN (IC 7EE1)

IC Data Sheets

Figure 8-10 Internal block diagram and pin configuration

2011-Sep-09

back to

div. table

Page 73

8.11 Diagram DVBS-FE B07A, STV6110AT (IC 7R02)

18770_304_100217.eps

110601

Block diagram

STV6110AT

PLL, dividers

Amplifier

RF_IN

C bus interface

AGC

RF_OUT

SCL

XTAL_IN

SDA

DC offset compensation

XTAL_OUT

XTAL_INN

IC Data Sheets

EN 73Q551.2E LA 8.

Figure 8-11 Internal block diagram and pin configuration

back to

div. table

2011-Sep-09

Page 74

EN 74 Q551.2E LA8.

18770_305_100217.eps

110601

Block diagram

7FB1

Soft Start

COMP

Current Comparator

f(I

DRAIN1

) + DC(ofst)

Anti-Cross

Conduction

1.2 MHz Oscilator

Divide by 2/4

Ramp Gen 1

Ramp Gen 2

CLK1

CLK2

CLK1

Weak Pull-Down MOSFET

5EN1

6EN2

6 A6 A

VDD2

Internal Control

10SEQ

150 k

Output

Undervoltage

Detect

FB1

FB2

CLK1

TPS54283PWP

4GND

8FB2

Soft Start

COMP

Current Comparator

Anti-Cross

Conduction

CLK2

Weak Pull-Down MOSFET

11BP

9ILIM2

150 k

CLK2

4GND

Level

Select

5.25-V

Regulator

References

BOOT1

PVDD1

SW1

BOOT2

PVDD2

SW2

f(I

DRAIN2

) + DC(ofst)

0.8 V

REF

MAX2

(Set to one of two limits)

f(I

DRAIN1

)

f(I

MAX1

)

Overcurrent Comp

f(I

SLOPE1

)

Level

Shift

Level

Shift

f(I

DRAIN2

)

f(I

MAX2

)

f(I

SLOPE2

)

FET Switch

TSD

PVDD2

f(I

SLOPE1

)

f(I

SLOPE2

)

SD1 SD2 UVLO

0.8 V

REF

SD2

0.8 V

REF

SD1

UDG-07007

Overcurrent Comp

COMP

IC Data Sheets

8.12 Diagram DVBS supply B08A, TPS54283PWP (IC 7T03)

Figure 8-12 Internal block diagram and pin configuration

2011-Sep-09

back to

div. table

Page 75

8.13 Diagram DVBS supply B08B, LNBH23Q (IC 7T50)

18770_306_100217.eps

100217

Block diagram

Pinning information

SDA SCL

LNBH23

ADDR

A-GND

IC Diagnostics

IC interface

DSQIN

Vup

VoRX

VoTX

22KHz Oscill.

PWM

Controller

Rsense

VSEL

Linear Post-reg +Modulator +Protections +Diagnostics

ITEST

TTX

VSEL

VOUT Control

EXTM

P-GND

Preregulator +U.V.lockout +P.ON reset

BypVcc Vcc- LISEL TTX

TEN

DSQOUT

DETIN

22KHz Tone Amp. Diagn.

22KHz Tone Freq. Detector

TTX

VCTRL

SDA SCL

LNBH23

ADDR

A-GND

IC Diagnostics

IC interface

DSQIN

Vup

VoRX

VoTX

22KHz Oscill.

PWM

Controller

Rsense

VSEL

Linear Post-reg +Modulator +Protections +Diagnostics

ITEST

TTX

VSEL

VOUT Control

EXTM

P-GND

Preregulator +U.V.lockout +P.ON reset

BypVcc Vcc- LBypVcc Vcc- LISEL TTX

TEN

DSQOUT

DETIN

22KHz Tone Amp. Diagn.

22KHz Tone Freq. Detector

TTXTTX

VCTRL

1n.c. 2n.c. 3 n.c . 4LX 5P-GND 6 SDA 7n.c. 8 n.c .

9 SCL 10A DD R 11D SQout 12D SQIN 13 EXTM 14TTX 15B Y P 16n.c . 17n.c . 18 Vcc-L 19V c c 20A -GND 21V oRX 22V oTX 23 n.c. 24n.c . 25n.c . 26n.c . 27V up 28 ISEL 29D ETIN

30VCTRL 31n.c. 32n.c.

Connected with power grounds and to the ground layer through vias to dissipate the heat.

Epad

IC Data Sheets

EN 75Q551.2E LA 8.

Figure 8-13 Internal block diagram and pin configuration

back to

div. table

2011-Sep-09

Page 76

EN 76 Q551.2E LA8.

Personal Notes:

10000_012_090121

110

IC Data Sheets

2011-Sep-09

back to

div. table

Page 77

9. Block Diagrams

MAIN POWER SUPPLY

32" PSLC-P019A

(1050)

LCD DISPLAY

(1004)

WIRING DIAGRAM 32" OSCAR

1M95

14P

1316

10P

1319

12P

1M54

2P3

1308

1M09

SSB

3104 313 6538.x

(1011)

AMBILIGHT MODULE

(1073)

AMBILIGHT MODULE

(1075)

19050_036_110421.eps

110801

1735

(B03A)

1. LEFT-SPEAKER

2. GND-AUDIO

3. GND-AUDIO

4. RIGHT-SPEAKER

1H95

(B11B)

1. +3V3-STANDBY

2. STANDBY-1

3. GND

4. GND

5. +12VIN

6. +12VIN

7. +24V-AUDIO-POWER

8. GND-AUDIO

9. LAMP-ON-1

10. BACKLIGHT-PWM_BL-VS-1

11. BACKLIGHT-BOOST-1

12. POWER-OK-1

13. +24V

14. GND

1M54

(B11B)

1. GND

2. BL-DIM5

3. BL-DIM6

4. BL-DIM7

5. BL-DIM8

6. BL-DIM9

7. BL-DIM10

8. BL-DIM11

9. BL-DIM12

1H24

(B11B)

1. +3V3-1

2. USB-WIFI-DDn

3. USB-WIFI-DDp

4. GND

5. GND

6. GND

1H99

(B11B)

1. GND_AL_BRG

2. +12V_AL_BRG

3. GND_AL_BRG

4. +12V_AL_BRG

1W35

(B11B)

1. GND

2. N.C.

3. AUDIO-SPEAKERn

1G51

(B06B)

1. +VDISP

2. +VDISP

3. +VDISP

4. +VDISP | |

51. N.C.

1H59

(B11B)

1. AMBI-SPI-CLK-OUT

2. GND

3. AMBI-SPI-SDO-OUT

4. AMBI-SPI-SDI-OUT-GI

5. V-AMBI

6. AMBI-PWM-CLK_B2

7. GND

8. AMBI-SPI-CS-OUTn_R2

9. AMBI-LATCH1_G2

10. V -AMBI

11. AMBI-BLANK_R1

12. AMBI-PROG_B1

13. AMBI-LATCH2_DIS

14. AMBI-TEMP-1

15. GND_AL_BRG

16. GND_AL_BRG

17. GND_AL_BRG

18. GND_AL_BRG

19. GND_AL_BRG

20. N.C.

21. +12V_AL_BRG

22. +12V_AL_BRG

23. +12V_AL_BRG

24. +12V_AL_BRG

25. +12V_AL_BRG

26. +12V_AL_BRG

1M54

1M83

926

AMBILIGHT MODULE

(1070)

AMBILIGHT MODULE

(1072)

1M83

26P

1M84

26P

1H95

14P

1H99

1W35

1735

1M21

18P

1M21

18P

1H59

26P

1G50

41P

1G51

51P

INLET

MAINS

SWITCH

(8408)

1M84

26P

1M84

26P

1M83

26P

1M84

26P

1M83

26P

1M20

11P

1M22

11P

TO STAND

IR/LED/KEYBOARD

(1010)

1H24

1M21

(B09A)

1. LIGHT-SENSOR

2. LED-1

3. LED-2

4. GND

5. KEYBOARD

6. +3V3-STANDBY

7. RC

8. +5V

9. N.C.

10. GND

11. N.C.

12. N.C.

13. N.C.

14. GND

15. N.C.

16. 3D-LED

17. N.C.

18. N.C.

WIFI-MODULE

(1042)

3D TRANSMITTER

(1002)

WIFI

(1041)

8151

8735

8801

8802

8408

8121

8150

8309

8354

8683

8584

8120

8583

8395

8684

WIFI

(1040)

8324

9-1 Wiring diagram Oscar 32"

Block Diagrams

EN 77Q551.2E LA 9.

2011-Sep-09

back to

div. table

Page 78

9-2 Wiring diagram Oscar 37"

Wifi

(1040)

1M83

1M8 4

1M8 3

1M84

8395

INLET

2p3

1316 14 p

1M09

1M95

1M99

14 p

10p

1M84

1M83

1M84

8584

8683

8684

1M21

Led & Control (1010)

11p

18p

1M20

11p

8802

8152

8154

1L011L02

1M54

1M95

1M99

14 p

1M21

18p

51p

1735

1M59

1F24 5p

1W35

3p 10p

1M99

1M54

8M99

8M54

(1)

1G51

MAINS

SWITC

26p

SSB 3104 313 6539.x

(1011

)

Bolt On

(1030

)

1308

Wifi

(1040

)

Wifi

(1041)

8801

8121

80p

8735

8583

8324

Main Power Supply

(1050)

8408

8M09

8395

8316

STAND

3D Transmitter (1002)

LCD DISPLAY

(1004)

26p

26p 26p26p 26p

26p 26p

8120

AMBILIGHT MODULE

(1070

)

AMBILIGHT MODULE

(1072

)

AMBILIGHT MODULE

(1073

)

AMBILIGHT MODULE

(1075

)

WIRING DIAGRAM 37" OSCAR

19050_082_110727.eps

110728

1F24 (B01C)

1. +3V3-1

2. USB-WIFI-DDn

3. USB-WIFI-DDp

4. GND

5. GND

6. GND

1M59 (B09A)

1. AMBI-SPI-CLK-OUT 15. GND_AL

2. GND 16. GND_AL

3. AMBI-SPI-SDO-OUT 17. GND_AL

4. AMBI-SPI-SDI-OUT_G1 18. GND_AL

5. V-AMBI 19. GND_AL

6. AMBI-PWM-CLK_B2 20. NC

7. GND 21. AMBI-POWER

8. AMBI-SPI-CS-OUTn_R2 22. AMBI-POWER

9. AMBI-LATCH1_G2 23. AMBI-POWER

10. V-AMBI 24. AMBI-POWER

11. AMBI-BLANK_R1 26. AMBI-POWER

12. AMBI-PROG_B1 26. AMBI-POWER

13. AMBI-LATCH2_DIS

14. AMBI-TEMP

1M99 (B03C)

1. GND_AL

2. +12V_AL

3. GND_AL

4. +12V_AL

1M95 (B03C)

1. +3V3-STANDBY

2. STANDBY- 1

3. GND

4. GND

5. +12VIN

6. +12VIN

7. +24V-AUDIO-POWER

8. GND-AUDIO

9. LAMP-ON-1

10. BACKLIGHT-PWM_BL-VS-1

11. BACKLIGHT-BOOST- 1

12. POWER-OK-1

13. +24V

14. GND_AL

1735 (B03]A)

1. LEFT-SPEAKER

2. GND-AUDIO

3. GND-AUDIO

4. RIGHT-SPEAKER

1M21 (B09A)

1. LIGHT-SENSOR 10. GND

2. LED-1 11. SDA-SET

3. LED-2 12. NC

4. GND 13. NC

5. KEYBOARD 14. GND

6. +3V3-STANDBY 15. NC

7. RC 16. 3D-LED

8. +5V 17. NC

9. SCL-SET 18. NC

1G51 (B06B)

1. +VDISP

2. +VDISP

3. +VDISP

4. +VDISP | | |

51. N.C.

Block Diagrams

EN 78Q551.2E LA 9.

2011-Sep-09

back to

div. table

Page 79

9-3 Wiring diagram Oscar 46"

Wifi (1042)

1G51 51p

1316

1319

15p

14p

CN1 CN2 CN3 CN4 CN5 CN6 CN7 50p

8408

INLET

1M83

1M84

2p3

1308

1M21

8120

Led & Control (1010)

11p

18p

1M20

11p

8801

8802

1M83

1M85

1M84

1M09

1M83

1M84

1M83

1M84

1M83

1M84

8581

8582

8152

8399

8395

1319

1316

1M95

14 p

12p14p

1M99

10p

1M09

14p

1M21

18p

1G51

51p

1735

1M59

1F24

1W35

1G51

1T51

15p

1F53

10p

1M99

8580

1M95

26p

8584

26p

8683

8121

SSB 3104 313 6539.x

(1011)

Bolt On

(1030)

51p51p

50p 50p 50p 50p 50p

Main Power Supply

(1050)

MAINS

SWITCH

Wifi

DC/DC

(1051)

26p

8309

8735

8151

8319

8316

12p

8684

AMBILIGHT MODULE

(1073)

AMBILIGHT MODULE

(1070)

AMBILIGHT MODULE

(1072)

AMBILIGHT MODULE

(1075)

LCD DISPLAY

(1004)

26p26p

26p 26p

Wifi

(1040)

LCD DISPLAY

(1004)

50p

8F53

STAND

WIRING DIAGRAM 46" OSCAR

ALD

(1041)

3D Transmitter

(1002)

19050_080_110725.eps

110728

1F24 (B01C)

1. +3V3-1

2. USB-WIFI-DDn

3. USB-WIFI-DDp

4. GND

5. GND

6. GND

1M59 (B09A)

1. AMBI-SPI-CLK-OUT 15. GND_AL

2. GND 16. GND_AL

3. AMBI-SPI-SDO-OUT 17. GND_AL

4. AMBI-SPI-SDI-OUT_G1 18. GND_AL

5. V-AMBI 19. GND_AL

6. AMBI-PWM-CLK_B2 20. NC

7. GND 21. AMBI-POWER

8. AMBI-SPI-CS-OUTn_R2 22. AMBI-POWER

9. AMBI-LATCH1_G2 23. AMBI-POWER

10. V-AMBI 24. AMBI-POWER

11. AMBI-BLANK_R1 26. AMBI-POWER

12. AMBI-PROG_B1 26. AMBI-POWER

13. AMBI-LATCH2_DIS

14. AMBI-TEMP

1M95 (B03C)

1. +3V3-STANDBY

2. STANDBY-1

3. GND

4. GND

5. +12VIN

6. +12VIN

7. +24V-AUDIO-POWER

8. GND-AUDIO

9. LAMP-ON-1

10. BACKLIGHT-PWM_BL-VS-1

11. BACKLIGHT-BOOST- 1

12. POWER-OK-1

13. +24V

14. GND_AL

1735 (B03]A)

1. LEFT-SPEAKER

2. GND-AUDIO

3. GND-AUDIO

4. RIGHT-SPEAKER

1M21 (B09A)

1. LIGHT-SENSOR 10. GND

2. LED-1 11. SDA-SET

3. LED-2 12. NC

4. GND 13. NC

5. KEYBOARD 14. GND

6. +3V3-STANDBY 15. NC

7. RC 16. 3D-LED

8. +5V 17. NC

9. SCL-SET 18. NC

1G51 (B06B)

1. +VDISP

2. +VDISP

3. +VDISP

4. +VDISP | | |

51. N.C.

Block Diagrams

EN 79Q551.2E LA 9.

2011-Sep-09

back to

div. table

Page 80

9-4 Wiring diagram Oscar 52"

Wifi (1042)

1G51 51p

1316

I2S

8685

1319

CN1 CN2 CN3

CN4

CN5

CN6

CN7

INLET

1M95

1M99

14p

10p

1M09

2p3

1308

1M21

8120

Led & Control(1010)

1M20

8801

8802

1M83

1M85

1M84

1M09

8309

1M83

1M84

1M83

1M84

8684

0 I

8581

8582

8686

8687

8683

CN8

1M83

1M84

1M83

1M84

1M83

1M84

1M83

1M84

1M83

1M84

1M95 14p

1M21

18p

1G51

51p

1735

1M59

1F24

1G51

1T51

15p

1F53

10p

1M99

1319

1316

12p 14p

8F53

26p

MAINS

SWITCH

Main Power Supply

(1050)

Bolt On (1030)

51p

LCD DISPLAY (1004)

STAND

Wifi (1040)

11p

18p

3DTransmitter (1002)

Wifi (1041)

SSB 3104 313 6539.x

(1011)

26p

DC/DC (1051)

ALD

26p

LCD DISPLAY (1004)

15p14p

50p 50p 50p 50p 50p 50p

12p

50p 50p

AMBILIGHT MODULE

(1076)

AMBILIGHTMODULE

(1075)

AMBILIGHT MODULE

(1073)

AMBILIGHTMODULE

(1074)

AMBILIGHTMODULE (1072)

AMBILIGHT MODULE (1071)

AMBILIGHTMODULE (1070

26p26p

26p

26p 26p 26p 26p

26p

26p26p26p26p

26p

8408

8735

8121

8580

8319

8M99

8316

8324

8395

8G51

8T51

8584

1W35

WIRING DIAGRAM 52" OSCAR

1F24 (B01C)

1. +3V3-1

2. USB-WIFI-DDn

3. USB-WIFI-DDp

4. GND

5. GND

6. GND

1M59 (B09A)

1. AMBI-SPI-CLK-OUT 15. GND_AL

2. GND 16. GND_AL

3. AMBI-SPI-SDO-OUT 17. GND_AL

4. AMBI-SPI-SDI-OUT_G1 18. GND_AL

5. V-AMBI 19. GND_AL

6. AMBI-PWM-CLK_B2 20. NC

7. GND 21. AMBI-POWER

8. AMBI-SPI-CS-OUTn_R2 22. AMBI-POWER

9. AMBI-LATCH1_G2 23. AMBI-POWER

10. V-AMBI 24. AMBI-POWER

11. AMBI-BLANK_R1 26. AMBI-POWER

12. AMBI-PROG_B1 26. AMBI-POWER

13. AMBI-LATCH2_DIS

14. AMBI-TEMP

1M95 (B03C)

1. +3V3-STANDBY

2. STANDBY-1

3. GND

4. GND

5. +12VIN

6. +12VIN

7. +24V-AUDIO-POWER

8. GND-AUDIO

9. LAMP-ON-1

10. BACKLIGHT-PWM_BL-VS-1

11. BACKLIGHT-BOOST-1

12. POWER-OK-1

13. +24V

14. GND_AL

1735 (B03]A)

1. LEFT-SPEAKER

2. GND-AUDIO

3. GND-AUDIO

4. RIGHT-SPEAKER

1M21 (B09A)

1. LIGHT-SENSOR 10. GND

2. LED-1 11. SDA-SET

3. LED-2 12. NC

4. GND 13. NC

5. KEYBOARD 14. GND

6. +3V3-STANDBY 15. NC

7. RC 16. 3D-LED

8. +5V 17. NC

9. SCL-SET 18. NC

1G51 (B06B)

1. +VDISP

2. +VDISP

3. +VDISP

4. +VDISP | | |

51. N.C.

19050_092_110825.eps

110907

Block Diagrams

EN 80Q551.2E LA 9.

2011-Sep-09

back to

div. table

Page 81

9-5 Wiring diagram Oscar Platinum 58"

WIRING DIAGRAM 58" OSCAR PLATINUM

19050_088_110727.eps

110728

1F24 (B01C)

1. +3V3-1

2. USB-WIFI-DDn

3. USB-WIFI-DDp

4. GND

5. GND

6. GND

1M59 (B09A)

1. AMBI-SPI-CLK-OUT 15. GND_AL

2. GND 16. GND_AL

3. AMBI-SPI-SDO-OUT 17. GND_AL

4. AMBI-SPI-SDI-OUT_G1 18. GND_AL

5. V-AMBI 19. GND_AL

6. AMBI-PWM-CLK_B2 20. NC

7. GND 21. AMBI-POWER

8. AMBI-SPI-CS-OUTn_R2 22. AMBI-POWER

9. AMBI-LATCH1_G2 23. AMBI-POWER

10. V-AMBI 24. AMBI-POWER

11. AMBI-BLANK_R1 26. AMBI-POWER

12. AMBI-PROG_B1 26. AMBI-POWER

13. AMBI-LATCH2_DIS

14. AMBI-TEMP

1M99 (B03C)

1. GND_AL

2. +12V_AL

3. GND_AL

4. +12V_AL

1M95 (B03C)

1. +3V3-STANDBY

2. STANDBY-1

3. GND

4. GND

5. +12VIN

6. +12VIN

7. +24V-AUDIO-POWER

8. GND-AUDIO

9. LAMP-ON-1

10. BACKLIGHT-PWM_BL-VS-1

11. BACKLIGHT-BOOST- 1

12. POWER-OK-1

13. +24V

14. GND_AL

1735 (B03A)

1. LEFT-SPEAKER

2. GND-AUDIO

3. GND-AUDIO

4. RIGHT-SPEAKER

1M21 (B09A)

1. LIGHT-SENSOR 10. GND

2. LED-1 11. SDA-SET

3. LED-2 12. NC

4. GND 13. NC

5. KEYBOARD 14. GND

6. +3V3-STANDBY 15. NC

7. RC 16. 3D-LED

8. +5V 17. NC

9. SCL-SET 18. NC

(5211)

(5212)

1G51

1MP1

1M83

1M84

INLET

8584

8685

8684

1316

I2S

8683

1319

14p 14p

CN1 CN2

CN3

CN4

CN5

50p

Tweeter

1L12

Woofer R

1M83

1M84

1M83

1M84

2p3

1319

1308

1316

1MP1

1M09

14p 14p

8319

8323

15p

1316

1319

14p

1316

1319

CN1 CN2 CN3

CN4

1L11

25p

1322

8316

8121

1M95

11p

1M99

1M21

8120

Led & Control (1010)

1M20

1M83

1M84

1M83

1M84

1M83

1M84

1M83

1M84

8581

8686

1N95

11p

1N99

1M95

1M99

10p

14p

1N09

8687

1M95

1M99

14 p

1M21

18p

1G51

51p

1735

1M59

1F24

1G51

1T51

15p

1F53

10p

1M99

Wifi (1042)

Woofer L

8T51

8M95

8M99

1M09

8M09

26p

MAINS

SWITCH

8408

Main Power Supply

(1050)

8322

LCD DISPLAY

(1004)

50p 50p 50p 50p

14p

14p 14p

25p

LCD DISPLAY

(1004)

50p 50p 50p 50p

LCD DISPLAY

(1004)

8801

8802

8301

8321

8320

Wifi

(1040)

Wifi

(1041)

3D Transmitter (1002)

11p

18p

11p

SSB 3104 313 6539.x

(1011)

51p

Bolt On

(1030)

DC/DC

(1051)

51p

ALD

8G51

8N95

8N99

8N09

8735

AMBILIGHT MODULE

(1076)

AMBILIGHT MODULE

(1075)

AMBILIGHT MODULE

(1072)

AMBILIGHT MODULE

(1071)

AMBILIGHT MODULE

(1070)

AMBILIGHT MODULE

(1073)

AMBILIGHT MODULE

(1074)

26p

26p 26p 26p 26p 26p 26p

26p 26p

26p

1G51 (B06B)

1. +VDISP

2. +VDISP

3. +VDISP

4. +VDISP | | |

51. N.C.

Block Diagrams

EN 81Q551.2E LA 9.

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div. table

2011-Sep-09

Page 82

9-6 Wiring diagram Cannes 40 - 46"

Wifi (1042)

8120

INLET

8735

1M83

1M84

1M83

1M84

1G51

51p

1M21

8121

Led & Control (1010)

1M20

1319

1316

1M09

1M95

1M99

14p

10p

1M54

10p 12p

8584

From SSBTo TCon

1W35

1G51

1T51

10p

1M99

1M54

8M54

8M99

8T51

8309

8G51

26p

14p

1M95

1M99

1M59

1F24

1735

51p

1G51

1M21

18p

SSB 3104 313 6539.x

(1011)

1308

Main Power Supply

(1050)

2p3

MAINS

SWITCH

8408

Bolt On

(1030)

51p

LCD DISPLAY

(1004)

STAND

LCD DISPLAY

(1004)

AMBILIGHT MODULE

(1073)

AMBILIGHT MODULE

(1075)

26p

Wifi

(1040)

Wifi

(1041)

3D Transmitter (1002)

11p

18p

11p

8802

8801

8583

8395

8735

WIRING DIAGRAM 40”- 46" CANNES

19050_090_110728.eps

110728

1F24 (B01C)

1. +3V3-1

2. USB-WIFI-DDn

3. USB-WIFI-DDp

4. GND

5. GND

6. GND

1M59 (B09A)

1. AMBI-SPI-CLK-OUT 15. GND_AL

2. GND 16. GND_AL

3. AMBI-SPI-SDO-OUT 17. GND_AL

4. AMBI-SPI-SDI-OUT_G1 18. GND_AL

5. V-AMBI 19. GND_AL

6. AMBI-PWM-CLK_B2 20. NC

7. GND 21. AMBI-POWER

8. AMBI-SPI-CS-OUTn_R2 22. AMBI-POWER

9. AMBI-LATCH1_G2 23. AMBI-POWER

10. V-AMBI 24. AMBI-POWER

11. AMBI-BLANK_R1 26. AMBI-POWER

12. AMBI-PROG_B1 26. AMBI-POWER

13. AMBI-LATCH2_DIS

14. AMBI-TEMP

1M99 (B03C)

1. GND_AL

2. +12V_AL

3. GND_AL

4. +12V_AL

1M95 (B03C)

1. +3V3-STANDBY

2. STANDBY-1

3. GND

4. GND

5. +12VIN

6. +12VIN

7. +24V-AUDIO-POWER

8. GND-AUDIO

9. LAMP-ON-1

10. BACKLIGHT-PWM_BL-VS-1

11. BACKLIGHT-BOOST- 1

12. POWER-OK-1

13. +24V

14. GND_AL

1735 (B03]A)

1. LEFT-SPEAKER

2. GND-AUDIO

3. GND-AUDIO

4. RIGHT-SPEAKER

1M21 (B09A)

1. LIGHT-SENSOR 10. GND

2. LED-1 11. SDA-SET

3. LED-2 12. NC

4. GND 13. NC

5. KEYBOARD 14. GND

6. +3V3-STANDBY 15. NC

7. RC 16. 3D-LED

8. +5V 17. NC

9. SCL-SET 18. NC

1G51 (B06B)

1. +VDISP

2. +VDISP

3. +VDISP

4. +VDISP | | |

51. N.C.

Block Diagrams

EN 82Q551.2E LA 9.

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2011-Sep-09

div. table

Page 83

9-7 Wiring diagram Sundance 50"

Woofe (5211)r

INLET

30 p 30 p

8584

M0 9

1M83

1M84

1M83

41p

1G50

51p

1M9 5

1M99

14p

10p

2p3

Led & Control (1010)

1M20

11p

1319

14p

1308

8149

1M95

1M99

14p

1M21

18p

1D38

1G51

51p

1735

1M59

1F24

1G51

1M99

10p

1M21

1M20

8120

1T50

1T51

1M84

1G51

Wifi (1042)

MAINS

SWITCH

11p

51p

41p

SSB 3104 313 6539.x

(1011)

Bolt On

(1030)

Main Power Supply

(1050)

LCD DISPLAY

(1004)

LCD DISPLAY

(1004)

8151

8150

18p

8121

8583

8324

8319

8408

AMBILIGHT MODULE

(1076)

AMBIL

GHT MODULE

(1074)

8399

8395

8801

8802

8M99

Wifi

(1040)

Wifi

(1041)

26p

WIRING DIAGRAM 50" SUNDANCE

19050_081_110726.eps

110728

1F24 (B01C)

1. +3V3-1

2. USB-WIFI-DDn

3. USB-WIFI-DDp

4. GND

5. GND

6. GND

1M59 (B09A)

1. AMBI-SPI-CLK-OUT 15. GND_AL

2. GND 16. GND_AL

3. AMBI-SPI-SDO-OUT 17. GND_AL

4. AMBI-SPI-SDI-OUT_G1 18. GND_AL

5. V-AMBI 19. GND_AL

6. AMBI-PWM-CLK_B2 20. NC

7. GND 21. AMBI-POWER

8. AMBI-SPI-CS-OUTn_R2 22. AMBI-POWER

9. AMBI-LATCH1_G2 23. AMBI-POWER

10. V-AMBI 24. AMBI-POWER

11. AMBI-BLANK_R1 26. AMBI-POWER

12. AMBI-PROG_B1 26. AMBI-POWER

13. AMBI-LATCH2_DIS

14. AMBI-TEMP

1M99 (B03C)

1. GND_AL

2. +12V_AL

3. GND_AL

4. +12V_AL

1M95 (B03C)

1. +3V3-STANDBY

2. STANDBY-1

3. GND

4. GND

5. +12VIN

6. +12VIN

7. +24V-AUDIO-POWER

8. GND-AUDIO

9. LAMP-ON-1

10. BACKLIGHT-PWM_BL-VS-1

11. BACKLIGHT-BOOST- 1

12. POWER-OK-1

13. +24V

14. GND_AL

1D38 (B03A)

1. LEFT-SPEAKER

2. GND-AUDIO

3. RIGHT-SPEAKER

1735 (B03]A)

1. LEFT-SPEAKER

2. GND-AUDIO

3. GND-AUDIO

4. RIGHT-SPEAKER

1G51 (B06B)

1. +VDISP

2. +VDISP

3. +VDISP

4. +VDISP | | |

51. N.C.

1M21 (B09A)

1. LIGHT-SENSOR 10. GND

2. LED-1 11. SDA-SET

3. LED-2 12. NC

4. GND 13. NC

5. KEYBOARD 14. GND

6. +3V3-STANDBY 15. NC

7. RC 16. 3D-LED

8. +5V 17. NC

9. SCL-SET 18. NC

Tweeter R (5221)

Tweeter L (5221)

Block Diagrams

EN 83Q551.2E LA 9.

2011-Sep-09

back to

div. table

Page 84

9-8 Block Diagram Video

VIDEO

COMMON INTERFACE

B01A

1R01

1R10

RF_AGC IF-OUT1

IF-OUT2

1P05

1 3 4 6 7

9 10 12

1P04

9 10 12

1P03

9 10 12

1P02

9 10 12

+3V3-HDMI

16M

DRX2+

DRX2-

DRX1+

DRX1-

DRX0+

DRX0-

DRXC+

DRXC-

ARX2+

ARX2-

ARX1+

ARX1-

ARX0+

ARX0-

ARXC+

ARXC-

BRX2+

BRX2-

BRX1+

BRX1-

BRX0+

BRX0-

BRXC+

BRXC-

CRX2+

CRX2-

CRX1+

CRX1-

CRX0+

CRX0-

CRXC+

CRXC-

7R02 STV6110A

DVB-S

TUNER

RF-AGC

TUN-IF-P

TUN-IF-N

9,27,64

B07A

B01F

RF IN

B01H

DVBS-FE

SAT IN

TUNER

1T01 TH2627

MAIN HYBRID

TUNER

HDMI

18 2

HDMI SIDE

CONNECTOR

18 2

HDMI 3

CONNECTOR

18 2

HDMI 2

CONNECTOR

18 2

HDMI 1

CONNECTOR

21 20 32 18 19

B02E

CONTROL

B04D

7EC1 SII9287BC

26 25 24 23 22 21 20 19

72 71 70 69 68 67 66 65

8 7 6 5 4 3 2 1

18 17 16 15 14 13 12 11

VCC33

XTAL

AGC

5F73

SELECT-SAW

HDMI

RXD

HDMI

SWITCH

RXA

RXB

RXC

TXC_P TXC_N

TX0_P TX0_N TX1_P TX1_N TX2_P TX2_N

7R01 STV0903BAC

7 8

122

12 11

5F70

7F70

62 63 60 61 58 59 56

DVB-S

CHANNEL

DECODER

2F90

B04A

B04B

78 75

TS-DVBS-CLOCK

74 73

+5V-TUN-PIN

1F75

SAW 36MHZ17

ANALOGUE EXTERNALS A

EXT 1

B01I

SCART1

VGA

CONNECTOR

ANALOGUE EXTERNALS B

1E04

EXT 3

1E08

1E03

Block Diagrams

1P00

17 18 51 52

PCMCIA

CONDITIONAL

ACCESS

TS-DVBS-VALID

TS-DVBS-SOP

TS-DVBS-DATA

B10A

ONLY FOR TV-SETS WITH DVB-S

7F75 UPC3221GV

VCC

2F74

AGC AMPLIFIER

2F78

AGC CONTROL

PNX-IF-AGC

1E01

15 11 AE13

7E05EF7E06

1E05

1 2

3 13 14

OUT

7E09-1

IF-P-DVBT2

AV1-CVBS

AV1-STATUS

H-SYNC-VGA V-SYNC-VGA

HDMIA-RXC+

HDMIA-RXC-

HDMIA-RX0+

HDMIA-RX0-

HDMIA-RX1+

HDMIA-RX1-

HDMIA-RX2+

HDMIA-RX2-

DVBT2

7FJ1

DVBT2-IFN DVBT2-IFP

IF-AGC

AV1-R AV1-G

AVI-B

AV1-BLK

R-VGA G-VGA B-VGA

AV3-PR

AV3-Y

AV3-PB

68P

MDO(0-7)

7FJ0 CXD2820R

DECODER

49 50 64

3F79-1

3F79-4

B02G

CONTROL

B02G

CONTROL

+5VCA

7F01 74LVC245APW

BUFFER

CA-MDI(0-7)

9R03-1

9R03-2

9R04

9R03-4

DVBT2

CHANNEL

3 5 7

ONLY FOR TV-SETS WITH DVB-T2

BANDPASS

FILTER

TS-FE-VALID

TS-FE-SOP

TS-FE-CLOCK

TS-FE-DATA

TS-FE-VALID

TS-FE-SOP

TS-FE-CLOCK

TS-FE-DATA

PNX-IF-P

PNX-IF-N

CVBS-MON-OUT1

+3V3

CA-MDO(0-7)

+3V3

EN 84Q551.2E LA 9.

3S0W

B02

7S00 PNX85537EB

B02A

MD0

MDI

R23

TNR_SER1_MIVAL

R22

TNR_SER1_SOP

T22

TNR_SER1_MICLK

T21

TNR_SER1_DATA

B02I

AE12

TUNER_P

AF12

TUNER_N

AD12

IF_AGC

AC13

AV1_R AV1_G

AD13

AV1_B

AB15

CVBS_Y1

AF11

CVBS1_OUT

AF16

VGA_R

AD16

VGA_G

AE16

VGA_B

AB18

HSYNC_IN

AC18

VSYNC_IN

AC15

PR_R_C1

AE15

Y_G1

AD15

PB_B1

B02C

W25

RXC_A_P

W26

RXC_A_N

V25

RX2_A_P

V26

RX2_A_N

U25

RX1_A_P

U26

RX1_A_N

T25

RX0_A_P

T26

RX0_A_N

W24

RREF

PNX85500

VIDEO STREAM

ANALOG VIDEO

HDMI_DV

VIDEO OUT - LVDS

B06B

LVD S

B02F

LOUT1

LOUT2

LOUT3

LOUT4

USB HUB

B01C

CONROL

B02E

R26

USB_DN

R25

USB_DP

FLASH

B02A

PNX85537

XIO_D

B02B

NAND_RDY1

NAND_WP_

MEMORY

NAND_CE1

VREF_1 VREF_2

E21 F21 A21

A2 V1

USB-DM

B01B

XIO-D(00-07)

NAND-CE1n

NAND-RDY1n

NAND-WPn

DDR2-VREF-CTRL2 DDR2-VREF-CTRL3

B05A

D(0-7)

USB-DP

FLASH

DDR

7B00 H5PS1G83E

SDRAM 128Mx8

VDDL

7F20 H27U4G8F2DTR

NAND

FLASH

9 7

VCC

12,37

VREF

D(8-15)

+3V3

1FL5

7B01 H5PS1G83E

SDRAM 128Mx8

VREF

VDDL

PX1

PX2

PX3

PX4

9F26

7FL5 CY7C65631

17 18

24M

D(16-23)

USB HUB

7B02 H5PS1G83E

B03C B03C

B02G

B09A

B02G

9F25

5 6

13 14

RESET-USBn

SDRAM 128Mx8

VREF

VDDL

USB-WIFI-DDn

USB-WIFI-DDP

BACKLIGHT-PWM_BL-VS

LAMP-ON

CTRL-DISP

3D-LED

SPLASH-ON

+VDISP

ONLY FOR SSB 3104 313 6538.x

USB1-DM

USB1-DP

USB2-DM

USB2-DP

+5V

B02G

DDR2-D(0-31)

7B03 H5PS1G83E

D(24-31)

SDRAM 128Mx8

VREF

VDDL

A1 E2A1 E2A1 E2A1 E2

DDR2-A(0-14)

N.C.

I2C

N.C.

+5V-USB1

1P08

+5V-USB2

1P07

1F24

1 2 3 4 5

+1V8 DDR2-VREF-DDR

1G51

51 50 49 48 47 46 45 42

TO DISPLAY

BOLT-ON MODULE

4 3 2 1

1G50

TO DISPLAY

3 2 1

1 2 3 4

B11C

CONNECTOR

+3V3-1

TO WIFI MODULETO WIFI MODULE

4321

SIDE USB

4321

SIDE USB

CONNECTORS

1H24

1 2 3 4 5

SSB 3104 313 6538.x

19050_006_110415.eps

110805

2011-Sep-09

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div. table

Page 85

9-9 Block Diagram Audio

AUDIO

COMMON INTERFACE

B01A

1R01

1R10

IF-OUT1

IF-OUT2

18 2

7R02 STV6110A

16M

1P05

1 3 4 6 7

9 10 12

1P04

9 10 12

1P03

9 10 12

+3V3-HDMI

1P02

9 10 12

DVB-S

TUNER

TUN-IF-P

TUN-IF-N

DRX2+

DRX2-

DRX1+

DRX1-

DRX0+

DRX0-

DRXC+

DRXC-

ARX2+

ARX2-

ARX1+

ARX1-

ARX0+

ARX0-

ARXC+

ARXC-

BRX2+

BRX2-

BRX1+

BRX1-

BRX0+

BRX0-

BRXC+

BRXC-

CRX2+

CRX2-

CRX1+

CRX1-

CRX0+

CRX0-

CRXC+

CRXC-

CONTROL

B07A

B01F

RF IN

B01H

DVBS-FE

SAT IN

TUNER

1T01 TH2627

MAIN HYBRID

TUNER

HDMI

HDMI SIDE

CONNECTOR

HDMI 3

CONNECTOR

HDMI 2

CONNECTOR

HDMI 1

CONNECTOR

7R01 STV0903BAC

B02E

21 20 32 18 19

XTAL

AGC

5F73

SELECT-SAW

B04D

7EC1 SII9287BCNU

26 25 24 23 22 21 20 19

IP IM

RXD

HDMI

7 8

122

12 11

DVB-S

CHANNEL

DECODER

2F90

5F70

7F70

SAW 36MHZ17

TS-DVBS-VALID

TS-DVBS-SOP

TS-DVBS-CLOCK

TS-DVBS-DATA

ONLY FOR TV-SETS WITH DVB-S

+5V-TUN-PIN

1F75

2F74

2F78

ANALOGUE EXTERNALS A

B04A

1E01-1

SCART1

HDMI

SWITCH

72 71 70 69 68

RXA 67 66 65

8 7 6 5

RXB

4 3 2 1

9,27,64

VCC33

18 17 16 15

RXC

14 13 12 11

ARC-eHDMI+ eHDMI+

TXC_P

TXC_N

TX0_P TX0_N TX1_P TX1_N TX2_P TX2_N

62 63 60 61 58 59 56

ANALOGUE EXTERNALS B

B04B

AUDIO IN

L+R

VGA (OR DVI)

AUDIO

1E10

DIGITAL

AUDIO

OUT

5EC2

1E08

1E09

Block Diagrams

7F75 UPC3221GV

VCC

AGC AMPLIFIER

AGC CONTROL

PNX-IF-AGC

AP-SCART-OUT-L

AP-SCART-OUT-R

2 3

+3V3

1 3

PCMCIA

CONDITIONAL

ACCESS

OUT

3F79-1

3F79-4

B10A

3EA7-1

3EA7-4

7E01

A-PLOP

SPDIF-OPT

1P00

17 18 51 52

DVBT2

DVBT2-IFN

DVBT2-IFP

IF-P-DVBT2

HDMIA-RXC+

HDMIA-RXC-

HDMIA-RX0+

HDMIA-RX0-

HDMIA-RX1+

HDMIA-RX1-

HDMIA-RX2+

HDMIA-RX2-

68P

A-PLOP

MDO(0-7)

9R03-2

9R03-4

7FJ0 CXD2820R

DVBT2

CHANNEL

DECODER

BANDPASS

AUDIO-OUT-L

AUDIO-OUT-R

B04E

+5VCA

7F01 74LVC245APW

BUFFER

CA-MDI(0-7)

9R03-1

TS-FE-VALID

TS-FE-SOP

9R04

TS-FE-CLOCK

TS-FE-DATA

TS-FE-VALID

TS-FE-SOP

TS-FE-CLOCK

TS-FE-DATA

ONLY FOR TV-SETS WITH DVB-T2

PNX-IF-P

FILTER

PNX85500: AUDIO

B02D

7S05

173

AUDIO-IN1-L

AUDIO-IN1-R

AUDIO-IN3-L

AUDIO-IN3-R

AUDIO-IN4-L

AUDIO-IN4-R

7S09

+3V3

2 1 4

PNX-IF-N

+3V3

CA-MDO(0-7)

ADAC(5)

ADAC(6)

SPDIF-OUT-PNX

SEL-HDMI-ARC

3S0W

+3V3

EN 85Q551.2E LA 9.

B02

7S00 PNX85537EB

B02A

MD0

MDI

R23

TNR_SER1_MIVAL

R22

TNR_SER1_SOP

T22

TNR_SER1_MICLK

T21

TNR_SER1_DATA

B02I

AE12

TUNER_P

AF12

TUNER_N

AD12

IF_AGC

B02D

AE6

ADAC_5

AF6

ADAC_6

AE10

AIN1_L

AF10

AIN1_R

AE9

AIN3_L

AF9

AIN3_R

AD9

AIN4_L

AC9

AIN4_R

AF5

SPDIF_OUT

B02G

AF18

P0_4

B02C

W25

RXC_A_P

W26

RXC_A_N

V25

RX2_A_P

V26

RX2_A_N

U25

RX1_A_P

U26

RX1_A_N

T25

RX0_A_P

T26

RX0_A_N

W24

RREF

PNX85500

VIDEO STREAM

ANALOG VIDEO

AUDIO

STANDBY

HDMI_DV

PNX85500: AUDIO

B02D

AUDIO

B02D

B04E

B01C

B01B

B05A

7B00 H5PS1G83EFR

D(0-7)

SDRAM 128Mx8

VDDL

DDR2-VREF-CTRL2 DDR2-VREF-CTRL3

ADAC(1)

ADAC(2)

AUDIO-MUTE-UP

B03C

HEADPHONE

RESET-AUDIO

ADAC(3)

ADAC(4)

USB HUB

USB-DM

USB-DP

FLASH

7F20 H27U4G8F2DTR-BC

NAND

FLASH

9 7

DDR

VREF

DETECT2

VCC

D(8-15)

AD7

ADAC_1

AE7

ADAC_2

STANDBY

B02G

CONROL

B02E

FLASH

B02A

PNX85537

NAND_RDY1

NAND_WP_

MEMORY

B02B

PO_7

PO_6

ADAC3

ADAC4

USB_DN USB_DP

XIO_D

NAND_CE1

VREF_1 VREF_2

AC19

AB19

AF7

AD6

R26 R25

XIO-D(00-07)

NAND-CE1n

E21

NAND-RDY1n

F21

NAND-WPn

A21

A2 V1

7S05 LM324P

21,37

7B01 H5PS1G83EFR

SDRAM 128Mx8

B03A

7D11

MAINS SWITCH

DETECT

+3V3

VREF

VDDL

AUDIO

+AUDIO-L

-AUDIO-R

7D15

A-PLOP

A-STBY

7EE0-1 7EE0-2

7B02 H5PS1G83EFR

D(16-23)

SDRAM 128Mx8

A-PLOP

VREF

VDDL

1FL5

B04E

17 18

24M 22

512

7D10 TPA3123D2PWP

CLASS D

POWER

AMPLIFIER

PVCC_L

IN-L

PVCC_R

IN-R

MUTE

OUT-R

A-PLOP

7EE1 TPA6111A2DGN

HEADPHONE

AMPLIFIER

SHUTDOWN

IN-1

IN-2

9F26

9F25

7FL5 CY7C65631

USB HUB

7B03 H5PS1G83EFR

D(24-31)

SDRAM 128Mx8

VDDL

A1 E2A1 E2A1E2A1E2

OUT-L

B03A B04A

VO_1 VO_2

VDD

RES

9 10 5 6

USB-WIFI-DDn

USB-WIFI-DDP

RESET-USBn

DDR2-D(0-31)

VREF

DDR2-A(0-14)

5D07

1,3

5D08

10,12

LEFT-SPEAKER

RIGHT-SPEAKER

7D03

STANDBY &

PROTECTION

1 7

+3V3

USB1-DM

USB1-DP

USB2-DM

USB2-DP

B02G

+1V8 DDR2-VREF-DDR

+24V-AUDIO-POWER

B01J

AMP1 AMP2

+5V-USB1

+5V-USB2

+5V

1F24

1 2 3 4 5

1735

TO SPEAKERS

(IN STAND)

1D38

5D03

2 3

TO WOOFER

RES

TEMP SENSOR + HEADPHONE

1328

2 3

1P08

1 2 3 4

1P07

1 2 3 4

4321

B11B

HEADPHONE

OUT 3.5mm

USB 1 SIDE

CONNECTOR

USB 2 SIDE

CONNECTOR

CONNECTORS

+5V

1H24

1 2 3 4 5

TO WIFI MODULETO WIFI MODULE

SSB 3104 313 6538.x

2011-Sep-09

back to

div. table

19050_007_110415.eps

110728

Page 86

9-10 Block Diagram Control & Clock Signals

B04D

HDMI

B01D

SD-CARD

B02A

PNX85500

B06C

AMBILIGHT CPLD

B04C

ETHERNET + SERVICE

B01A

COMMON INTERFACE

B09A

CONNECTORS COMP

B01B

FLASH

B03C

DC / DC

B05A

DDR

B01E

PNX85500-CONTROL

B04C

ETHERNET + SERVICE

B02E

PNX85500: MIPS

B01C

USB HUB

B03C

DC / DC

B02G

PNX85500: STANDBY CONTROLLER

B07A

DVBS-FE

B02G

PNX85500: STANDBY CONTROLLER

CONTROL + CLOCK SIGNALS

B03C

DC/DC

B11B

CONNECTORS

B10A

DVBT2

B09A

CONNECTORS COMP

B11B

CONNECTORS

B11B

CONNECTORS

B06B

VIDEO OUR - LVDS

B11A

FPGA-BACKLIGHT DIMMING

RES

VIDEO STREAM

B02A

B02E

ETHERNET

CA-A(00-14)

1H95

LED1

AD26

AE26

AA22

DETECT2

AA26

AF19

RESET-STBYn

4x HDMI

CONNECTOR

AB22

RESET-SYSTEMn

AD21

ENABLE-3V3n

PNX85537

7S00 PNX85537EB

SD-CARD

CONNECTOR

AC25

LED2

1S02

54M

AF17

AE17

CONTROL

B02E

STANDBY

B02G

HDMI_DV

B02C

AD22

AV1-BLK

AF20

STANDBY

AD23

KEYBOARD

3D-LED

LIGHT-SENSOR

AD18

AC19

RESET-USBn

AB19

RESET-AUDIO

AF1

SENSE+1V1

AE25

AV1-STATUS

BACKLIGHT-PWM_BL-VS-1

BACKLIGHT-BOOST-1

B01C

AC21

POWER-OK

B02G

B01F

B02E

B01F

B03B

7S20 NCP303LSN28G

INP

OUTP

+3V3-STANDBY

GND

B02E

B02H

POWER

7EC1 SII9187ACNU SII9287BCNU

HDMI

SWITCH

B04A

1P00

PCMCIA

CONDITIONAL

ACCESS

P3_0 P3_1 P1_7

P6_4

P2_2

P2_7

P1_1

P2_6

P0_6

P2_3

VDD_1V1

XTAL_IN

XTAL_OUT

P5_1

P5_0

P3_2 P3_3 P3_5

CADC_2

RESET_IN

P1_2

W24

RREF

PWM_1

PWM_0

7F02 7F03

7F04 7F05

7F01

TO POWER SUPPLY

B04A

COMMON INTERFACE

+3V3-STANDBY

+5V

B04E

B03C

SDM

SPI-PROG

AF22

AB20

FF04

FF29

19050_019_110419.eps

110805

RXD-UP TXD-UP

Y23 Y24

UART

SERVICE

CONNECTOR

AE21 AF21

RXD1-MIPS TXD1-MIPS

AD23

P5_0

LED-2

LED-1

1M21

7U43

ARX-HOTPLUG

1E06

P2_0

AC20

LCD-PWR-ONn

B03H

RESET-STBYn

AUDIO-MUTE-UP

B03A

P0_7

RESET-DVBS

AA15

N5 N4

SENSE+1V2

B03D

VDDA_1V2

AA18

RESET-DVBS

B07A

P0_1

AE18

RESET-ETHERNETn

B04C

P0_3

AF18

SEL-HDMI-ARC

B02D

B06B

P0_4

AE20

LAMP-ON

SPLASH-ON

STANDBY

POWER-OK

LAMP-ON

V23

BOOST-PWM

GPIO_10

B09A

BACKLIGHT-BOOST

1M95

31 BRX-HOTPLUG CRX-HOTPLUG

41 DRX-HOTPLUG

PCEC-HDMI CEC-HDMI

1P05-19

1P02-19 1P03-19 1P04-19

TO PIN:

1P02-13 1P03-13 1P04-13 1P05-13

FLASH

B02A

7F20 H27U4G8F2DTR

NAND

FLASH

12,37

+3V3

VCC

MDI

1P09

SDIO-DAT3

CC_DAT3

2 W6

SDIO-CLK

SDIO-CMD

CMD

AA2

ETH-TXCLK

RXCLK

10 U6

SDIO-CDn

SDCD

AA3

ETH-RXCLK

TXCLK

12 V6

SDIO-WP

SDWP

RXD TXD

CLK

SDIO-DAT0

DAT_0

SDIO-DAT1

DAT_1

SDIO-DAT2

DAT_2

DDR-CLK_N DDR-CLK_P

SPI_CLK

SPI_CSB

SPI_SDO

SPI_SDI

P6_5

7F52 M25P05-AVMN6P

FLASH

512K

+3V3-STANDBY

VCC

PNX-SPI-CLK

AF24

PNX-SPI-WPn

AE22

PNX-SPI-CSBn

AF23

PNX-SPI-SDO

AE23

PNX-SPI-SDI

AF25

CONTROL

+3V3-STANDBY

+12V

ENABLE-1V8

ENABLE-3V3-5V

DETECT2

XIO-D(00-07)

CA-MDI(0-7)

MDO

CA-MDO(0-7)MDO(0-7)

ETH-TXD

ETH-RXD

XIO_A

XIO_D

XIO-A(0-15)

CA-D(0-7)

MEMORY

B02B

F8 E8F8 E8F8 E8F8 E8

SDRAM 128Mx8

7B01 H5PS1G83EFR

SDRAM

128Mx8

7B02 H5PS1G83EFR

SDRAM 128Mx8

7B03 H5PS1G83EFR

CLK_N

CLK_P

GPI0_2

V22

GPI0_7

GPI0_3

SDRAM 128Mx8

7B00 H5PS1G83EFR

DDR2-D(0-31)

D(24-31)

D(16-23)

D(8-15)

D(0-7)

DDR2-A(0-13)

B06C

BL_PWM

BACKLIGHT-PWM

AD5

BACKLIGHT-PWM_BL-VS

RESET-SYSTEMn

AE4

B01K B02G

RESET_SYS

GPI0_11

SELECT-SAW

U23

B01F

CLK_54_OUT

AC5

PXCLK54

B02G

+3V3

3S0W

TO IR / LED BOARD AND

KEYBOARD CONTROL

9U41

9CH0

B03E B03B B03D B02G B03A

7EC0

7R01 STV0903BAC

MULTI

STANDARD DEMODULATOR FOR SAT DIG TV

7R02 STV6110A

SATELLITE

TUNER

122

XTAL

SENSE+1V0-DVBS

T21

TS-DVBS-DATA

T22

TS-DVBS-CLOCK

R22 R23

TS-DVBS-SOP

TS-DVBS-VALID

78 62

TS-FE-DATA

TS-FE-CLOCK

TS-FE-SOP

TS-TS-VALID

9R03-4

9R04

9R03-2

9R03-1

B02G

RESET-ETHERNETn

B08A

XIO-D(00-15)

Pin8 Pin3Pin5Pin7 Pin6

Pin4

Pin9

Pin2 Pin1

7GA0 XC9572XL

CPLD

VIO

VCCIO

PNX-SPI-SDI

PNX-SPI-SDO

PNX-SPI-CS-BLn

PNX-SPI-CLK

PNX-SPI-CSBn

HDMIA-RX

4 3 21

USB-DM1

USB-DP1

USB-DM2

USB-DP2

SIDE USB

CONNECTOR

1P08

+5V-USB2

+5V-USB1

5 6

4 3 21

SIDE USB

CONNECTOR

1P07

+3V3-1

USB-DM3 USB-DP3

13 14

9F26

9F25

7FL5 CY7C65631

USB HUB

1H24

4 5

+5V

1F24

4 5

USB-DM USB-DP

R26 R25

USB_DP

USB_DN

TNR_SER1_MIVAL

TNR_SER1_SOP

TNR_SER1_MICLK

TNR_SER1_DATA

1F51

4 5

LEVEL SHIFTED

FOR

DEBUG USE

ONLY

7E10 LAN8710A-EZK

ETHERNET

CONNECTOR

RJ45

SDM

SPI-PROG

1FL5

24M

1E70

25M

K24

CA-MOCLKMOCLK

VS_2

L23

CA-MOVALMOVAL

MOVAL

L22

CA-MOSTRTMOSTRT

MOSTRT

7F00

1N00

7FJ0 CXD2820R

DVBT2

CHANNEL

DECODER

DVBT2-IFN DVBT2-IFP

49 50

5 7

TS-FE-VALID

TS-FE-SOP

TS-FE-CLOCK

TS-FE-DATA

RES

9GA0

RESET-SYSTEMn

1M59

4 6

13 14

AMBI-SPI-CLK-OUT

AMBI-SPI-SDO-OUT

AMBI-SPI-SDI-OUT_G1

AMBI-PWM-CLK_B2

AMBI-SPI-CS-OUTn_R2

AMBI-LATCH1_G2

AMBI-PROG_B1

AMBI-BLANK_R1

AMBI-LATCH2_DIS

AMBI-TEMP-1

1H59

4 6

13 14

AMBILIGHT

MODULE

7GA0 XC9572XL

FPGA

1M54

4 5

BL-DIM5 BL-DIM6

1G51

3D-LR-DISP

1W35

AUDIO-SPEAKERn

BL-DIM7

BL-DIM8

BL-DIM9

BL-DIM10

BL-DIM11

BL-DIM12

DISPLAY

STAND

TO WIFI MODULE

3U42

3C70

3U43

B11A B06B

6 7

100

PROG-B

7H06 RT9818C

INP

OUTP

7H08 XC3S200A

FLASH

512K

SP3A-CCLK

6 1

27 46

SP3A-CSO-B

SP3A-MOSI

SP3A-MISO

+3V3

GND

PR3D-LED

BL-DIM

FPGA-SYS-CLK

7H05 3225

27M

3D-VS

3D-VS-DISP

CH02 CH01

TO POWER SUPPLY

ONLY FOR SSB 3104 313 6538.x

SSB 3104 313 6538.x

FOR SSB 3104 313 6538.x

CTRL-DISP

BACKLIGHT-PWM_BL-VS

LAMP-ON

SPLASH-ON

3D-LED

B03C B03C B02G B09A B02G

Block Diagrams

EN 86Q551.2E LA 9.

2011-Sep-09

back to

div. table

Page 87

9-11 Block Diagram I2C

I²C

PNX85500: MIPS

B02E

DDR

B05A

FLASH

B01B

ETHERNET + SERVICE

B04C

PNX85500: CONTROL

B01E

PNX85500-CONTROL

B01E

PNX85500: STANDBY CONTROLER

B02G

HDMI

B04D

DVBT2

B10A

HDMI

B01H

TEMP SENSOR + HEADPHONE

B01J

DVBS-FE

B07A

DVBS-SUPPLY

B08B

TUNER BRAZIL

B01K

TUNER

B01F

PNX85500: ANALOG VIDEO

B02I

ETHERNET + SERVICE

B04C

VGA

B01I

VIDEO OUT - LVDS

B06B

DVBS CONNECTOR BOARD

B09A

FPGA-BACKLIGHT DIMMING

B11A

FPGA - I/O BANKS

FB02A

FPGA

FPGA - BACKLIGHT DIMMING

FB02x

FB02G

1F52

7S00 PNX85537EB

PNX85537

SDA-SSB

SCL-SSB

C25 C26

1_SDA

1_SCL

AC23 AC24

MC_SDA MC_SCL

B25 A24

3_SDA

3_SCL

SDA-UP-MIPS SCL-UP-MIPS

CONTROL

STANDBY

DEBUG

ONLY

19050_005_110415.eps

110810

RES

3F63 3F62

7F58

M24C64

EEPROM

(NVM)

3F60

3F59

TUN-P7 TUN-P6

SDA-TUNER

SCL-TUNER

1T01

TH2627

MAIN

TUNER

3S60 3S61

3F75 3F76

53 54

7EC1

SII9287B SII9187A

HDMI MUX

3EC5

3EC3

HDMI

CONNECTOR 3

HDMI

CONNECTOR 2

1P04

16 15

29 30

1P03

16 15

33 34

1P02

16 15

39 40

HDMI

CONNECTOR

SIDE

1P05

16 15

3FBF-2

3FBF-1

DIN-5V

43 44

47 48

Y25 Y26

Y23 Y24

GPIO_2 GPIO_3

DDCA-SDA DDCA-SCL

ARX-DDC-SDA

ARX-DDC-SCL

BRX-DDC-SDA

BRX-DDC-SCL

CRX-DDC-SDA CRX-DDC-SCL

DRX-DDC-SDA DRX-DDC-SCL

7FD1

LM75BDP

TEMP

SENSOR

3FD3

3FD4

46 45

7FE0

TC90517FG

DEMODULATOR

3FE9

3FE8

13 12

3S56 3S57

3S2F

3S2G

3S5Y

3S5Z

3S6D

3S6E

+3V3

3S69

3S6A

+3V3

3S6V

3S6W

+3V3-STANDBY

3S81

3S80

+3V3

3S83

3S84

+3V3

3S6F

3S6G

+3V3

AD25 AD24

1E05

12 15

VGA-SDA-EDID-HDMI VGA-SCL-EDID-HDMI

VGA-SDA-EDID VGA-SCL-EDID

3FC1

3FC2

+5V-VGA

9FC2 9FC4

9FC1 9FC3

RES

3S5V-1 3S5V-3

3EC1-1

3EC1-3

AIN-5V

3ECA-1

3ECA-2

BIN-5V

3ECA-3

3ECA-4

CIN-5V

3ECP-3

3ECP-1

+5V-EDID

3ECU-2

3ECU-4

+3V3

B24

Y6 AB4 AC1 AA3

11 10

A23

4_SDA

4_SCL

AE21 AF21

P3_0 P3_1

VGA

CONNECTOR

RXD1-MIPS

TXD1-MIPS

W21 W22

GPIO_2 GPIO_3

RXD2-MIPS TXD2-MIPS

UART

SERVICE

CONNECTOR

1E06

2 1

3E53-3 3E53-1

3E53-4 3E53-2

1F51

B02E

B02G

MEMORY

B02B

FLASH

B02A

ANALOGUE

VIDEO

VGA_EDID_SDA

VGA_EDID_SCL

B02I

B02C

ERR

ERR15ERR

4 5

SDA-BL SCL-BL

LVD S

CONNECTOR

TO DISPLAY OR BOLT-ON

1G51

50 49

SDA-DISP SCL-DISP

3S67

3S65

3S68

3S66

+3V3

B26 A25

2_SDA

2_SCL

SDA-SET

SCL-SET

3S58

3S5W

3S6B

3S6C

+3V3

3S1G

3S1H

+3V3-STANDBY

RES

9S13 9S10

3G2W 3G2Y

LEVEL SHIFTED

FOR DEBUG

USE ONLY

RXD-UP TXD-UP

3F65 3F64

7S01

PCA9540B

2 CHAN.

MULTIPLEX.

ERR

7T50

LNBH23QT

LNB

CONTROLLER

3T61

3T51

ERR

29 30

7FJ0

CXD2820R

DVBT CHANNEL DECODER

3FJJ

3FJH

98 97

7R01

STV903BAC

CHANEL DEC

DVBS

3R00

3R01

ERR

7R02

STV6110A SATELITE

TUNER

ERR

9S12 9S11

7E10 LAN8710A-EZK

ETH-RXD(0)

ETH-RXD(3) ETH-RXCLK

ETH-RXD(1) ETH-RXD(2)

AA1 AA4

AB1 AB2 AA2

22 23 24 25 20

ETH-TXD(0)

ETH-TXD(3) ETH-TXCLK

ETH-TXD(1) ETH-TXD(2)

RXD_0 RXD_1 RXD_2 RXD_3 RXCLK

TXD_0 TXD_1 TXD_2 TXD_3 TXCLK

XIO_D

ETHERNET

3R15

3R14

+3V3RF

18 19

SDAT SCLT

DDC_A_SDA DDC_A_SCL

HDMI_DV

HDMI

CONNECTOR 1

ETHERNET

CONNECTOR

RJ45

RES

SDRAM 128Mx8

7B01 H5PS1G83EFR

SDRAM 128Mx8

7B02 H5PS1G83EFR

FLASH

(4Gx16)

SDRAM 128Mx8

7B03 H5PS1G83EFR

SDRAM 128Mx8

7B00 H5PS1G83EFR

DDR2-D(0-31)

XIO-D(00-07)

D(24-31)

D(16-23)

D(8-15)

D(0-7)

DDR2-A(0-13)

18 2

SPI_CLK

SPI_CSB SPI_SDO SPI_SDI

P6_5

7F52 M25P05-AVMN6P

FLASH

512K

+3V3-STANDBY

VCC

PNX-SPI-CLK

AF24

PNX-SPI-WPn

AE22

PNX-SPI-CSBn

AF23

PNX-SPI-SDO

AE23

PNX-SPI-SDI

AF25

7F20 H27U4G8F2DTR

ERR

STANDBY

MAIN

MAIN NVM

EDID

Programmable via USB

RES

OPTIONALOPTIONAL OPTIONAL

1M71

3C83 3C81

16 15

7H08

XC3S200A

FPGA

(SPARTAN)

3H14

3H13

RES

NAND-CE1n

E21

NAND_CE1 NAND_RDY1 NAND_WP_

NAND-RDY1n

F21

NAND-WPn

A21

9 7 19

PQ-FPGA

FRCV

BL-FPGA

TCON

for component

7T00

7T20

7T08

supported via main software

ONLY FOR

SSB 3104 313 6538.x

Block Diagrams

EN 87Q551.2E LA 9.

2011-Sep-09

back to

div. table

Page 88

9-12 Supply Lines Overview

B01A

COMMON INTERFACE

B01D

SD-CARD

B01F

TUNER

B01K

TUNER BRAZIL

B01C

USB HUB

B02B

PNX85500: SDRAM

B01B

FLASH

B02A

PNX85500: NANDFLASH CONDITIONAL ACCESS

B02C

PNX85500: DIGITAL VIDEO IN

B02E

PNX85500: MIPS

B02G

PNX85500: STANDBY CONTROLLER

B02H

PNX85500: POWER

B01I

VGA

B01J

TEMP SENSOR + HEADPHONE

B01E

PNX85500: CONTROL

B03D

DC / DC

B03E

DC / DC

B08A

DVBS-SUPPLY

B08B

DVBS-SUPPLY

B10A

DVBT2

B04A

ANALOGUE EXTERNALS A

B04C

ETHERNET + SERVICE

B03F

TEMPSENSOR + AMBILIGHT

B06A

DISPLAY INTERFACING-VDISP

B02D

PNX85500: AUDIO

B03B

DC / DC

SUPPLY LINES OVERVIEW

PSU

B03C

CONNECTORS COMP

B11B

CONNECTORS

B03H

VDISP - SWITCH

B04D

HDMI

B04E

HEADPHONE

B04B

ANALOGUE EXTERNALS B

B06B

VIDEO OUT - LVDS

B06D

SPI-BUFFER

B06C

AMBILIGHT CPLD

B07A

DVBS-FE

B05A

DDR

B01G

TOSHIBA SUPPLY

B03G

FAN - CONTROL

B09A

CONNECTORS COMP

B01H

HDMI

B03A

AUDIO

B03C

DC / DC

B11A

FPGA-BACKLIGHT DIMMING

B11B

CONNECTORS

B12A

DVBS DCDC TPA54231

+5V

+5VCA

3F01

B03e

+3V3

B03e

+3V3-SD

3F40

+3V3

+5V-TUN-PIN

+5V-TUN

B03e

+3V3

B03e

+1V8

DDR2-VREF-CTRL2

DDR2-VREF-CTRL3

B03c (B11b)

+3V3

B03e

+3V3

B03e

B01g

B03e

B03b

+3V3

B03e

B01e,B02e, g,h,B03a,b,c,h, B04d,e,B09a

B02d,B03a

+3V3

B03e

+3V3-ST

ANDBY

+3V3-STANDBY

B03c (B11b)

+1V1

B03b

+3V3-STANDBY

B03c (B11b)

+1V1

B03b

B10a

+1V2

B03d

+1V8

B03b

+2V5

B03d

+2V5-AUDIO

B02d

+2V5-LVDS

B03d

+3V3

B03e

+3V3-STANDBY

+3V3-ST

ANDBY

B03c (B11b)

+3V3

+1V2-BRA-VDDC

+1V2-BRA-DR1

+3V3

B03e

+3V3-STANDBY

B03c (B11b)

+5V

B03e

B03d

B03e

9F71

+3V3-BRA

+3V3

5FE7

+3V3

+5V+5V

+2V5-LVDS

+2V5

B03e

B11b

+2V5-AUDIO

+3V3-ARC

+3V3+3V3

B03d

+2V5+2V5

+2V5-BRA

+3V3-BRA-FLT

+5V+5V

7FE3

IN OUT

COM

5FE9

5FE4

3S20 3S06

+24V-AUDIO-POWER

+24V-AUDIO-VDD

3S0Z

3S11

7U03 TPS53126PW

+12V

+1V8

+1V1

5U01

+12V

12V/1V1

COVERSION

12V/1V8

COVERSION

5U02

5U00

B03c

+3V3-STANDBY

B03c (B11b)

Dual

Synchronous

Step-Down

Controller

7U04

7U01

7U02-2

7U02-1

1M95

66 77

1M95

+3V3-STANDBY

+12V_AL_BRG

3V3SB

+12V3

1M09

11 22

LAMP-ON-1

14 14

1M99

BACKLIGHT-BOOST-1

+12V_AL

GND_AL

B03c,h

B11b

B09a

B08a,B09a

BACKLIGHT-PWM_BL-VS-1

+24V-AUDIO-POWER

13 13

+24V

10 10

+VSND

BL-DIM1

BL-I-CTRL

POK

44 55

STANDBY-1

STANDBY

GND1 GND1

GND1

BL-ON-OFF

GND1

11 11

+24V

GND1

+12VIN

CUA0

+1V2

+1V8+1V8

+12V

7UA3

B03b

+3V3-ET-ANA

+3V3+3V3

B03e

+2V5-REF

+12V+12V

B03c

B03b

B02h

B03c

B03e B03e

B03e

3U16

3UA0

7UC0

IN OUT

COM

3U15

7UA0

VOLT.

REG.

+5V-TUN

+5V5-TUN+5V5-TUN

7UA6

ENABLE-1V8

+3V3

+12V+12V

+1V1+1V1

B03e

+12VIN+12VIN

+5V+5V

+3V3+3V3

B03e

+3V3+3V3

5UD3 5UD2

+5V

+5V5-TUN

6UD0

7UD1

IN OUT

COM

+3V3+3V3

V-AMBI

1UM0 T 1.0A

5UM1

+VDISP-INT+VDISP-INT

+VDISP

1G03 T 3.0A

5E08

+VDISP-INT

+12VD+12VD

+3V3+3V3

7UU2

LCD-PWR-ONn

7UU0

B03c

B03e

+3V3-STANDBY+3V3-STANDBY

B03c (B11b)

1P03

HDMI 2

CONNECTOR

BIN-5V

1P02

HDMI 1

CONNECTOR

+5V-EDID

+3V3-STANDBY+3V3-STANDBY

+3V3+3V3

+3V3-HDMI

CIN-5V

1P04

HDMI 3

CONNECTOR

AIN-5V

5EC0

B03e

B03c (B11b)

B03e

+5V-VGA+5V-VGA

+5V +5V

B01I

B02b,h,B03d, B05a

B02h,g,B03e

DIN-5VDIN-5V

B01h

B03e

B03c (B11b)

B03h

B03b

6EC1

+3V3-STANDBY+3V3-STANDBY

+3V3+3V3

B03e

+5V+5V

B03e

B06a

+VDISP+VDISP

+3V3+3V3

B08a

+2V5-DVBS+2V5-DVBS

+1V-DVBS+1V-DVBS

B03e

+3V3

B01f

B06a

B09a

B03d

VIO

+3V3+3V3

B03e

5GA1

VINT

5GA0

+3V3RF

+3V3-DVBS+3V3-DVBS

B08a

5R01

+3V3-DEMOD

5R00

B03c (B11b)

+24V

+5V-DVBS

+2V5-DVBS

+24V

B03e

+3V3+3V3

+V-LNB

B03c

+12V+12V

B08a

+V-LNB+V-LNB

B08a

+3V3-DVBS+3V3-DVBS

5T03

5T04

7T03 TPS54283PWP

Dual

N-Synchr

Converter

+3V3-DVBS

7T02

IN OUT

COM

+1V-DVBS

7T00

IN OUT

COM

5T00 5T01

7T01

IN OUT

COM

5T02

B01,a,c,e,k, B03c,d,e, B04a,b,d, B09a

B08b

B07a,B08b

B07a

B02g,h, B03e,B10a

B02d,h B02h

+5V-VGA

1E05

VGA

CONNECTOR

B04d

B01g

19050_004_110415.eps

110729

B01E

POWER-OK-1

12 12

B02G

B02G B06C

B01,a,b,c,d,e, g,j,k, B02a,c,d,e,h, B03c,f,g,h, B04a,c,d,e, B06b,c,d, B08a,B09a, B10a,B11a

+12V3

GND1

DDR2-VREF-DDR

+1V8+1V8

B03b

3B20

B03e

+1V2-BRA-VDDC

+3V3+3V3

+1V2-BRA-DR1

B01k

7FA3

IN OUT

COM

5FA3

7S08

IN OUT

COM

+3V3-DVBT2-R

+2V5-DVB

+2V5-DVBT2-A +2V5-DVBT2-X

+3V3+3V3

B03e

5FK1

5FJ2

+3V3-DVBT2-D

5FJ1

+1V2-DVBT2-C

+1V2-DVBT2-M

+1V2-DVBT2-P

+1V2+1V2

B03d

B06b

+5V-TUN-PIN+5V-TUN-PIN

B01f

+1V2-FE

7FK1

IN OUT

COM

9FK6

5FJ7

5FJ5 5FJ6

5FJ3 5FJ4

VCCINT

+3V3+3V3

B03e

7H03

IN OUT

COM

6 7

1H95

1 2

1H99

GND_AL

4 5

11 12

5FA4

B03e B03c

+12V+12V

+3V3+3V3

5UD0 5UD1

7UD0

IN OUT

COM

+5V

+3V3-1

+5V-USB2

3FL2

+5V-USB1

3F32

B03e

B03c (B11b)

+3V3-STANDBY+3V3-STANDBY

+5V+5V

+3V3+3V3

B03c (B11b)

+12V_AL+12V_AL

1M71

1M59

1M21

TEMP

SENSOR

(OPTIONAL)

IR/LED

BOARD

+5V+5V

B03e

+3V3+3V3

B03e

+3V3-STANDBY+3V3-STANDBY

B03c (B11b)

B03b,d,e,g, B08b,B09a

B03h

+12V

1U40 T 3.0A

+12VD

DIN-5V

1P05

HDMI SIDE

CONNECTOR

B04d

B03c (B11b)

+3V3-STANDBY+3V3-STANDBY

+24V-AUDIO-POWER

+AVCC

3D09

9FL2

VCCA-O

5H01

+5V-DVBS

+24V+24V

B03e

+3V3+3V3

B03e

7K00

IN OUT

COM

5K00

B03e B01c

+3V3

+3V3-1

B03e

B03f

B11b

+5V

1H87

T 2.0A

+12V_AL_BRG+12V_AL_BRG

B09a

V-AMBI

1H59

AMBILIGHT

MODULE

AMBILIGHT

MODULE

ONLY FOR SSB 3104 313 6538.x

AMBI-POWER

1C87 T 2.0A

SSB 3104 313 6538.x

SSB 3104 313 6539.x

Block Diagrams

EN 88Q551.2E LA 9.

2011-Sep-09

back to

div. table

Page 89

Block Diagrams

9-13 Block Diagram Bolt-On 1, 3104 313 65372, xxPFL9xx6 series except 37"

BLOCK DIAGRAM Bolt-On 1, 3104 313 65372, xxPFL9xx6 series except 37"

EN 89Q551.2E LA 9.

BLOCK DIAGRAM VIDEO, AUDIO

FB02N

1G51

FROM SSB

INPUT-LVDS

FPGA-RX2

FPGA-RX1

FB02x

FB02B

7T02 M25P40

FLASH 16Mbit

PQ-FPGA

FPGA

FPGA SUPPLY & CTL

MISO MOSI CCLK CSO-B

7T00 XC6SLX9

PQ FPGA

A(0-12)

FB02C

7T04 H5PS5162

DQ(0-15)

FB02J

7T30 M25P16

FLASH

16Mbit

FRCV

FB02H

FPGA-DDR

DDR2

1x64MB

FPGA-TX2

FPGA-TX1

FRC-CONTROL

AUDIO + WiHD

FB02x

SF-SO SFB-SI SFB-SCK SFB-CS SFB-WPn SFB-Hldn

FRC-V

7T20 TFRCV-B1A03

TRIDENT

FRC-V

FB02Q

MA(0-13)

7T50 H5TQ1G63

DDR3

128MB

AUDIO-SPEAKERn

FCR-DDR3

MD(0-15)

V1-TX0

V1-TX7

FB02P

FRC-V-BY-ONE

1T51

TO DISPLAY PANEL

1W53

STAND

SUPPLY LINES OVERVIEW

DC-DC CONVERTERS

FB01A

1M99

1 2 3 4 5 6 7 8 9 10

FB02N

1G51

48 ... 51

FROM SSB FROM PSUFROM SSB

54 ... 61

GND_AL

INPUT - LVDS

9S05

+12VD

+12V

FB02n

FB02e

FB01a

FB02b

FB02b FB02c

DC-DC CONVERTERS

FB01A

5U54

+12V

5U55

5U53

3U15

FPGA I/O BANKS

FB02A

+1V2-FPGA

+1V8-FPGA

VCCO0

VCCO1

VCCO2

VAUX

FPGA-DDR2-VREF

7U75

7U76

7U10

7U51

TPS53114

6U15

7U05

7U06

FPGA-DDR2-VREF

5U75

5U76

+1V05

5U51

+1V2-FPGA

+1V8-FPGA

VCCO0

VCCO1

VCCO2

VAUX

+1V5

+3V3

+2V5

+5V

FB01a FB01a

FB01a

FB02b

FB01a

FPGA-SUPPLY & CRTL

FB02B

5T00

+2V5

5T03

+3V3

5T05

5T07

7T09

IN OUT

COM

7T15...7T17

+5V

FPGA-DDR

FB02C

+1V8-FPGA

OUTPUT-VDISP

FB02E

+12VD

7T06

LCD-PWR-ONn

+2V5

3T18

1T10

T 3.0A

VAUX

VCCO2 VCCO1

VCCO0

+1V8-FPGA +1V8-FPGA

+1V2-FPGA

+1V8-FPGA

FPGA-DDR2-VREF

+VDSIP

+2V5

FB02a FB02a FB02a

FB02a

FB02a, FB02c

FB02a

FB02p

FB01a

FB01a FB01a

FB01a

FB01a FB02b FB02e

FB01a

FB02n FB01a

FB01a

AUDIO - WiHD

FB02H

FRC - CONTROL

FB02J

5TDA

FRC - DDR IO

FB02K

+1V5

FRC - SUPPLY ANA

FB02L

FRC - SUPPLY DIG

FB02M

+1V5 +1V05

I2C-MUX & TEMPSENS.

FB02O

FRC V-BY-ONE OUTPUT

FB02P

+1V8-FPGA +1V8-FPGA +VDISP +VDISP

FRC - DDR3

FB02Q

+1V5

POWER SEQUENCING

FB02R

+3V3 +3V3 +2V5

CONNECTORS BACKL.

FB02S

+3V3 +3V3

+3V3-SFB

+3V3+3V3

+1V5

+2V5+2V5

+3V3+3V3 +1V5

+1V05

+3V3+3V3

+1V5

+12V+12V

+2V5

BLOCK DIAGRAM I²C

INPUT-LVDS

FB02N

1G51

FROM SSB

3S40

3S42

FB02O

+3V3

3SG9

SDA_SSB

SCL_SSB

I²C-MUX & I²C TEMP SENSOR

3SG2

3TS4

3TS5

7GS2

LM75BDP

TEMP

SENSOR

RES

FPGA-I/O BANKS

FB02A

3T30

3T29

R12

T12

7T00

XC6SLX9 PQ FPGA

3SH3

3SH2

1SG2

PROGRAMMING

7GS1

PCA9540B

2 CHAN.

MULTIPLEX.

ENGINEERING

3HS0

4 5

7 8

RES

+3V3

3GS6

3SH1

3GS7

9GS5

9GS4

9GS7

9GS6

SDA-DISP

SCL-DISP

SDA-BL

SCL-BL

FB02J

RES

FRC-CONTROL

3TDD

3TDA

TFRCV-B1A03

FB02D

FB02P

FB02S

RES

3TDB

7T20

FRC-V

OUTPUT-LVDS FPGA

1T61

3T61

3T62

RES

FRC V-BY-ONE OUTPUT

1T51

3TN7

3TN6

TO DISPLAY PANEL

CONNECTORS BACKLIGHT

1F53

3SEG

3SC6

TO DISPLAY PANEL

3TDC

3TDG

B24

SDA-FRC

3TDF

C24

SCL-FRC

BLOCK DIAGRAM CONTROL & CLOCK SIGNALS

INPUT-LVDS

FB02N

1G51

CTRL-DISPIN

BL-ON-OUT

BL-DIM

3D-LED-S6 4 10

SPLASH-ON

FB02J

FPGA

FB02B

SUPPLY & CTL

LCD-PWR-ON-FRCn

FB02J

LCD-PWR-ONn

FB02E

7T02 M25P40

FLASH 16Mbit

PQ-FPGA

7T03

FPGA-SYS-CLK

27M

+3V3

1T22

3TDW

3TDV

DEBUG

MISO MOSI CCLK CSO-B

9T14

7T00 XC6SLX9

PQ FPGA

FB02C

A(0-12)

CONTROL

DQ(0-15)

3D-LR 3D-VS RESET-FRCn CTRL-DISP 3D-LR-FPGA-FRC 3D-LR-DISP BL-SPI-SDO BL-SPI-CSn BL-SPI-CLK

FPGA-DDR

7T04 H5PS5162

DDR2

1x64MB

FB02J

FB02B

FRC - CONTROL

BL-ON-OUT

SPLASH-ON

FB02N

LCD-PWR-ON-FRCn

3D-LR RESET-FRCn CTRL-DISP 3D-LR-FPGA-FRC BL-SPI-SDO BL-SPI-CSn BL-SPI-CLK 3D-LR-DISP

7T20 TFRCV-B1A03

TRIDENT

FRC-V

FB02Q

MA(0-13)

MD(0-15)

FB02J

SF-SO SF-SI SF-SCK SF-CS SF-WPn SF-Hldn

BL-ON VSYNC-FRC

1T21

FCR-DDR3

7T50 H5TQ1G63

DDR3

128MB

CONTROL

FRC-CONTROL

7T60, 7T61

+3V3

7T25 NCP303LSN28G

INP

OUTP

GND

24M

SFB-SO SFB-SI SFB-SCK SFB-CS SFB-WPn SFB-Hldn

7T30 M25P16

FLASH

16Mbit

3TG3, 9T19

3D-VS

RESET-FRCn

FRCV

VSYNC-FRC BL-SPI-SDO BL-SPI-CLK BL-SPI-CSn

3TG4

BL-ON-OUT

9T23..25

FB02P

CTRL-DISP

FB02S

BL-SPI-SDO-OUT BL-SPI-CLK-OUT BL-SPI-CSn-OUT

FRC-V-BY-ONE

1T51

CONNECTORS BACKLIGHT

1F53

7 5

PANEL

TO DISPLAY

PANEL

TO DISPLAY

2011-Sep-09

back to

div. table

19050_094_110902.eps

110908

Page 90

9-14 Block Diagram Bolt-On 1, 3104 313 65372, xxPFL8xx6 series

19050_093_110902.eps

110908

BLOCK DIAGRAM VIDEO, AUDIO

DDR3

128MB

DDR2

1x64MB

FPGA-RX2

V1-TX0

1G51

1T51

TRIDENT

FRC-V

PQ FPGA

BL FPGA

FPGA-RX1

FB02N

INPUT-LVDS

7T00 XC6SLX9

FB02x

FPGA

FB02C

FPGA-DDR

DQ(0-15)

A(0-12)

7T04 H5PS5162

FPGA-TX2

FPGA-TX1

7T20 TFRCV-B1A03

FB02x

FRC-V

DDR3

128MB

MA(0-13)

7T50 H5TQ1G63

7T51 H5TQ1G63

MD(0-15)

MD(16-31)

V1-TX7

FB02Q

FCR-DDR3

FB02P

FRC-V-BY-ONE

FLASH 16Mbit

7T30 M25P16

FRCV

SFB-SI SFB-SCK SFB-CS

SF-SO

SFB-WPn SFB-Hldn

FB02J

FRC-CONTROL

PQ-FPGA

FB02B

FPGA SUPPLY & CTL

7T02 M25P40

FLASH

4Mbit

MISO MOSI CCLK CSO-B

1W53

FB02H

AUDIO + WiHD

AUDIO-SPEAKERn

BLOCK DIAGRAM Bolt-On 1, 3104 313 65372, xxPFL8xx6 series

BLOCK DIAGRAM I²C

1G51

FB02N

INPUT-LVDS

3SG9

3SG2

+3V3

SDA_SSB

SCL_SSB

3S40

3S42

FB02O

I²C-MUX & I²C TEMP SENSOR

4 5

3HS0

3GS6

3SH1

3GS7

+3V3

RES

7 8

9GS7

9GS6

7GS1

PCA9540B

2 CHAN.

MULTIPLEX.

9GS5

9GS4

7GS2

LM75BDP

TEMP

SENSOR

3TS4

3TS5

SDA-DISP

SCL-DISP

SDA-BL

SCL-BL

RES

1T61

FB02D

OUTPUT-LVDS FPGA

3T30

3T29

T12

R12

FB02G

FPGA-BACKLIGHT DIMMING

7T00

XC6SLX9 PQ FPGA

7T08

XCS3S50A

BL FPGA

3TCK

3TCH

FB02A

FPGA-I/O BANKS

7T20

TFRCV-B1A03

FRC-V

3TDD

3TDC

FB02J

FRC-CONTROL

3TDB

RES

+3V3

3TDG

3TDF

SDA-FRC

SCL-FRC

B24

C24

3TDW

3TDV

1T22

1SG2

3SH3

3SH2

3T61

3T62

1T51

3TN7

3TN6

FB02P

FRC V-BY-ONE OUTPUT

1F53

FB02S

CONNECTORS BACKLIGHT

3SEG

3SC6

RES

BLOCK DIAGRAM CONTROL & CLOCK SIGNALS

TRIDENT

FRC-V

PQ FPGA

7T00 XC6SLX9

FB02C

FPGA-DDR

DDR2

1x64MB

7T04 H5PS5162

7T20 TFRCV-B1A03

MA(0-13)

DDR3

128MB

7T50 H5TQ1G63

DDR3

128MB

7T51 H5TQ1G63

MD(16-31)

FB02Q

FCR-DDR3

FB02P

FRC-V-BY-ONE

FLASH 16Mbit

7T30 M25P16

FRCV

SF-SI SF-SCK SF-CS

SF-SO

SF-WPn SF-Hldn

FB02J

FRC-CONTROL

PQ-FPGA

FB02B

FPGA SUPPLY & CTL

7T02 M25P40

FLASH 16Mbit

MISO MOSI CCLK CSO-B

1M99

GND_AL

6 7 8 9 10

2 3 4 5

+12VD

FB01A

DC-DC CONVERTERS

FB02N

INPUT - LVDS

54 ... 61

1G51

48 ... 51

9S05

+12V

FB01a

FB01A

DC-DC CONVERTERS

FB02n

+12V

7U75

5U54

5U75

7U76

5U55

5U76

7U06

7U05

7U51

TPS53114

5U53

5U51

+1V5

+3V3

7U10

+2V5

+1V05

FB02A

FPGA I/O BANKS

+1V2-FPGA

+1V8-FPGA

VCCO0

VCCO1

VCCO2

+1V2-FPGA

+1V8-FPGA

VCCO0

VCCO1

VCCO2

VAUX

FPGA-DDR2-VREF

VAUX

FPGA-DDR2-VREF

+5V

3U15

6U15

FB02B

FPGA-SUPPLY & CRTL

+2V5

5T00

VAUX

FB02a

FB02b

FB01a

+1V2-FPGA

+1V8-FPGA +1V8-FPGA

+3V3

VCCO2

FB02a

FB01a

5T03

FB02b

VCCO1

FB02a

5T05

VCCO0

FB02a

5T07

FB02b

FB01a

7T09

IN OUT

COM

FB02a, FB02c

7T15...7T17

+5V

+1V2-FPGA

FB02a

FB02b

FB02C

FPGA-DDR

+1V8-FPGA

3T18

FPGA-DDR2-VREF

FB02E

OUTPUT-VDISP

FB02e

FB02b

7T06

LCD-PWR-ONn

1T10 T 3.0A

+12VD

FB01a

+2V5

+VDSIP

FB02G

FPGA BACKLIGHT DIM

FB01a

7TC3

IN OUT

COM

+3V3

VCCINT

5T06

VCCA-O

FB02H

AUDIO - WiHD

+3V3+3V3

FB02J

FRC - CONTROL

+3V3+3V3

5TDA

+3V3-SFB

FB02K

FRC - DDR IO

+1V5

FB02L

FRC - SUPPLY ANA

+2V5+2V5

FB02M

FRC - SUPPLY DIG

+3V3+3V3 +1V5

+1V5

+1V05

FB02O

I2C-MUX & TEMPSENS.

+3V3+3V3

FB02P

FRC V-BY-ONE OUTPUT

+3V3+3V3 +1V8-FPGA +1V8-FPGA +VDISP +VDISP

FB02Q

FRC - DDR3

+1V5

FB02p

FB02R

POWER SEQUENCING

+12V+12V +3V3 +3V3 +2V5

+2V5

FB01a

FB01a FB01a

FB01a

FB02n

FB02e

FB02b

FB01a

FPGA-DDR2-VREF

FB02a

FB02c

FB02S

CONNECTORS BACKL.

+3V3 +3V3

FB01a

SUPPLY LINES OVERVIEW

MD(0-15)

7T08 XC3S50A

BL-FPGA

7TC2 M25P05

FLASH 512kbit

SP3A-MISO SP3A-MOSI SP3A-CCLK SP3A-CSO-B

A(0-12)

DQ(0-15)

1M54

2 : 9

FB02S

CONNECTORS BACKLIGHT

FB02G

FPGA-BACKLIGHT DIMMING

7T03

27M

FPGA-SYS-CLK

FB02G

CPLD-SYS-CLK

1G51

FB02N

INPUT-LVDS

CTRL-DISPIN

1T21

24M

BL-ON-OUT

BL-DIM

3D-LED-S6 3D-LED-S3A

4 10

SPLASH-ON

BL-DIM(5-12)

BL-SPI-CLK

BL-SPI-CSn

BL-SPI-SDO

CONTROL

BL-ON-OUT

SPLASH-ON

FB02J

FB02N

CTRL-DISPIN BL-DIM 3D-LED-S3A SPLASH-ON

FB02N

BL-DIM(5-12)

BL-SPI-CLK

BL-SPI-CSn

BL-SPI-SDO

BL-SPI-CLK

BL-SPI-CSn

BL-SPI-SDO

1T51

3D-LR-DISP

3D-LR-FPGA-FRC

CTRL-DISP

RESET-FRCn

7T25 NCP303LSN28G

INP

OUTP

+3V3

GND

RESET-FRCn

CONTROL

3D-VS

VSYNC-FRC

3D-LR

7T60, 7T61

SFB-SI SFB-SCK SFB-CS

SFB-SO

SFB-WPn

SFB-Hldn

3TG3,

9T19

3D-VS

LCD-PWR-ON-FRCn

FB02B

FB02J

FRC - CONTROL

LCD-PWR-ON-FRCn

FB02J

LCD-PWR-ONn

FB02E

9T14

BL-ON

BL-ON-OUT

3TG4

TO DISPLAY PANEL

FROM SSB

FB01a

3TDA

FROM SSB

RES

TO DISPLAY PANEL

PROGRAMMING

ENGINEERING

DEBUG

STAND

FROM SSB FROM PSUFROM SSB

TO DISPLAY

PANEL

TO PSU

Block Diagrams

EN 90Q551.2E LA 9.

2011-Sep-09

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div. table

Page 91

9-15 Block Diagram Bolt-On 3, 3104 313 65462, xxPFL7xx6 series

19050_095_110906.eps

110907

BLOCK DIAGRAM VIDEO, AUDIO

DDR2

1x64MB

FPGA-RX2

TX1

1G51

1T51

TRIDENT

FRC-V

PQ FPGA

FPGA-RX1

FB02N

INPUT-LVDS

7T00 XC6SLX9

FB02x

FPGA

FB02C

FPGA-DDR

DQ(0-15)

A(0-12)

7T04 H5PS5162

FPGA-TX2

FPGA-TX1

7T20 TFRCV-B1A05

FB02x

FRC-V

TX2

FB02Q

FRC-DDR3

FB02P

FRC LVDS OUT

FLASH 16Mbit

7T30 M25P16

FRCV

SFB-SI SFB-SCK SFB-CS

SF-SO

SFB-WPn SFB-Hldn

FB02J

FRC-CONTROL

PQ-FPGA

FB02B

FPGA SUPPLY & CTL

7T02 M25P40

FLASH

16Mbit

MISO MOSI CCLK CSO-B

BLOCK DIAGRAM Bolt-On 3, 3104 313 65462, xxPFL7xx6 series

BLOCK DIAGRAM I²C

1G51

FB02N

INPUT-LVDS

3SG9

3SG2

+3V3

SDA_SSB

SCL_SSB

3S40

3S42

FB02O

I²C-MUX & I²C TEMP SENSOR

4 5

3HS0

3GS6

3SH1

3GS7

+3V3

RES

9GS7

9GS6

7GS1

PCA9540B

2 CHAN.

MULTIPLEX.

9GS5

9GS4

7GS2

LM75BDP

TEMP

SENSOR

3TS4

3TS5

SDA-DISP

SCL-DISP

SDA-BL

SCL-BL

3T30

3T29

T12

R12

7T00

XC6SLX9 PQ FPGA

FB02A

FPGA-I/O BANKS

7T20

TFRCV-B1A05

FRC-V

3TDD

3TDC

FB02J

FRC-CONTROL

3TDB

RES

+3V3

3TDG

3TDF

SDA-FRC

SCL-FRC

B24

C24

3TDW

3TDV

1T22

1SG2

3SH3

3SH2

1T51

3TN1

3TN2

FB02P

FRC LVDS OUT

BLOCK DIAGRAM CONTROL & CLOCK SIGNALS

TRIDENT

FRC-V

PQ FPGA

7T00 XC6SLX9

FB02C

FPGA-DDR

DDR2

1x64MB

7T04 H5PS5162

7T20 TFRCV-B1A05

DDR3

128MB

7T50 H5TQ1G63

FB02Q

FRC-DDR3

FLASH 16Mbit

7T30 M25P16

FRCV

SF-SI SF-SCK SF-CS

SF-SO

SF-WPn SF-Hldn

FB02J

FRC-CONTROL

PQ-FPGA

FB02B

FPGA SUPPLY & CTL

7T02 M25P40

FLASH 16Mbit

MISO MOSI CCLK CSO-B

1M99

GND_AL

6 7 8 9 10

2 3 4 5

+12VD

FB01A

DC-DC CONVERTERS

FB02N

INPUT - LVDS

54 ... 61

1G51

48 ... 51

9S05

+12V

FB01a

FB01A

DC-DC CONVERTERS

FB02n

+12V

7U75

5U54

5U75

7U76

5U55

5U76

7U06

7U05

7U51

TPS53114

5U53

5U51

+1V5

+3V3

7U10

+2V5

+1V05

FB02A

FPGA I/O BANKS

+1V2-FPGA

+1V8-FPGA

VCCO0

VCCO1

VCCO2

+1V2-FPGA

+1V8-FPGA

VCCO0

VCCO1

VCCO2

VAUX

FPGA-DDR2-VREF

VAUX

FPGA-DDR2-VREF

+5V

3U15

6U15

FB02B

FPGA-SUPPLY & CRTL

+2V5

5T00

VAUX

FB02a

FB02b

FB01a

+1V2-FPGA

+1V8-FPGA +1V8-FPGA

+3V3

VCCO2

FB02a

FB01a

5T03

FB02b

VCCO1

FB02a

5T05

VCCO0

FB02a

5T07

FB02b

FB01a

7T09

IN OUT

COM

FB02a, FB02c

7T15...7T17

+5V

+1V2-FPGA

FB02a

FB02b

FB02C

FPGA-DDR

+1V8-FPGA

3T18

FPGA-DDR2-VREF

FB02E

OUTPUT-VDISP

FB02e

FB02b

7T06

LCD-PWR-ONn

1T10 T 3.0A

+12VD

FB01a

+2V5

+VDSIP

FB01a

FB02J

FRC - CONTROL

+3V3+3V3

5TDA

+3V3-SFB

FB02K

FRC - DDR IO

+1V5

FB02L

FRC - SUPPLY ANA

+2V5+2V5

FB02M

FRC - SUPPLY DIG

+3V3+3V3

+1V5

+1V05

FB02O

I2C-MUX & TEMPSENS.

+3V3+3V3

FB02P

FRC LVDS OUT

+VDISP +VDISP

FB02Q

FRC - DDR3

+1V5

FB02p

FB02R

POWER SEQUENCING

+12V+12V +3V3 +3V3 +2V5

+2V5

FB01a

FB01a FB01a

FB01a

FB02n

FB02e

FPGA-DDR2-VREF

FB02a

FB02c

SUPPLY LINES OVERVIEW

MD(0-15)

A(0-12)

DQ(0-15)

7T03

27M

FPGA-SYS-CLK

1G51

FB02N

INPUT-LVDS

CTRL-DISPIN

1T21

24M

BL-ON-OUT

BL-DIM

SPLASH-ON

BL-SPI-CLK

BL-SPI-CSn

BL-SPI-SDO

CONTROL

BL-ON-OUT

SPLASH-ON

FB02J

FB02N

BL-SPI-CLK

BL-SPI-CSn

BL-SPI-SDO

3D-LR-DISP

3D-LR-FPGA-FRC

CTRL-DISP

RESET-FRCn

7T25 NCP303LSN28G

INP

OUTP

+3V3

GND

RESET-FRCn

CONTROL

3D-VS

3D-LR

7T60, 7T61

SFB-SI SFB-SCK SFB-CS

SFB-SO

SFB-WPn

SFB-Hldn

LCD-PWR-ON-FRCn

FB02B

FB02J

FRC - CONTROL

LCD-PWR-ON-FRCn

FB02J

LCD-PWR-ONn

FB02E

9T14

BL-ON

BL-ON-OUT

3TG4

TO DISPLAY PANEL

FROM SSB

FB01a

3TDA

FROM SSB

PROGRAMMING

ENGINEERING

DEBUG

FROM SSB FROM PSUFROM SSB

MA(0-13)

VSYNC-FRC

3TG3, 9T19

3D-VS

DDR3

128MB

DDR3

128MB

MA(0-13)

7T50 H5TQ1G63

7T51 H5TQ1G63

MD(0-15)

MD(16-31)

TX3

TX4

1T50

TO DISPLAY PANEL

RES

FB01C

LEADING EDGE CONN.

1M21 1M20

SCL-CRP

SDA-CRP

FROM SSB

TO LED & CONTROL

1M21 1M20

SCL-CRP SDA-CRP

FROM SSB

TO LED & CONTROL

FB01C

LEADING EDGE CONN.

IR_IRQ_RF4CE

KEYBOARD

LED2-OUT

LED1-OUT

LIGHT-SENSOR

Block Diagrams

EN 91Q551.2E LA 9.

2011-Sep-09

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Page 92

Circuit Diagrams and PWB Layouts

19050_015_110419.eps

110419

Common Interface

B01A B01A

2011-03-07

3104 313 6538

SPB SSB

TV550 2K11 4DDR EU SD

3EN2

3EN1

3EN2

3EN1

3EN2

3EN1

3EN2

3EN1

3EN2

3EN1

3EN2

3EN1

CONTROL

TRANSPORT STREAM FROM CAM

15-BIT ADDRESS

8-BIT DATA

2F05

100n

+3V3

RES

1 8

3F07-3

3 6

10K

3F07-1

10K

3F07-2

3F07-4

10K

HOOK1

1X111X10

HOOK1

IF04

IF08

IF07

IF06

+3V3

+5VCA

3F03-2

1 8

100R

3F03-1

100R

3F02

100R

3F01

0R4

REF EMC HOLE

1X08

100K

3F06

16 15 14 13 12 11

4 5 6 7

74LVC245A

7F04

3F12

10K

3F11-1

10K

1 83F04-1 100R

16V22u

2F01RES

+5VCA

RES

2F00

100n

17 16 15 14 13 12 11

4 5 6 7

7F00

74LVC245A

3F10-4

10K

3 6

10K

3F10-3

1 8

3F10-2

10K

3F10-1

IF05

IF03

IF02

IF01

+3V3

3F11-4

10K

3 6

10K

3F11-3

3F11-2

10K

69 70

71 72

61 62 63 64 65 66 67

51 52 53 54 55 56 57 58 59

42 43 44 45 46 47 48 49

33 34 35 36 37 38 39

40 41

24 25 26 27 28 29

30 31 32

15 16 17 18 19

20 21 22 23

1P00

92789-055LF

10 11 12 13 14

+3V3

100R3F05-33 6

3F05-2

100R

1 8

3F05-1 100R

100R3F04-4

3F08-4

10K

3F08-3

3 6

10K

1 8

3F08-2

3F08-1

100n

2F02

+3V3

RES

17 16 15 14 13 12 11

4 5 6 7

74LVC245A

7F01

+5VCA

+5V

+3V3

100n

2F04

+3V3

RES

100R3F05-4

17 16 15 14 13 12 11

7F02 74LVC245A

4 5 6 7

100n

2F06

RES

10K

3 6

10K

3F09-4

10K

3F09-2

3F09-3

10K

1 8

3F09-1

17 16 15 14 13 12 11

4 5 6 7

74LVC245A

7F03

RES

2F03

100n

+3V3

1X07

REF EMC HOLE

3F04-3 100R3 6

100R273F04-2

+3V3

12 11

5 6 7

17 16 15 14 13

74LVC245A

7F05

EMC HOLE

1X04

REF EMC HOLE

1X01

CA-RDY

CA-DATADIR

CA-DATAENn

CA-RST

CA-CD1n

CA-CD2n

CA-DATAENn

CA-DATADIR

CA-ADDENn

MOCLK

MOVAL

MOSTRT

MDO0

MDO1

MDO2

MDO3

MDO4

MDO5

MDO6

MDO7

CA-WAITn

CA-INPACKn

CA-WP

CA-VS1n

XIO-A11 XIO-A12 XIO-A13 XIO-A14

CA-ADDENn

CA-D00

CA-D01 CA-D02 CA-D03 CA-D04 CA-D05 CA-D06 CA-D07

CA-MOCLK

CA-MOVAL CA-MOSTRT

CA-MDO0

CA-MDO1 CA-MDO2 CA-MDO3 CA-MDO4

CA-MDO6

CA-MDO5

CA-MDO7

CA-A00

CA-A01 CA-A02 CA-A03 CA-A04 CA-A05 CA-A06 CA-A07

XIO-A00

XIO-A01 XIO-A02 XIO-A03 XIO-A04 XIO-A05 XIO-A06 XIO-A07

CA-ADDENn

CA-A08

CA-A09 CA-A10 CA-A11 CA-A12 CA-A13 CA-A14

XIO-A08

XIO-A09 XIO-A10

XIO-D02 XIO-D03 XIO-D04 XIO-D05 XIO-D06 XIO-D07

CA-REGn

CA-CE1n CA-CE2n

CA-OEn

CA-WEn CA-IORDn CA-IOWRn

XIO-D10

XIO-D11

XIO-D09 XIO-D08 XIO-OEn XIO-WEn XIO-D14 XIO-D15 CA-WAITn

CA-ADDENn

CA-RST

CA-VS1n

MOCLK

CA-WAITn

MOCLK

MOVAL

MOSTRT

MDO0

MDO1 MDO2 MDO3 MDO4 MDO5 MDO6 MDO7

XIO-D00

XIO-D01

CA-RDY

CA-WEn

CA-WP

CA-MISTRT CA-MDI0 CA-MDI1 CA-MDI2 CA-MDI3

CA-MDI4 CA-MDI5 CA-MDI6 CA-MDI7

MOSTRT

MOVAL

CA-CD1n

CA-CD2n

CA-CE2n

MDO2

MDO3 MDO4 MDO5 MDO6 MDO7

MDO0 MDO1

CA-INPACKn

CA-IORDn CA-IOWRn

CA-REGn

CA-A00

CA-A01

CA-A10

CA-A11

CA-A12

CA-A13 CA-A14

CA-MICLK

CA-MIVAL

CA-A02

CA-A03

CA-A04

CA-A05

CA-A06

CA-A07

CA-A08

CA-A09

CA-CE1n

CA-D00 CA-D01 CA-D02

CA-D03 CA-D04 CA-D05 CA-D06 CA-D07

CA-OEn

10. Circuit Diagrams and PWB Layouts

10-1 B01 310431365381

Common Interface

EN 92Q551.2E LA 10.

2011-Sep-09

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Page 93

Flash

19050_016_110419.eps

110419

Flash

B01B B01B

2011-03-07

3104 313 6538

SPB SSB

TV550 2K11 4DDR EU SD

VCC

VSS

0 1 2

4 5 6 7

CLE ALE CE RE

100n

2F20

+3V3

3F19

10K

100R3F22-4 4 5

3F22-1 100R1 8

100R3F22-33 6

3F22-2 100R

3F21-4 100R

100R3F21-2 2 7

3F20-4 100R45

100R3F21-33 6

1 8

3 6

3F21-1 100R

100R3F20-3

100R3F20-2

3F20-1 100R1 8

IF22

IF21

IF23

+3V3

2F21

100n

3F24

2K2

3F23 10K

18 19

46 47

4 5

6 10 11 14

27 28

33 34 35 38 39

40 45

15 20 21 22 23 24 25 26

17 9

30 31 32

41 42 43

4G × 16

[FLASH]

NAND04GW3B2DN6F

7F20

NAND-CE1n

NAND-RDY1n

NAND-WPn

XIO-D01

XIO-D00

XIO-D03

XIO-D02

XIO-D05

XIO-D04

XIO-D07

XIO-D06

NAND-ALE

NAND-CLE

XIO-OEn XIO-WEn

Circuit Diagrams and PWB Layouts

EN 93Q551.2E LA 10.

2011-Sep-09

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Page 94

USB Hub

19050_017_110419.eps

110419

USB Hub

B01C B01C

2011-03-07

3104 313 6538

SPB SSB

TV550 2K11 4DDR EU SD

SPI_SCK

SPI_SD

VIA

VCC

GND

XIN

XOUT

SELFPWR

VBUSPOWER

RESET

DD+

DD1DD1+

DD2DD2+

RES

GREEN1 AMBER1

GREEN2 AMBER2

PWR1

OVR1

PWR2

OVR2

SPI_CS

CY7C65621

9FLE 9FLC/D

N N

3FL4

Y N Y

9FL3

Y NCY7C65631

9F25/6

Y Y

9FL2

NNNN

USB1 (TOP)

USB2 (BOT)

1F24SCENARIO

Y N

Y2x USB + WIFI

2x USB

1x USB + WIFI

3F34

CY7C65621

7FL5

3FLG

1P08

3F323FL2

1P07

(WIFI)

9FLF/G

Y N

Y Y Y

9FLH/J

NNN N

9FLK/L

1x USB

3FL7

N Y N

1FL5

24M

2FL7

12p

100n

2FL4

3FLA 10K

FL32

100K

3FL4-1

100K

3FL4-3

3FL4-4

100K

3 4 5

FL33

USB-16-PBT-B-30-CU1-BRF

1P08 1 2

100n

2FL9

2FL8

+3V3

1u0

IFLD

10K

3FL7

IFLB

IFL2

10K

IFLA

+3V3

3FLF

3FLD

10K

3FLG

10K

+3V3 +3V3

12p

2FL6

+5V

+5V-USB1

3FLH

10K

3FLJ

0R4

RES

IFLG

9FLC

0R4

3FL2

2FLC

1n0

81 82

60 61 62 63 64 65 66

71 72 73 74 75 76

77 78 79 80

1923273339

67 68 69 70

25 48 49

35571115

1 2 44 43

53 51

6 42 41 54

475056

1216202428

FL30

7FL5

CY7C65621-56LTXCT

FL39

IFLC

FL38

10n

2FL5

100n

2FL2

100n

2FL1

IFLF

1n0

2FLB

100K

3FL4-2

2FLA

1n0

2FL3

10n

3FLE-2

100K

IFLE

IFL3

+3V3

IFL1

9FL2-33

9FL2-2

9FL2-1

9FL1-1RES 1 8

+3V3

+5V

IFL4

100K

3F34-1

+3V3

9FL2-4

10K3FLC

+5V-USB2

9FLD

FL42

9F26 9F25

3F34-4

+5V

100K

9FLK 9FLL

FL31

9FLH

9FLG

9FLF

1 2 3 4 5 67

RES

1F24

502386-0570

FL37

FL36

1P07 1 2 3 4 5

USB-16-PBT-B-30-CU1-BRF

FL40 FL41

100K

3F34-2

100K

+5V-USB2

+5V-USB1

3F34-3

3FLE-3

100K

3FLE-4

100K

9FLJ

100K

3FLE-1

9FL3

2FLD

10n

9FLE

RES 4 5

15K

9FL1-4

RES 3 6

3FLB

RES 2 7

9FL1-3

9FL1-2

3F32

+5V

+3V3

FL430R4

USB2-DP

USB2-DM

+3V3-1

USB2-DP USB-WIFI-DDn

USB-WIFI-DDp

USB-OVR1

USB1-DM USB1-DP

USB2-DM USB2-DP

RESET-USBn USB1-DM USB1-DP USB-DM USB-DP

USB-WIFI-DDn USB-WIFI-DDp

USB2-DM

Circuit Diagrams and PWB Layouts

EN 94Q551.2E LA 10.

2011-Sep-09

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Page 95

SD Card

19050_018_110419.eps

110419

SD-Card

B01D B01D

2011-03-07

3104 313 6538

SPB SSB

TV550 2K11 4DDR EU SD

3F45

10K

47K

3F41-2

RES

+3V3-SD

100R

3F44-2

100R

3F43-2

FF50

FF43

+3V3-SD

16V22u

2F40

FF41

FF48

100R

3F44-1

1 8

3 6

10 11 12

3F43-3

100R

1P09-2

SCDA7A0200

+3V3

FF45

3F42-1

47K

3F42-3

47K

3 6

47K

3 6

3F41-4

47K

3F41-3

1 8

0R4

3F40

47K

3F41-1

IF47

FF44

+3V3

FF42

FF49

FF47

100R

3F43-4

3F44-4

13 14

100R

1 2

4 5 6 7

1P09-1

SCDA7A0200

FF46

SDIO-CLK

47K

3F42-2

SDIO-DAT3

SDIO-CMD

SDIO-CLK

SDIO-DAT0

SDIO-DAT1

SDIO-DAT2

SDIO-CDn

SDIO-WP

SDIO-DAT3

SDIO-CMD

SDIO-DAT0

SDIO-DAT1

SDIO-DAT2

SDIO-CDn

SDIO-WP

Circuit Diagrams and PWB Layouts

EN 95Q551.2E LA 10.

2011-Sep-09

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Page 96

PNX85500 Control

19050_020_110420.eps

110420

PNX85500-Control

B01E B01E

2011-03-07

3104 313 6538

SPB SSB

TV550 2K11 4DDR EU SD

HOLD

VSS

VCC

SCL

ADR

0 1 2 SDA

MAIN NVM

SCL

FOR

DEBUG

SDA

DEBUG ONLY

DEBUG / RS232 INTERFACE

SHIFTED

USE ONLY

LEVEL

FF61

3F63

+3V3-STANDBY

100R

3F58

10K

3F59

3F60

100R

IF51

IF59

FF55

IF52

+3V3

IF50

+3V3-STANDBY

RES

2F58

100n

+3V3-STANDBY

10K

3F67

+5V

RES

100n

2F52

10K

3F53

IF56

IF57

IF53

10K

3F69

RES

7F52 M25P05-AVMN6

FLASH

512K

FF04

RES7F54-1

BC847BPN(COL)

FF66

100R

3F65

IF54

FF64

FF63

FF62

3F62

100R

RES

7F54-2

BC847BPN(COL)

RES

1 2

FF29

1F52

IF61

FF57

+3V3

FF65

RES

47K

3F68

FF56

RES

1 2

4 5

IF55

1F51

9CH0

(8K × 8)

1 2

EEPROM

7F58

10K

3F52

3F54

1K0

RES

2F49

100p

IF62

+3V3

RES

1u0

2F53

10K

3F66

+3V3

RES

PDTA114EU

7F53

3F64

IF58

100R

FF58

TXD-UP

RXD-UP

BOOST-PWM

BACKLIGHT-BOOST

SPI-PROG

SDM

RESET-STBYn SPI-PROG

PNX-SPI-CLK

PNX-SPI-SDOPNX-SPI-SDI

PNX-SPI-CSBn

PNX-SPI-WPn

SDA-UP-MIPS

SCL-UP-MIPS

SCL-SSB

SDA-SSB

Circuit Diagrams and PWB Layouts

EN 96Q551.2E LA 10.

2011-Sep-09

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Page 97

Tuner

19050_021_110420.eps

110420

Tuner

B01F B01F

2011-03-07

3104 313 6538

SPB SSB

TV550 2K11 4DDR EU SD

AGC CONTROL

O2ISWI

GND

22p

1p0

12p

15p 2F80 15p 2F77

820n

680n

2F73 1p0

2F72

12p

5p6

Used

2F62

RES

10p

Used

5F74

560n

9F06

Remarks

2F82

9F03

Component

Europe

Brazil

FA23X7

18p

5F71 680n

RES

For BR NIM Tuner only

Item No.

1T01

9F04

Used

RES

2F61

TH26X3

9F02

RES

Used

9F05 RES

For EU Hybrid Tuner only

4u7

RES

6p8

RES

IF76

2F9A

IF80

47R

3F75

2F82

330n

5F76RES

2F86

15p

9F03

IF75

IF81

RES5F72

30R

AF73

2 INPUT1

3 INPUT2

7OUTPUT1

OUTPUT2

4 VAGC

VCC

7F75 UPC3221GV-E1

GND15GND2

2F79

10n

2F75

FF82

10n

2F78

2F74

10n

2F66

15p

3F77

4K7

RES

FF01

15p

2F65

3F81 220R

FF00

3F80 220R

2F98

6p8

RES

3F79-4

220R

6p8

2F9D

2F9C

6p8

RES

6p8

2F9BRES

2F76

RES

2p2

6p8

2F99RES

RES 2F97

6p8

9F01

9F00

IF74

9F06

IF72

FF74

AF70

AF71

100p

2F95RES

IF90

IF89

9F71

5F71

2F72

10n

2F94 RES

3K3

3F78

+5V-TUN-PIN

10n

2F91

2F90

10n

RES

FF81

5F73

ATB2012

4n72F59

2F70

1p0

RES

3F76

47R

1K0

3F71

3F72

4K7

2F73

2F60 100n

FF71

+5V-TUN-PIN

IF15

FF76

IF11

IF10

IF82

IF16

10n

2F64

IF12

2F80

IF78

IF86

IF77

AF72

4n72F81

IF88

IF73

RES

RF_AGC

RF_IO

TUN

B+_TUN

I2C_ADR5I2C_SCL

I2C_SDA

IF_OUT111IF_OUT2

1415

4MHZ_REF

B+_LNA

TUNER

1T01

+5V-TUN-PIN

2F85

47n

5 4

5F66

680n

36M17

1 2

9F05

X7251M

1F75

+5V-TUN

IF79

2F96

100p

RES

2F71

10n

+5V-TUN-PIN

RES

IF87

820R

3F82

7F70

PDTC114EU

2F92

10n

6F72

BA591

2F61

100n

2F93

5F70

FF75

470n

22u

2F88

IF13

IF14

220R

3F79-1

2F62

5F74

2F77

10n

2F63

15p

2F84

9F02

IF-AGC

IF+

IF-

RF-AGC

9F04

TUN-P1

TUN-IF-P

TUN-IF-N

TUN-IF-P

TUN-IF-N

IF-AGC

IF-P-DVBT2

IF-N-DVBT2

PNX-IF-AGC

SCL-TUNER

TUN-P6

SDA-TUNER

TUN-P7

PNX-IF-P

PNX-IF-N

TUN-P7

TUN-P6

SELECT-SAW

Circuit Diagrams and PWB Layouts

EN 97Q551.2E LA 10.

2011-Sep-09

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Page 98

Toshiba Supply

19050_022_110420.eps

110420

Toshiba supply

B01G B01G

2011-03-07

3104 313 6538

SPB SSB

TV550 2K11 4DDR EU SD

COM

OUTIN

* FOR DVBT-2

+3V3

+1V2-BRA-VDDC

+1V2-BRA-DR1

+1V2-FE

5FA4

30R

5FA3

10u

2FA4

2FA3

100n

FFAF

FFA2

LD1117DT12

7FA3

100n

2FA2

Circuit Diagrams and PWB Layouts

EN 98Q551.2E LA 10.

2011-Sep-09

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Page 99

HDMI

19050_023_110420.eps

110420

HDMI

B01H B01H

2011-03-07

3104 313 6538

SPB SSB

TV550 2K11 4DDR EU SD

HDMI CONNECTOR SIDE

47K

3FBF-2

DIN-5V

3FBF-1

47K

DIN-5V

FFB5

FFB4

FFB6

FFB3

FFB1 FFB2

2 3 4 5 6 7 8 9

2021 22

10 11 12 13 14 15 16 17 18

1P05

DRX1-

DRX0+

DRX0-

DRX-DDC-SCL DRX-DDC-SDA

DRX2+

DRXC+

DRXC-

PCEC-HDMI

DRX-DDC-SCL DRX-DDC-SDA

DRX-HOTPLUG

DRX2-

DRX1+

Circuit Diagrams and PWB Layouts

EN 99Q551.2E LA 10.

2011-Sep-09

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Page 100

VGA

19050_024_110420.eps

110420

VGA

B01I B01I

2011-03-07

3104 313 6538

SPB SSB

TV550 2K11 4DDR EU SD

VGA

CONNECTOR

FFC7

3FC7

18R

3FC6

FFC3

6FC8

RES

1FC2

12V

CDS4C12GTA

1FC6

4 5 6 7

1216-02D-15L-2EC

10 11 12 13 14

1E05

RES

9FC4

RES

9FC2

9FC1

FFC4

FFC8

FFC1

12V

RES

CDS4C12GTA

6FC6

RES

3FC2

10K

12V

CDS4C12GTA

6FC2

3FC4

4K7

RES

4K7

3FC3

RES

100p

2FC3 2FC1

100p

RES2FC2

100p

RES

6FC5

CDS4C12GTA

12V

CDS4C12GTA

6FC3

RES

12V

RESRES

12V

CDS4C12GTA

6FC4

RES

12V

CDS4C12GTA

6FC1

FFC5

9FC5

9FC6

1FC4

47p

2FC4

3FC5

18R

1FC5

2FC5

47p

1FC3

FFC2

2FC8

47p

1FC1

9FC3

47p

2FC7 2FC6

47p

FFC9

FFC6

6FC7

CDS4C12GTA

12V

RES

10K

3FC1

VGA-SCL-EDID

VGA-SDA-EDID

R-VGA

H-SYNC-VGA

V-SYNC-VGA

G-VGA

B-VGA

+5V-VGA

VGA-SDA-EDID-HDMI

VGA-SCL-EDID-HDMI

Circuit Diagrams and PWB Layouts

EN 100Q551.2E LA 10.

2011-Sep-09

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div. table