Philips 32PFL3605D, 40PFL3605D Schematic

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Colour Television Chassis
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Contents Page Contents Page

1. Revision List 2
2. Technical Specifications and Connections 2
3. Precautions, Notes, and Abbreviation List 4
4. Mechanical Instructions 8
5. Service Modes, Error Codes, and Fault Finding 13
6. Alignments 19
7. Circuit Descriptions 21
8. IC Data Sheets 27
9. Block Diagrams Wiring Diagram 32" - 40" (Dali) 37 Block Diagram Video 38 Block Diagram Audio 39 Block Diagram Control & Clock Signals 40 Block Diagram I2C 41 Supply Lines Overview 42
10. Circuit Diagrams and PWB Layouts Diagram PWB SSB: DC-DC SSB: Tuner (B02A) 44 63-64 SSB: Digital Demodulator (B02B) 45 63-64 SSB: Class-D & Muting (B03) 46 63-64 SSB: MTK Power (B04A) 47 63-64 SSB: DDR (B04B) 48 63-64 SSB: Controller (B04C) 49 63-64 SSB: LVDS Display (B04D) 50 63-64 SSB: HDMI & Multiplexer (B05) 51 63-64 SSB: Analog I/O - Headphone (B06A) 52 63-64 SSB: Analog I/O - Audio (B06B) 53 63-64 SSB: Analog I/O - Video (B06C) 54 63-64 SSB: USB (B06D) 55 63-64 SSB: VGA (B06E) 56 63-64 SSB: Hospitality (B07) 57 63-64 SSB: TCON Control (B08A) 58 63-64 SSB: TCON DC/DC (B08B) 59 63-64 SSB: P Gamma, VCOM & NVM (B08C) 60 63-64
©
Copyright 2010 Koninklijke Philips Electronics N.V. All rights reserved. No part of this publication may be reproduced, stored in a retrieval system or transmitted, in any form or by any means, electronic, mechanical, photocopying, or otherwise without the prior permission of Philips.
(B01) 43 63-64
SSB: MPD (B08D) 61 63-64 SSB: Mini LVDS (B08E) 62 63-64 SSB: SRP List Explanation 65 SSB: SRP List 66 IR/LED Board (J) 68 68 Keyboard Control Board (E) 69 70
11. Styling Sheets Styling Sheet Dali 32" - 40" 71
Published by JA/JY 1064 BU TV Consumer Care Printed in the Netherlands Subject to modification EN 3122 785 18980
2010-Apr-06
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Bottom connector
Side connector
Back connector
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Revision List

1. Revision List

Manual xxxx xxx xxxx.0
• First release.

2. Technical Specifications and Connections

Index of this chapter:
2.1
Technical Specifications

2.2 Directions for Use

2.3 Connections

Notes:
• Figures can deviate due to the different set executions.
• Specifications are indicative (subject to change).

2.1 Technical Specifications

For on-line product support please use the links in Table 2-1. Here is product information available, as well as getting started, user manuals, frequently asked questions and software & drivers.
2.3 Connections

Table 2-1 Described Model numbers

CTN Styling Published in:
32PFL3605D/78
40PFL3605D/78
Dali 3122 785 18980
2.2 Directions for Use
You can download this information from the following websites:
http://www.philips.com/support http://www.p4c.philips.com
Note: The following connector colour abbreviations are used (according to DIN/IEC 757): Bk= Black, Bu= Blue, Gn= Green, Gy= Grey, Rd= Red, Wh= White, Ye= Yellow.
2010-Apr-06

Figure 2-1 Connection overview

2.3.1 Side Connections

1 - USB2.0
Figure 2-2 USB (type A)
1-+5V k 2 - Data (-) jk 3 - Data (+) jk 4 - Ground Gnd H
2 - HDMI: Digital Video/Audio - In (see HDMI 1)
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Technical Specifications and Connections
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2.3.2 Back Connections

3 - CVI-1: Cinch: Video YPbPr - In, Audio - In
Wh - Audio - L 0.5 V Rd - Audio - R 0.5 V Rd - Video Pr 0.7 V Bu - Video Pb 0.7 V Gn - Video Y 1 V
/ 10 kΩ jq
RMS
/ 10 kΩ jq
RMS
/ 75 Ω jq
PP
/ 75 Ω jq
PP
/ 75 Ω jq
PP
4 - Service Connector (UART)
1 - Ground Gnd H 2 - UART_TX Transmit k 3 - UART_RX Receive j
5 - AV IN: S-Video (Hosiden): Video Y/C - In
1 - Ground Y Gnd H 2 - Ground C Gnd H 3 - Video Y 1 V 4 - Video C 0.3 V
/ 75 Ω j
PP
/ 75 Ω j
PP
5 - AV IN: Cinch: Video CVBS - In, Audio - In
Ye - Video CVBS 1 V Wh - Audio L 0.5 V Rd - Audio R 0.5 V
/ 75 ohm jq
PP
/ 10 kohm jq
RMS
/ 10 kohm jq
RMS

2.3.3 Bottom Connections

6 - CVI-2: Cinch: Video YPbPr - In, Audio - In
Wh - Audio - L 0.5 V Rd - Audio - R 0.5 V Rd - Video Pr 0.7 V Bu - Video Pb 0.7 V Gn - Video Y 1 V
/ 10 kΩ jq
RMS
/ 10 kΩ jq
RMS
/ 75 Ω jq
PP
/ 75 Ω jq
PP
/ 75 Ω jq
PP
9 - VGA: Video RGB - In
Figure 2-4 VGA Connector
1 - Video Red 0.7 V 2 - Video Green 0.7 V 3 - Video Blue 0.7 V 4-n.c.
/ 75 Ω j
PP
/ 75 Ω j
PP
/ 75 Ω j
PP
5 - Ground Gnd H 6 - Ground Red Gnd H 7 - Ground Green Gnd H 8 - Ground Blue Gnd H 9-+5V 10 - Ground Sync Gnd H
+5 V j
DC
11 - n.c. 12 - DDC_SDA DDC data j 13 - H-sync 0 - 5 V j 14 - V-sync 0 - 5 V j 15 - DDC_SCL DDC clock j
10 - Aerial - In
- - F-type Coax, 75 Ω D
7 - Cinch: Digital Audio - Out
Bk - Coaxial 0.4 - 0.6V
/ 75 ohm kq
PP
8 - HDMI 1: Digital Video, Digital Audio - In
Figure 2-3 HDMI (type A) connector
1 - D2+ Data channel j 2 - Shield Gnd H 3 - D2- Data channel j 4 - D1+ Data channel j 5 - Shield Gnd H 6 - D1- Data channel j 7 - D0+ Data channel j 8 - Shield Gnd H 9 - D0- Data channel j 10 - CLK+ Data channel j 11 - Shield Gnd H 12 - CLK- Data channel j 13 - Easylink Control channel/CEC jk 14 - n.c. 15 - DDC_SCL DDC clock j 16 - DDC_SDA DDC data jk 17 - Ground Gnd H 18 - +5V j 19 - HPD Hot Plug Detect j 20 - Ground Gnd H
9 - Mini Jack: Audio - In DVI/VGA
Bk - Audio 0.5 V
RMS
/ 10 kΩ jo
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Precautions, Notes, and Abbreviation List

3. Precautions, Notes, and Abbreviation List

Index of this chapter:
3.1
Safety Instructions

3.2 Warnings

3.3 Notes

3.4 Abbreviation List

3.1 Safety Instructions

Safety regulations require the following during a repair:
• Connect the set to the Mains/AC Power via an isolation transformer (> 800 VA).
• Replace safety components, indicated by the symbol h, only by components identical to the original ones. Any other component substitution (other than original type) may increase risk of fire or electrical shock hazard. Of de set ontploft!
Safety regulations require that after a repair, the set must be returned in its original condition. Pay in particular attention to the following points:
• Route the wire trees correctly and fix them with the mounted cable clamps.
• Check the insulation of the Mains/AC Power lead for external damage.
• Check the strain relief of the Mains/AC Power cord for proper function.
• Check the electrical DC resistance between the Mains/AC Power plug and the secondary side (only for sets that have a Mains/AC Power isolated power supply):
1. Unplug the Mains/AC Power cord and connect a wire
between the two pins of the Mains/AC Power plug.
2. Set the Mains/AC Power switch to the “on” position
(keep the Mains/AC Power cord unplugged!).
3. Measure the resistance value between the pins of the
Mains/AC Power plug and the metal shielding of the tuner or the aerial connection on the set. The reading should be between 4.5 MΩ and 12 MΩ.
4. Switch “off” the set, and remove the wire between the
two pins of the Mains/AC Power plug.
• Check the cabinet for defects, to prevent touching of any inner parts by the customer.
picture carrier at 475.25 MHz for PAL, or 61.25 MHz for NTSC (channel 3).
• Where necessary, measure the waveforms and voltages
with (D) and without (E) aerial signal. Measure the voltages in the power supply section both in normal operation (G) and in stand-by (F). These values are indicated by means of the appropriate symbols.

3.3.2 Schematic Notes

• All resistor values are in ohms, and the value multiplier is often used to indicate the decimal point location (e.g. 2K2 indicates 2.2 kΩ).
• Resistor values with no multiplier may be indicated with either an “E” or an “R” (e.g. 220E or 220R indicates 220 Ω).
• All capacitor values are given in micro-farads (μ=× 10 nano-farads (n =× 10
• Capacitor values may also use the value multiplier as the decimal point indication (e.g. 2p2 indicates 2.2 pF).
• An “asterisk” (*) indicates component usage varies. Refer to the diversity tables for the correct values.
• The correct component values are listed on the Philips Spare Parts Web Portal.

3.3.3 Spare Parts

For the latest spare part overview, consult your Philips Spare Part web portal.

3.3.4 BGA (Ball Grid Array) ICs

Introduction
For more information on how to handle BGA devices, visit this URL: http://www.atyourservice-magazine.com “Magazine”, then go to “Repair downloads”. Here you will find Information on how to deal with BGA-ICs.
BGA Temperature Profiles
For BGA-ICs, you must use the correct temperature-profile. Where applicable and available, this profile is added to the IC Data Sheet information section in this manual.
-9
), or pico-farads (p =× 10
. Select
-12
-6
),
).
3.2 Warnings
• All ICs and many other semiconductors are susceptible to
electrostatic discharges (ESD w). Careless handling during repair can reduce life drastically. Make sure that, during repair, you are connected with the same potential as the mass of the set by a wristband with resistance. Keep components and tools also at this same potential.
• Be careful during measurements in the high voltage section.
• Never replace modules or other components while the unit is switched “on”.
• When you align the set, use plastic rather than metal tools. This will prevent any short circuits and the danger of a circuit becoming unstable.
3.3 Notes

3.3.1 General

• Measure the voltages and waveforms with regard to the chassis (= tuner) ground (H), or hot ground (I), depending on the tested area of circuitry. The voltages and waveforms shown in the diagrams are indicative. Measure them in the Service Default Mode with a colour bar signal and stereo sound (L: 3 kHz, R: 1 kHz unless stated otherwise) and

3.3.5 Lead-free Soldering

Due to lead-free technology some rules have to be respected by the workshop during a repair:
• Use only lead-free soldering tin. If lead-free solder paste is required, please contact the manufacturer of your soldering equipment. In general, use of solder paste within workshops should be avoided because paste is not easy to store and to handle.
• Use only adequate solder tools applicable for lead-free soldering tin. The solder tool must be able: – To reach a solder-tip temperature of at least 400°C. – To stabilize the adjusted temperature at the solder-tip. – To exchange solder-tips for different applications.
• Adjust your solder tool so that a temperature of around 360°C - 380°C is reached and stabilized at the solder joint. Heating time of the solder-joint should not exceed ~ 4 sec. Avoid temperatures above 400°C, otherwise wear-out of tips will increase drastically and flux-fluid will be destroyed. To avoid wear-out of tips, switch “off” unused equipment or reduce heat.
• Mix of lead-free soldering tin/parts with leaded soldering tin/parts is possible but PHILIPS recommends strongly to avoid mixed regimes. If this cannot be avoided, carefully clear the solder-joint from old tin and re-solder with new tin.
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Precautions, Notes, and Abbreviation List
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3.3.6 Alternative BOM identification

It should be noted that on the European Service website, “Alternative BOM” is referred to as “Design variant”.
The third digit in the serial number (example: AG2B0335000001) indicates the number of the alternative B.O.M. (Bill Of Materials) that has been used for producing the specific TV set. In general, it is possible that the same TV model on the market is produced with e.g. two different types of displays, coming from two different suppliers. This will then result in sets which have the same CTN (Commercial Type Number; e.g. 28PW9515/12) but which have a different B.O.M. number. By looking at the third digit of the serial number, one can identify which B.O.M. is used for the TV set he is working with. If the third digit of the serial number contains the number “1” (example: AG1B033500001), then the TV set has been manufactured according to B.O.M. number 1. If the third digit is a “2” (example: AG2B0335000001), then the set has been produced according to B.O.M. no. 2. This is important for ordering the correct spare parts! For the third digit, the numbers 1...9 and the characters A...Z can be used, so in total: 9 plus 26= 35 different B.O.M.s can be indicated by the third digit of the serial number.
Identification: The bottom line of a type plate gives a 14-digit serial number. Digits 1 and 2 refer to the production centre (e.g. AG is Bruges), digit 3 refers to the B.O.M. code, digit 4 refers to the Service version change code, digits 5 and 6 refer to the production year, and digits 7 and 8 refer to production week (in example below it is 2006 week 17). The 6 last digits contain the serial number.
MODEL :
PROD.NO:
32PF9968/10
AG 1A0617 000001
MADE IN BELGIUM
220-240V 50/60Hz
VHF+S+H+UHF
S
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Figure 3-1 Serial number (example)

3.3.7 Board Level Repair (BLR) or Component Level Repair (CLR)

If a board is defective, consult your repair procedure to decide if the board has to be exchanged or if it should be repaired on component level. If your repair procedure says the board should be exchanged completely, do not solder on the defective board. Otherwise, it cannot be returned to the O.E.M. supplier for back charging!

3.3.8 Practical Service Precautions

• It makes sense to avoid exposure to electrical shock.
While some sources are expected to have a possible dangerous impact, others of quite high potential are of limited current and are sometimes held in less regard.
• Always respect voltages. While some may not be
dangerous in themselves, they can cause unexpected reactions that are best avoided. Before reaching into a powered TV set, it is best to test the high voltage insulation. It is easy to do, and is a good service precaution.
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3.4 Abbreviation List

0/6/12 SCART switch control signal on A/V
board. 0 = loop through (AUX to TV), 6 = play 16 : 9 format, 12 = play 4 : 3 format
AARA Automatic Aspect Ratio Adaptation:
algorithm that adapts aspect ratio to remove horizontal black bars; keeps the original aspect ratio
ACI Automatic Channel Installation:
algorithm that installs TV channels directly from a cable network by
means of a predefined TXT page ADC Analogue to Digital Converter AFC Automatic Frequency Control: control
signal used to tune to the correct
frequency AGC Automatic Gain Control: algorithm that
controls the video input of the feature
box AM Amplitude Modulation AP Asia Pacific AR Aspect Ratio: 4 by 3 or 16 by 9 ASF Auto Screen Fit: algorithm that adapts
aspect ratio to remove horizontal black
bars without discarding video
information ATSC Advanced Television Systems
Committee, the digital TV standard in
the USA ATV See Auto TV Auto TV A hardware and software control
system that measures picture content,
and adapts image parameters in a
dynamic way AV External Audio Video AVC Audio Video Controller AVIP Audio Video Input Processor B/G Monochrome TV system. Sound
carrier distance is 5.5 MHz BDS Business Display Solutions (iTV) BLR Board-Level Repair BTSC Broadcast Television Standard
Committee. Multiplex FM stereo sound
system, originating from the USA and
used e.g. in LATAM and AP-NTSC
countries B-TXT Blue TeleteXT C Centre channel (audio) CEC Consumer Electronics Control bus:
remote control bus on HDMI
connections CL Constant Level: audio output to
connect with an external amplifier CLR Component Level Repair ComPair Computer aided rePair CP Connected Planet / Copy Protection CSM Customer Service Mode CTI Color Transient Improvement:
manipulates steepness of chroma
transients CVBS Composite Video Blanking and
Synchronization DAC Digital to Analogue Converter DBE Dynamic Bass Enhancement: extra
low frequency amplification DCM Data Communication Module. Also
referred to as System Card or
Smartcard (for iTV). DDC See “E-DDC” D/K Monochrome TV system. Sound
carrier distance is 6.5 MHz DFI Dynamic Frame Insertion
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DFU Directions For Use: owner's manual DMR Digital Media Reader: card reader DMSD Digital Multi Standard Decoding DNM Digital Natural Motion DNR Digital Noise Reduction: noise
reduction feature of the set DRAM Dynamic RAM DRM Digital Rights Management DSP Digital Signal Processing DST Dealer Service Tool: special remote
control designed for service
technicians DTCP Digital Transmission Content
Protection; A protocol for protecting
digital audio/video content that is
traversing a high speed serial bus,
such as IEEE-1394 DVB-C Digital Video Broadcast - Cable DVB-T Digital Video Broadcast - Terrestrial DVD Digital Versatile Disc DVI(-d) Digital Visual Interface (d= digital only) E-DDC Enhanced Display Data Channel
(VESA standard for communication
channel and display). Using E-DDC,
the video source can read the EDID
information form the display. EDID Extended Display Identification Data
(VESA standard) EEPROM Electrically Erasable and
Programmable Read Only Memory EMI Electro Magnetic Interference EPG Electronic Program Guide EPLD Erasable Programmable Logic Device EU Europe EXT EXTernal (source), entering the set by
SCART or by cinches (jacks) FDS Full Dual Screen (same as FDW) FDW Full Dual Window (same as FDS) FLASH FLASH memory FM Field Memory or Frequency
Modulation FPGA Field-Programmable Gate Array FTV Flat TeleVision Gb/s Giga bits per second G-TXT Green TeleteXT H H_sync to the module HD High Definition HDD Hard Disk Drive HDCP High-bandwidth Digital Content
Protection: A “key” encoded into the
HDMI/DVI signal that prevents video
data piracy. If a source is HDCP coded
and connected via HDMI/DVI without
the proper HDCP decoding, the
picture is put into a “snow vision” mode
or changed to a low resolution. For
normal content distribution the source
and the display device must be
enabled for HDCP “software key”
decoding. HDMI High Definition Multimedia Interface HP HeadPhone I Monochrome TV system. Sound
2
I
C Inter IC bus
2
I
D Inter IC Data bus
2
I
S Inter IC Sound bus
carrier distance is 6.0 MHz
IF Intermediate Frequency IR Infra Red IRQ Interrupt Request ITU-656 The ITU Radio communication Sector
(ITU-R) is a standards body
subcommittee of the International
Telecommunication Union relating to
radio communication. ITU-656 (a.k.a.
SDI), is a digitized video format used for broadcast grade video. Uncompressed digital component or digital composite signals can be used. The SDI signal is self-synchronizing, uses 8 bit or 10 bit data words, and has a maximum data rate of 270 Mbit/s, with a minimum bandwidth of 135 MHz.
ITV Institutional TeleVision; TV sets for
hotels, hospitals etc.
LS Last Status; The settings last chosen
by the customer and read and stored in RAM or in the NVM. They are called at start-up of the set to configure it according to the customer's
preferences LATAM Latin America LCD Liquid Crystal Display LED Light Emitting Diode L/L' Monochrome TV system. Sound
carrier distance is 6.5 MHz. L' is Band
I, L is all bands except for Band I LPL LG.Philips LCD (supplier) LS Loudspeaker LVDS Low Voltage Differential Signalling Mbps Mega bits per second M/N Monochrome TV system. Sound
carrier distance is 4.5 MHz MHEG Part of a set of international standards
related to the presentation of
multimedia information, standardised
by the Multimedia and Hypermedia
Experts Group. It is commonly used as
a language to describe interactive
television services MIPS Microprocessor without Interlocked
Pipeline-Stages; A RISC-based
microprocessor MOP Matrix Output Processor MOSFET Metal Oxide Silicon Field Effect
Transistor, switching device MPEG Motion Pictures Experts Group MPIF Multi Platform InterFace MUTE MUTE Line MTV Mainstream TV: TV-mode with
Consumer TV features enabled (iTV) NC Not Connected NICAM Near Instantaneous Compounded
Audio Multiplexing. This is a digital
sound system, mainly used in Europe. NTC Negative Temperature Coefficient,
non-linear resistor NTSC National Television Standard
Committee. Color system mainly used
in North America and Japan. Color
carrier NTSC M/N= 3.579545 MHz,
NTSC 4.43= 4.433619 MHz (this is a
VCR norm, it is not transmitted off-air) NVM Non-Volatile Memory: IC containing
TV related data such as alignments O/C Open Circuit OSD On Screen Display OAD Over the Air Download. Method of
software upgrade via RF transmission.
Upgrade software is broadcasted in
TS with TV channels. OTC On screen display Teletext and
Control; also called Artistic (SAA5800) P50 Project 50: communication protocol
between TV and peripherals PAL Phase Alternating Line. Color system
mainly used in West Europe (color
carrier= 4.433619 MHz) and South
America (color carrier PAL M=
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3.575612 MHz and PAL N= 3.582056
MHz) PCB Printed Circuit Board (same as “PWB”) PCM Pulse Code Modulation PDP Plasma Display Panel PFC Power Factor Corrector (or Pre-
conditioner) PIP Picture In Picture PLL Phase Locked Loop. Used for e.g.
FST tuning systems. The customer
can give directly the desired frequency POD Point Of Deployment: a removable
CAM module, implementing the CA
system for a host (e.g. a TV-set) POR Power On Reset, signal to reset the uP PSDL Power Supply for Direct view LED
backlight with 2D-dimming PSL Power Supply with integrated LED
drivers PSLS Power Supply with integrated LED
drivers with added Scanning
functionality PTC Positive Temperature Coefficient,
non-linear resistor PWB Printed Wiring Board (same as “PCB”) PWM Pulse Width Modulation QRC Quasi Resonant Converter QTNR Quality Temporal Noise Reduction QVCP Quality Video Composition Processor RAM Random Access Memory RGB Red, Green, and Blue. The primary
color signals for TV. By mixing levels
of R, G, and B, all colors (Y/C) are
reproduced. RC Remote Control RC5 / RC6 Signal protocol from the remote
control receiver RESET RESET signal ROM Read Only Memory RSDS Reduced Swing Differential Signalling
data interface R-TXT Red TeleteXT SAM Service Alignment Mode S/C Short Circuit SCART Syndicat des Constructeurs
d'Appareils Radiorécepteurs et
Téléviseurs SCL Serial Clock I SCL-F CLock Signal on Fast I SD Standard Definition SDA Serial Data I SDA-F DAta Signal on Fast I
2
C
2
C bus
2
C
2
C bus SDI Serial Digital Interface, see “ITU-656” SDRAM Synchronous DRAM SECAM SEequence Couleur Avec Mémoire.
Color system mainly used in France and East Europe. Color carriers=
4.406250 MHz and 4.250000 MHz SIF Sound Intermediate Frequency SMPS Switched Mode Power Supply SoC System on Chip SOG Sync On Green SOPS Self Oscillating Power Supply SPI Serial Peripheral Interface bus; a 4-
wire synchronous serial data link
standard S/PDIF Sony Philips Digital InterFace SRAM Static RAM SRP Service Reference Protocol SSB Small Signal Board SSC Spread Spectrum Clocking, used to
reduce the effects of EMI STB Set Top Box STBY STand-BY SVGA 800 × 600 (4:3)
SVHS Super Video Home System SW Software SWAN Spatial temporal Weighted Averaging
Noise reduction SXGA 1280 × 1024 TFT Thin Film Transistor THD Total Harmonic Distortion TMDS Transmission Minimized Differential
Signalling TS Transport Stream TXT TeleteXT TXT-DW Dual Window with TeleteXT UI User Interface uP Microprocessor UXGA 1600 × 1 200 (4:3) V V-sync to the module VESA Video Electronics Standards
Association VGA 640 × 480 (4:3) VL Variable Level out: processed audio
output toward external amplifier VSB Vestigial Side Band; modulation
method WYSIWYR What You See Is What You Record:
record selection that follows main
picture and sound WXGA 1280 × 768 (15:9) XTAL Quartz crystal XGA 1 024 × 768 (4:3) Y Luminance signal Y/C Luminance (Y) and Chrominance (C)
signal YPbPr Component video. Luminance and
scaled color difference signals (B-Y
and R-Y) YUV Component video
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4. Mechanical Instructions

Index of this chapter:
4.1
Cable Dressing
4.2 Service Positions
4.3 Assy/Panel Removal
4.4 Set Re-assembly

4.1 Cable Dressing

Notes:
• Figures below can deviate slightly from the actual situation, due to the different set executions.

Figure 4-1 Cable dressing 32"

Figure 4-2 Adding felt on front cabinet 32"

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FELT (145 x 7 x 0.9)
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Figure 4-3 Cable dressing 40"

Figure 4-4 Adding felt on front cabinet 40"

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Mechanical Instructions

4.2 Service Positions

For easy servicing of a TV set, the set should be put face down on a soft flat surface, foam buffers or other specific workshop tools. Ensure that a stable situation is created to perform measurements and alignments. When using foam bars take care that these always support the cabinet and never only the display. Caution: Failure to follow these guidelines can seriously damage the display! Ensure that ESD safe measures are taken.

4.3 Assy/Panel Removal

Instructions below apply to the 32PFL3605D/xx, but will be similar for other models.

4.3.1 Rear Cover

Warning: Disconnect the mains power cord before you remove
the rear cover. Note: it is not necessary to remove the stand while removing the rear cover.
1. Remove all screws of the rear cover.
2. Lift the rear cover from the TV. Make sure that wires and flat coils are not damaged while lifting the rear cover from the set.

4.3.2 Rear Cover

Warning: Disconnect the mains power cord before removing
the rear cover. See Figure 4-5
1. Remove fixation screws [2] and [3] that secure the rear cover. It is not necessary to remove the stand first [1].
2. Lift the rear cover from the TV. Make sure that wires and flat foils are not damaged while lifting the rear cover from the set.
2010-Apr-06
.
Figure 4-5 Rear cover removal (32")

4.3.3 Speakers

Tweeters (when applicable)
Each tweeter unit is mounted with one screw. When defective, replace the whole unit.
Loudspeaker/subwoofer
The loudspeaker/subwoofer is located in the centre of the set, and is fixed with two screws. When defective, replace the whole unit.
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4.3.4 Main Power Supply

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Figure 4-6 Main Power Supply
Mechanical Instructions
Figure 4-8 Keyboard Control Board - 1 -
EN 11LC10.1L LA 4.
1. Unplug all connectors [1].
2. Remove the fixation screws [2].
3. Take the board out. When defective, replace the whole unit.
Be aware to (re)place the spacers [3].

4.3.5 Small Signal Board (SSB)

Refer to next figure for details.
Figure 4-9 Keyboard Control Board - 2 -

4.3.7 IR/LED Board

Refer to next figure for details.
Figure 4-7 SSB
1. Unplug all connectors [1] and [2].
2. Remove the fixation screws [3].
3. Take the board out. When defective, replace the whole unit.

4.3.6 Local Control Board

Refer to next figure for details.
1. Unplug the connector [1] on the IR/LED board that leads to the Local Control board, as it is not unplug-able at the Local Control board itself (soldered connector).
2. Release the cable from its clamps/tape.
3. Put your thumbs against the front bezel [1] while pulling the Local Control board in the direction of the arrow (fig. 2).
When defective, replace the whole unit.
1. Push both clips [1] that secure the IR & LED board outwards.
Figure 4-10 IR/LED Board
2. Pull the board out.
3. Remove the connectors [2] on the IR/LED board.
When defective, replace the whole unit.
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Mechanical Instructions

4.3.8 LCD Panel

Refer to Figure 4-11
1. Remove the Stand [A].
2. Remove the Speakers/Subwoofer [B] as described earlier.
3. Remove the PSU [C] and SSB [D] as described earlier.
4. Remove the IR/LED board [E] as described earlier.
5. Remove the Local Control board [F] as described earlier.
6. Remove the clamps [1].
7. Remove all metal brackets [2] that do not belong to the LCD display.
Now the LCD Panel can be lifted from the front cabinet.
for details.

4.4 Set Re-assembly

To re-assemble the whole set, execute all processes in reverse order.
Notes:
• While re-assembling, make sure that all cables are placed and connected in their original position.
• Pay special attention not to damage the EMC foams in the set. Ensure that EMC foams are mounted correctly.
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Figure 4-11 LCD Panel removal (based on 32" model)
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5. Service Modes, Error Codes, and Fault Finding

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Index of this chapter:
5.1
Test Points

5.2 Service Modes

5.3 Service Tools
5.4 Error Codes
5.5 The Blinking LED Procedure
5.6 Fault Finding and Repair Tips
5.7 Software Upgrading

5.1 Test Points

In the chassis schematics and layout overviews, the test points are mentioned. In the schematics and layouts, test points are indicated with “Fxxx” or “Ixxx”. As most signals are digital, it will be difficult to measure waveforms with a standard oscilloscope. Several key ICs are capable of generating test patterns, which can be controlled via ComPair. In this way it is possible to determine which part is defective.
Perform measurements under the following conditions:
• Service Default Mode.
• Video: Colour bar signal.
• Audio: 3 kHz left, 1 kHz right.
5.2 Service Modes
The Service Mode feature is split into four parts:
• Service Default Mode (SDM).
• Service Alignment Mode (SAM).
• Customer Service Mode (CSM).
• Computer Aided Repair Mode (ComPair).
SDM and SAM offer features, which can be used by the Service engineer to repair/align a TV set. Some features are:
• A pre-defined situation to ensure measurements can be made under uniform conditions (SDM).
• Activates the blinking LED procedure for error identification when no picture is available (SDM).
• The possibility to overrule software protections when SDM is entered via the Service pins.
• Make alignments (e.g. White Tone), (de)select options, enter options codes, reset the error buffer (SAM).
• Display information (“SDM” or “SAM” indication in upper right corner of screen, error buffer, software version, operating hours, options and option codes, sub menus).
The CSM is a Service Mode that can be enabled by the consumer. The CSM displays diagnosis information, which the customer can forward to the dealer or call centre. In CSM mode, “CSM”, is displayed in the top right corner of the screen. The information provided in CSM and the purpose of CSM is to:
• Increase the home repair hit rate.
• Decrease the number of nuisance calls.
• Solved customers' problem without home visit.
ComPair Mode is used for communication between a computer and a TV on I2C /UART level and can be used by a Service engineer to quickly diagnose the TV set by reading out error codes, read and write in NVMs, communicate with ICs and the uP (PWM, registers, etc.), and by making use of a fault finding database. It will also be possible to up and download the software of the TV set via I2C with help of ComPair. To do this, ComPair has to be connected to the TV set via the ComPair connector, which will be accessible through the rear of the set (without removing the rear cover).

5.2.1 General

Next items are applicable to all Service Modes or are general.
Life Timer
During the life time cycle of the TV set, a timer is kept (called “Op. Hour”). It counts the normal operation hours (not the Stand-by hours). The actual value of the timer is displayed in SDM and SAM in a decimal value. Every two soft-resets increase the hour by +1. Stand-by hours are not counted.
Software Identification, Version, and Cluster
The software ID, version, and cluster will be shown in the main menu display of SDM, SAM, and CSM. The screen will show: “AAAAAB-XX.YY”, where:
• AAAAA is the chassis name: LC101.
• B is the region indication: E= Europe, A= AP/China, U= NAFTA, L= LATAM.
• XX is the main version number: this is updated with a major change of specification (incompatible with the previous software version). Numbering will go from 01 - 99 and AA ­ZZ. – If the main version number changes, the new version
number is written in the NVM.
– If the main version number changes, the default
settings are loaded.
• YY is the sub version number: this is updated with a minor change (backwards compatible with the previous versions) Numbering will go from 00 - 99. – If the sub version number changes, the new version
number is written in the NVM.
– If the NVM is fresh, the software identification, version,
and cluster will be written to NVM.
Display Option Code Selection
When after an SSB or display exchange, the display option code is not set properly, it will result in a TV with “no display”. Therefore, it is required to set this display option code after such a repair. To do so, press the following key sequence on a standard RC transmitter: “062598” directly followed by MENU/HOME “xxx”, where “xxx” is a 3 digit decimal value of the panel type: see column “Display Code” in Table 6-4
, or see sticker on the
side/bottom of the cabinet. When the value is accepted and stored in NVM, the set will switch to Stand-by, to indicate that the process has been completed.
Figure 5-1 Location of Display Option Code sticker
During this algorithm, the NVM-content must be filtered, because several items in the NVM are TV-related and not SSB­related (e.g. Model and Prod. S/N). Therefore, “Model” and “Prod. S/N” data is changed into “See Type Plate”. In case a call centre or consumer reads “See Type Plate” in CSM mode, he needs to look to the side/bottom sticker to identify the set, for further actions.
and
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5.2.2 Service Default Mode (SDM)

Purpose
Set the TV in SDM mode in order to be able to create a pre­defined setting for measurements to be made. In this platform, a simplified SDM is introduced (without protection override and without tuning to a predefined frequency).
Specifications
• Set linear video and audio settings to 50%, but volume to 25%. Stored user settings are not affected.
• All service-unfriendly modes (if present) are disabled, since they interfere with diagnosing/repairing a set. These service unfriendly modes are: – (Sleep) timer. – Blue mute/Wall paper. – Auto switch “off” (when there is no “ident” signal). – Hotel or hospital mode. – Child lock or parental lock (manual or via V-chip). – Skipping, blanking of “Not favourite”, “Skipped” or
“Locked” presets/channels.
– Automatic storing of Personal Preset or Last Status
settings.
– Automatic user menu time-out (menu switches back/
OFF automatically.
– Auto Volume levelling (AVL).
How to Activate
To activate SDM, use one of the following methods:
• Press the following key sequence on the RC transmitter: “062596” directly followed by the MENU button.
• Short one of the “Service” pads on the TV board during cold start (see Figure 5-2 (remove the short after start-up). Caution: When doing this, the service-technician must know exactly what he is doing, as it could damage the television set.
). Then press the mains button
How to Navigate
As this mode is read only, there is not much to navigate. To switch to other modes, use one of the following methods:
• Command MENU from the user remote will enter the normal user menu (brightness, contrast, color, etc...) with “SDM” OSD remaining, and pressing MENU key again will return to the last status of SDM again.
• To prevent the OSD from interfering with measurements in SDM, command “OSD” or “i+” (“STATUS” or “INFO” for NAFTA and LATAM) from the user remote will toggle the OSD “on/off” with “SDM” OSD remaining always “on”.
• Press the following key sequence on the remote control transmitter: “062596” directly followed by the INFO[i+] button to switch to SAM (do not allow the display to time out between entries while keying the sequence).
How to Exit
Switch the set to Stand-by by pressing the mains button on the remote control transmitter or on the television set. If you switch the television set “off” by removing the mains (i.e., unplugging the television), the television set will remain in SDM when mains is re-applied, and the error buffer is not cleared. The error buffer will only be cleared when the “clear” command is used in the SAM menu.
Note:
• If the TV is switched “off” by a power interrupt while in SDM, the TV will show up in the last status of SDM menu as soon as the power is supplied again. The error buffer will not be cleared.
• In case the set is accidentally in Factory mode (with an “F” displayed on the screen), pressing and holding “VOL-“ and “CH-” simultaneously should exit the Factory mode.

5.2.3 Service Alignment Mode (SAM)

Purpose
• To change option settings.
• To display / clear the error code buffer.
• To perform alignments.
Figure 5-2 Service pads (SSB component side)
On Screen Menu
After activating SDM, the following items are displayed, with “SDM” in the upper right corner of the screen to indicate that the television is in Service Default Mode. Menu items and explanation:
• xxxxx: Operating hours (in decimal).
• AAAAAB-XX.YY: See paragraph
Version, and Cluster for the SW name definition.
• ERR: Shows all errors detected since the last time the buffer was erased in format <xxx> <xxx> <xxx> <xxx> <xxx> (five errors possible).
• OP: Used to read-out the option bytes. Ten codes (in two rows) are possible.
Software Identification,
Specifications
• Operation hours counter (maximum five digits displayed).
• Software version, error codes, and option settings display.
• Error buffer clearing.
• Option settings.
• Software alignments (White Tone).
• NVM Editor.
• Set screen mode to full screen (all content is visible).
How to Activate
To activate SAM, use one of the following methods:
• Press the following key sequence on the remote control transmitter: “062596” directly followed by the INFO[i+] button. Do not allow the display to time out between entries while keying the sequence.
• Or via ComPair.
After entering SAM, the following items are displayed, with “SAM” in the upper right corner of the screen to indicate that the television is in Service Alignment Mode.
Menu items and explanation:
1. System Information.
• Op Hour: This represents the life timer. The timer
counts normal operation hours, but does not count Stand-by hours.
• MAIN SW ID: See paragraph
Version, and Cluster for the SW name definition.
• ERR: Shows all errors detected since the last time the
buffer was erased. Five errors possible.
• OP1/OP2: Used to read-out the option bytes. See
paragraph 6.6
Option Settings in the Alignments
Software Identification,
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section for a detailed description. Ten codes are possible.
2. Tuner.
• AGC Adjustment: See paragraph 6.3.1 instructions.
• Store: To store the data.
3. Clear. Erases the contents of the error buffer. Select this menu item and press the MENU RIGHT key on the remote control. The content of the error buffer is cleared.
4. Options. To set the option bits. See paragraph 6.6
Settings in the “Alignments” chapter for a detailed
description.
5. RGB Align. To align the White Tone. See
Alignment: for a detailed description.
6. NVM Editor. To change the NVM data in the television set. See also paragraph 5.6
7. NVM Copy. Gives the possibility to copy/load the NVM file to/from an USB stick. See also paragraph 5.7.4
Copy NVM Data to/from USB and 5.7.5 How to Copy EDID Data to/from USB.
8. Initialise NVM. To initialize a (corrupted) NVM. Be careful, this will erase all settings!
9. Auto ADC. Refer to chapter 6. information.
10. EDID Write Enable. Enables EDID writing.
How to Navigate
• In the SAM menu, select menu items with the UP/DOWN keys on the remote control transmitter. The selected item will be indicated. When not all menu items fit on the screen, use the UP/DOWN keys to display the next / previous menu items.
• With the LEFT/RIGHT keys, it is possible to: – Activate the selected menu item. – Change the value of the selected menu item. – Activate the selected sub menu.
• When you press the MENU button twice while in top level SAM, the set will switch to the normal user menu (with the SAM mode still active in the background). To return to the SAM menu press the MENU button.
• The “INFO[i+]” key from the user remote will toggle the OSD “on/off” with “SAM” OSD remaining always “on”.
• Press the following key sequence on the remote control transmitter: “062596” directly followed by the MENU button to switch to SDM (do not allow the display to time out between entries while keying the sequence).
How to Store SAM Settings
To store the settings changed in SAM mode (except the OPTIONS and RGB ALIGN settings), leave the top level SAM menu by using the POWER button on the remote control transmitter or the television set. The mentioned exceptions must be stored separately via the STORE button.
How to Exit
Switch the set to STANDBY by pressing the mains button on the remote control transmitter or the television set.
Note:
• When the TV is switched “off” by a power interrupt while in SAM, the TV will show up in “normal operation mode” as soon as the power is supplied again. The error buffer will not be cleared.
• In case the set is in Factory mode by accident (with “F” displayed on screen), by pressing and hold “VOL-“ and “CH-” together should leave Factory mode.

5.2.4 Customer Service Mode (CSM)

Purpose
The Customer Service Mode shows error codes and information on the TV’s operation settings. A call centre can instruct the customer (by telephone) to enter CSM in order to
Fault Finding and Repair Tips.
Alignments for detailed
for
Option
White Tone
How to
identify the status of the set. This helps them to diagnose problems and failures in the TV before making a service call. The CSM is a read-only mode; therefore, modifications are not possible in this mode.
Specifications
• Ignore “Service unfriendly modes”.
• Line number for every line (to make CSM language independent).
• Set the screen mode to full screen (all contents on screen is visible).
• After leaving the Customer Service Mode, the original settings are restored.
• Possibility to use “CH+” or “CH-” for channel surfing, or enter the specific channel number on the RC.
How to Activate
To activate CSM, press the following key sequence on a standard remote control transmitter: “123654” (do not allow the display to time out between entries while keying the sequence).
After entering the Customer Service Mode, the following items are displayed:
Menu Explanation CSM1
1. Set Type. Type number, e.g. 32PFL5605/93. (*)
2. Production code. Product serial no., e.g. BZ1A1008123456 (*). BZ= Production centre, 1= BOM code, A= Service version change code, 10= Production year, 08= Production week, 123456= Serial number.
3. Installation date. Indicates the date of the first initialization of the TV. This date is acquired via time extraction.
4. a - Option Code 1. b - Option Code 2. Option code information (group 2).
5. SSB. Indication of the SSB factory ID (= 12nc). (*)
6. Display. Indication of the display ID (=12 nc). (*)
7. PSU. Indication of the PSU factory ID (= 12nc).
(*) If an NVM IC is replaced or initialized, these items must be re-written to it. ComPair will foresee in a possibility to do this.
Menu Explanation CSM2
1. Current Main SW. Shows the main software version.
2. Standby SW. Shows the Stand-by software version.
3. Panel Code. Shows the current display code.
4. Bootloader ID. Shows the Bootloader software ID.
5. NVM Version. The NVM software version no.
6. Flash ID. Shows the flash ID.
Menu Explanation CSM3
1. Signal Quality. Shows the signal quality (No Signal/Poor/ Average/Good).
2. Child lock. This is a combined item for locks. If any lock (Preset lock, child lock, lock after, or Parental lock) is active, this item indicates “active”.
3. HDCP KeyS. Indicates if the HDMI keys (or HDCP keys) are valid or not.
4. not used
5. not used
6. HDMI audio format input stream. Specification of HDMI audio input stream.
7. HDMI video format input stream. Specification of HDMI video input stream.
How to Exit
To exit CSM, use one of the following methods:
• Press the MENU/HOME button on the remote control transmitter.
• Press the POWER button on the remote control transmitter.
• Press the POWER button on the television set.
Option code information (group 1).
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Service Modes, Error Codes, and Fault Finding

5.3 Service Tools

5.3.1 ComPair

Introduction
ComPair (Computer Aided Repair) is a Service tool for Philips Consumer Electronics products. and offers the following:
1. ComPair helps you to quickly get an understanding on how to repair the chassis in a short and effective way.
2. ComPair allows very detailed diagnostics and is therefore capable of accurately indicating problem areas. You do not have to know anything about I2C or UART commands yourself, because ComPair takes care of this.
3. ComPair speeds up the repair time since it can automatically communicate with the chassis (when the uP is working) and all repair information is directly available.
4. ComPair features TV software up possibilities.
Specifications
ComPair consists of a Windows based fault finding program and an interface box between PC and the (defective) product. The (new) ComPair II interface box is connected to the PC via an USB cable. For the TV chassis, the ComPair interface box and the TV communicate via a bi-directional cable via the service connector(s).
How to Connect
This is described in the ComPair chassis fault finding database.

5.4 Error Codes

5.4.1 Introduction

Error codes are required to indicate failures in the TV set. In principle a unique error code is available for every:
• Activated (SW) protection.
•Failing I
• General I
The last five errors, stored in the NVM, are shown in the Service menu’s. This is called the error buffer. The error code buffer contains all errors detected since the last time the buffer was erased. The buffer is written from left to right. When an error occurs that is not yet in the error code buffer, it is displayed at the left side and all other errors shift one position to the right. An error will be added to the buffer if this error differs from any error in the buffer. The last found error is displayed on the left. An error with a designated error code may never lead to a deadlock situation. This means that it must always be diagnosable (e.g. error buffer via OSD or blinking LED procedure, ComPair to read from the NVM). In case a failure identified by an error code automatically results in other error codes (cause and effect), only the error code of the MAIN failure is displayed.

5.4.2 How to Read the Error Buffer

2
C device.
2
C error.
Figure 5-3 ComPair II interface connection
Caution: It is compulsory to connect the TV to the PC as
shown in the picture above (with the ComPair interface in between), as the ComPair interface acts as a level shifter. If one connects the TV directly to the PC (via UART), ICs will be blown!
How to Order
ComPair II order codes:
• ComPair II interface: 3122 785 91020.
• ComPair UART interface cable: 3138 188 75051.
• Program software can be downloaded from the Philips Service web portal.
Additional cables for VCOM Alignment
•ComPair/I
2
C interface cable: 3122 785 90004.
• ComPair/VGA adapter cable: 9965 100 09269.
Note: If you encounter any problems, contact your local support desk.
2010-Apr-06
You can read the error buffer in 3 ways:
• On screen via the SAM/SDM/CSM (if you have a picture). Example: – ERROR: 0 0 0 0 0 : No errors detected – ERROR: 6 0 0 0 0 : Error code 6 is the last and only
detected error
– ERROR: 9 6 0 0 0 : Error code 6 was detected first and
error code 9 is the last detected (newest) error
• Via the blinking LED procedure (when you have no picture). See paragraph 5.5
The Blinking LED Procedure.
•Via ComPair.

5.4.3 Error codes

The “layer 1” error codes are pointing to the defective board. They are triggered by LED blinking when CSM is activated. In the LC10 platform, only two boards are present: the SSB and the PSU/IPB, meaning only the following layer 1 errors are defined:
• 2: SSB
• 4: PSU/IPB
Table 5-1 Error code table
Layer-1 error code
2 SSB 11 Speaker DC protection active on SSB
4 IPB 12 +12 missing/low, IPB defective,
4 IPB 13 POK line defective
2 SSB 15 EEPROM I2C error on SSB, M24C16
2 SSB 16 Tuner I2C error on SSB
2 SSB 18 IF Demodulator I2C error on SSB,
Defective board
Layer-2 error code
Defective device
POWER_DOWN
TDA9886

5.4.4 How to Clear the Error Buffer

The error code buffer is cleared in the following cases:
• By using the CLEAR command in the SAM menu:
• If the contents of the error buffer have not changed for 50 hours, the error buffer resets automatically.
Note: If you exit SAM by disconnecting the mains from the television set, the error buffer is not reset.
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5.5 The Blinking LED Procedure

5.5.1 Introduction

The software is capable of identifying different kinds of errors. Because it is possible that more than one error can occur over time, an error buffer is available, which is capable of storing the last five errors that occurred. This is useful if the OSD is not working properly.
Errors can also be displayed by the blinking LED procedure. The method is to repeatedly let the front LED pulse with as many pulses as the error code number, followed by a period of
1.5 seconds in which the LED is “off”. Then this sequence is repeated.
Example (1): error code 4 will result in four times the sequence LED “on” for 0.25 seconds / LED “off” for 0.25 seconds. After this sequence, the LED will be “off” for 1.5 seconds. Any RC5 command terminates the sequence. Error code LED blinking is in red color.
Example (2): the content of the error buffer is “129600” After entering SDM, the following occurs:
• 1 long blink of 5 seconds to start the sequence,
• 12 short blinks followed by a pause of 1.5 seconds,
• 9 short blinks followed by a pause of 1.5 seconds,
• 6 short blinks followed by a pause of 1.5 seconds,
• 1 long blink of 1.5 seconds to finish the sequence,
• The sequence starts again with 12 short blinks.

5.5.2 Displaying the Entire Error Buffer

TV set. To initiate a forced default download the following action has to be performed:
1. Switch “off” the TV set with the mains cord disconnected from the wall outlet (it does not matter if this is from “Stand­by” or “Off” situation).
2. Short-circuit the SDM pads on the SSB (keep short circuited, see Figure 5-2
3. Press “P+” or “CH+” on the local keyboard (and keep it pressed).
4. Reconnect the mains supply to the wall outlet.
5. Release the “P+” or “CH+” when the set is started up and has entered SDM.
When the downloading has completed successfully, the set will perform a restart. After this, put the set to Stand-by and remove the short-circuit on the SDM pads.
Alternative method:
It is also possible to upload the default values to the NVM with ComPair in case the SW is changed, the NVM is replaced with a new (empty) one, or when the NVM content is corrupted. After replacing an EEPROM (or with a defective/no EEPROM), default settings should be used to enable the set to start-up and allow the Service Default Mode and Service Alignment Mode to be accessed.

5.6.3 No Picture

When you have no picture, first make sure you have entered the correct display code. See
Display Option Code Selection for the instructions.
See also Table 6-4
Option code overview.
).
Additionally, the entire error buffer is displayed when Service Mode “SDM” is entered. In case the TV set is in protection or Stand-by: The blinking LED procedure sequence (as in SDM­mode in normal operation) must be triggered by the following RC sequence: “MUTE” “062500” “OK”. In order to avoid confusion with RC5 signal reception blinking, this blinking procedure is terminated when a RC5 command is received.

5.6 Fault Finding and Repair Tips

Notes:
• It is assumed that the components are mounted correctly with correct values and no bad solder joints.
• Before any fault finding actions, check if the correct options are set.

5.6.1 NVM Editor

In some cases, it can be convenient if one directly can change the NVM contents. This can be done with the “NVM Editor” in SAM mode. With this option, single bytes can be changed.
Caution:
• Do not change these, without understanding the function of each setting, because incorrect NVM settings may seriously hamper the correct functioning of the TV set!
• Always write down the existing NVM settings, before changing the settings. This will enable you to return to the original settings, if the new settings turn out to be incorrect.

5.6.2 Load Default NVM Values

It is possible to download default values automatically into the NVM in case a blank NVM is placed or when the NVM first 20 address contents are “FF”. After the default values are downloaded, it is possible to start-up and to start aligning the

5.6.4 Unstable Picture via HDMI input

Check (via ComPair) if HDMI EDID data is properly programmed.

5.6.5 No Picture via HDMI input

Check if HDCP key is valid. This can be done in CSM.

5.6.6 HDMI CEC Not Functioning

Go to Home/Menu ->Setup -> Installation -> Preference and set the Easylink option to “on”. Also check if the connected device is CEC enabled.

5.6.7 TV Will Not Start-up from Stand-by.

Possible Stand-by Controller failure. Reflash the SW.

5.7 Software Upgrading

5.7.1 Introduction

It is possible for the user to upgrade the main software via the USB port. This allows replacement of a software image in a stand alone set. A description on how to upgrade the main software can be found in the DFU or on the Philips website.

5.7.2 Main Software Upgrade

Automatic Software Upgrade
In “normal” conditions, so when there is no major problem with the TV, the main software and the default software upgrade application can be upgraded with the “autorun.upg” (FUS part in the one-zip file). This can also be done by the consumers themselves, but they will have to get their software from the commercial Philips website or via the Software Update
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Assistant in the user menu (see DFU). The “autorun.upg” file must be placed in the root of your USB stick.
How to upgrade:
1. Copy the “autorun.upg” file to the root of an USB stick.
2. Insert the USB stick in the side I/O while the set is “on”. The TV will prompt an upgrade message. Press “Update” to continue, after which the upgrading process will start. As soon as the programming is finished, the set must be restarted.
In the “Setup” menu you can check if the latest software is running.

5.7.3 Content and Usage of the One-Zip Software File

Below you find a content explanation of the One-Zip file, and instructions on how and when to use it. Only files that are relevant for Service are mentioned here!
• EDID_clustername_version.zip. Contains the EDID content of the different EDID NVMs. See ComPair for further instructions.
• FUS_clustername_version.zip. Contains the “autorun.upg” which is needed to upgrade the TV main software and the software download application.
• NVM_clustername_version.zip. Default NVM content. Must be programmed via ComPair.
Service Modes, Error Codes, and Fault Finding

5.7.4 How to Copy NVM Data to/from USB

Write NVM data to USB
1. Insert the USB stick into the USB slot while in SAM mode.
2. Execute the command "NVM Copy" > "NVM Copy to USB", to copy the NVM data to the USB stick. The NVM filename on the USB stick will be named "NVM_COPY.BIN" (this takes a couple of seconds).
Write NVM data to TV
1. First, ensure (via a PC) that the filename on the USB stick has the correct format: "NVM_COPY.BIN".
2. Insert the USB stick into the USB slot while in SAM mode.
3. Execute the command "NVM Copy" > "NVM Copy from USB" to copy the USB data to NVM (this takes about a minute to complete).
Important: The file must be located in the root directory of the USB stick.

5.7.5 How to Copy EDID Data to/from USB

Write EDID data to USB
1. Insert the USB stick into the USB slot while in SAM mode.
2. Execute the command "NVM Copy" > "EDID Copy to USB", to copy the EDID data to the USB stick. The filename on the USB stick will be named "EDID2USB.BIN" (this takes a couple of seconds).
Write EDID data to TV
1. First, ensure (via a PC) that the filename on the USB stick has the correct format: "EDID2USB.BIN".
2. Insert the USB stick into the USB slot while in SAM mode.
3. Execute the command "NVM Copy" > "EDID Copy from USB" to copy the USB data to EDID (this takes about a minute to complete).
Important: The file must be located in the root directory of the USB stick.
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6. Alignments

Alignments
EN 19LC10.1L LA 6.
Index of this chapter:
6.1
General Alignment Conditions

6.2 Hardware Alignments

6.3 Software Alignments

6.4 ADC gain adjustment
6.6 Option Settings
Note: Figures below can deviate slightly from the actual situation, due to the different set executions.
General: The Service Default Mode (SDM) and Service Alignment Mode (SAM) are described in chapter 5. Menu navigation is done with the CURSOR UP, DOWN, LEFT or RIGHT keys of the remote control transmitter.

6.1 General Alignment Conditions

Perform all electrical adjustments under the following conditions:
• Power supply voltage (depends on region): – AP-NTSC: 120 V – AP-PAL-multi: 120 - 230 V – EU: 230 V
AC
– LATAM-NTSC: 120 - 230 V – US: 120 V
AC
or 230 VAC / 50 Hz (± 10%).
AC
/ 50 Hz (± 10%).
AC
/ 50 Hz (± 10%).
/ 50 Hz (± 10%).
AC
/ 60 Hz (± 10%).
• Connect the set to the mains via an isolation transformer with low internal resistance.
• Allow the set to warm up for approximately 15 minutes.
• Measure voltages and waveforms in relation to correct ground (e.g. measure audio signals in relation to AUDIO_GND). Caution: It is not allowed to use heatsinks as ground.
• Test probe: Ri > 10 Mohm, Ci < 20 pF.
• Use an isolated trimmer/screwdriver to perform alignments.
6.2 Hardware Alignments
6.3 Software Alignments
With the software alignments of the Service Alignment Mode (SAM) the Tuner and RGB settings can be aligned.

6.3.1 Tuner Adjustment (RF AGC Take Over Point)

Purpose: To keep the tuner output signal constant as the input
signal amplitude varies.
The LC10.1L LA chassis comes with the VA1E1BF2403 tuner. No alignment is necessary, as the AGC alignment is done automatically (standard value: “0”).

6.3.2 RGB Alignment

Before alignment, set the picture as follows:
Picture Setting
Dynamic backlight Off
Dynamic Contrast Off
Colour Enhancement Off
Picture Format Unscaled
Light Sensor Off
Brightness 50
Colour 0
Contrast 100
White Tone Alignment:
• Activate SAM.
• Select “RGB Align.“ and choose a color temperature.
• Use a 100% white screen as input signal and set the following values: – “Red BL Offset” and “Green BL Offset” to “7” (if
present).
– All “White point” values initial to “127”.
There are no hardware alignments foreseen for this chassis, but below find an overview of the most important DC voltages on the SSB. These can be used for checking proper functioning of the DC/DC converters.
Description Test
+12VS F118 11.7 12.3 12.91 B01_DC-DC
+3V3_STBY F113 3.2 3.3 3.4 B01_DC-DC
+3V3_SWF1333.173.343.5 B01_DC-DC
+1V2_SW F131 1.18 1.25 1.31 B01_DC-DC
+5V_SW F132 4.98 5.25 5.51 B01_DC-DC
+1V8_SW F125 1.74 1.83 1.92 B01_DC-DC
+1V0_SWF1340.991.051.1 B01_DC-DC
+5VS F235 4.94 5.2 5.46 B02A_Tuner
+2V5_SW F305 2.38 2.5 2.62 B02B_Demod
+5VTUN_DI GITAL
VLS_15V6 FJ00 14.82 15.6 16.38 B08B TCON DC/DC
VGL_-6V FJ14 -6.32 -6.02 -5.72 B08B TCON DC/DC
VCC_3V3 FK13 3.14 3.3 3.47 B08B TCON DC/DC
Specifications (V) Diagram
Point
Min. Typ. Max.
F236 4.75 5 5.25 B02A_Tuner
In case you have a color analyzer:
• Measure with a calibrated (phosphor- independent) color analyzer (e.g. Minolta CA-210) in the centre of the screen. Consequently, the measurement needs to be done in a dark environment.
• Adjust the correct x,y coordinates (while holding one of the White point registers R, G or B on max. value) by means of decreasing the value of one or two other white points to the correct x,y coordinates (see Table 6-1
White D alignment
values). Tolerance: dx: ± 0.002, dy: ± 0.002.
• Repeat this step for the other color Temperatures that need to be aligned.
• When finished return to the SAM root menu and press STANDBY on the RC to store the aligned values to the NVM.
Table 6-1 White D alignment values
Value Cool (11000 K) Normal (9000 K) Warm (6500 K)
x 0.276 0.287 0.313
y 0.282 0.296 0.329
If you do not have a color analyzer, you can use the default values. This is the next best solution. The default values are average values coming from production (statistics).
• Set the RED, GREEN and BLUE default values per temperature according to the values in the “Tint settings” table.
• When finished return to the SAM root menu and press STANDBY on the RC to store the aligned values to the NVM.
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Alignments
Table 6-2 Tint settings 32"
Colour Temp. R G B
Cool tbf tbf tbf
Normal tbf tbf tbf
Warm tbf tbf tbf
Table 6-3 Tint settings 40"
Colour Temp. R G B
Cool tbf tbf tbf
Normal tbf tbf tbf
Warm tbf tbf tbf

6.4 ADC gain adjustment

Use a Quantum Data Patters Generator 802BT and apply a “PgcWrgb” image (“dot, cross and color bar mix pattern”) according to Figure 6-1
.

6.5 TCON Alignment (= VCOM alignment)

New requirement for “TCON on SSB” project:
• The purpose of VCOM alignment is to obtain an equal voltages for both Positive and Negative LC polarity. This is important to avoid “Flicker” and “Image Sticking”.
• The P-Gamma + VCOM calibrator IC, ISL24837 is used for VCOM adjustment.
• The adjusted VCOM data will be stored inside on-chip memory and will be automatically recalled during each power-up.
ComPair (see 5.3.1
ComPair) will foresee in a possibility to do
this alignment.

6.6 Option Settings

6.6.1 Introduction

The microprocessor communicates with a large number of I ICs in the set. To ensure good communication and to make digital diagnosis possible, the microprocessor has to know which ICs to address. The presence/absence of these specific ICs (or functions) is made known by the option codes.
Notes:
• After changing the option(s), save them with the STORE command.
• The new option setting becomes active after the TV is switched “off” and “on” again with the mains switch (the EAROM is then read again).
2
C

Figure 6-1 “PgcWrgb” pattern

6.4.1 YPbPr

Following instructions result in correct alignment of ADC gain, offset and phase, related to YPbPr input signal. Apply a signal of format “1080i25”.
• Apply following signals to the YPbPr input connectors: – Pr signal of 0.7 Vp-p
connector.
– Y signal of 0.7 Vb-p
1
Vp-p
to the green cinch connector.
– Pb signal of 0.7 Vb-p
1
/ 75 ohm to the red cinch
2
/ 75 ohm with a sync pulse of 0.3
1
/ 75 ohm to the blue cinch
connector.
• Select the input source to YPbPr input.
• In SAM, initiate the “Auto ADC” calibration command.
Upon appearance of the “Auto ADC Completed” message, the alignment is completed.
Notes:
1. Peak-to-Peak
2. Black-to-Peak.

6.4.2 PC VGA

6.6.2 How To Set Option Codes

When the NVM is replaced, all options will require resetting. To be certain that the factory settings are reproduced exactly, you must set all option numbers. You can find the correct option numbers in Table 6-4
.
How to Change Options Codes
An option code (or “option byte”) represents eight different options (bits). All options are controlled via ten option bytes (OP#1... OP#10). Activate SAM and select “Options”. Now you can select the option byte (OP#1... OP#10) with the CURSOR UP/ DOWN keys, and enter the new 3 digit (decimal) value. For the correct factory default settings, see Table 6-4
Option code overview.
Table 6-4 Option code overview
CTN Option Code Display Code
32PFL3605D/78 002 192 145 248 072 006 060 078 068 001 237
40PFL3605D/78 002 192 145 248 072 006 060 078 068 002 238
Following instructions result in correct alignment of ADC gain, offset and phase, related to PC VGA input signal. Apply a signal of format “DMT1060”.
• Apply following signals to the PC VGA input connector: – Red signal of 650 - 730 mV. – Green signal of 650 - 730 mV. – Blue signal of 650 - 730 mV.
• Select the input source to PC VGA input.
• In SAM, initiate the “Auto ADC” calibration command.
Upon appearance of the “Auto ADC Completed” message, the alignment is completed.
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7. Circuit Descriptions

Index of this chapter:
7.1
Introduction
7.2 Power Supply
7.3 Video
7.3.1 Video: Front-End
7.3.2 VIDEO: TCON
7.4 Audio
7.5 Inputs
7.5.1 Inputs: HDMI
7.5.2 Inputs: USB
Notes:
•Only new circuits (circuits that are not published recently) are described.
• Figures can deviate slightly from the actual situation, due to different set executions.
• For a good understanding of the following circuit descriptions, please use chapter 9.
10.
Circuit Diagrams and PWB Layouts. Where necessary,
you will find a separate drawing for clarification.

7.1 Introduction

Block Diagrams and
Circuit Descriptions
EN 21LC10.1L LA 7.
The LC10.1L LA chassis is a digital chassis using a Mediatek chipset. It covers screen sizes of 32" to 40" with a styling called “Dali”.
Main key components are the Mediatek MT5363 integrated “System On Chip” (SoC) that supports multimedia video/audio input, and the integrated TCON (Timing Controller) part for the LCD panel.
System SoC is based on MT5363:
• NAND Flash – 128 Mbyte, NumOnyx/Hynix.
• DDR – 128 Mbyte (32x16M, 2 pcs), Hynix.
• Use internal MT5363 Stand-by micro-controller.
Tuner/Frontend configuration:
• Half NIM tuner from Sharp.
• Toshiba Channel Decoder (TC90517).
Digital Connectivity:
• 1x USB port with over current protection using power switch.
• 2x HDMI ports (using MT5363 internal mux).
Analog Connectivity:
• 2x YPbPr (component video) + Audio (cinch).
• 1x CVBS (composite) + Audio (cinch).
• 1x VGA (RGB) + Audio (3.5mm stereo jack).
Interfaces for debug and SW upgrade:
• UART (3.5mm jack).
•USB port.
•JTAG.
Refer to Figure 7-1
for details.
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Circuit Descriptions

Figure 7-1 LC10.1L LA Architecture

2010-Apr-06

Figure 7-2 SSB cell layout

Page 23

7.2 Power Supply

DC/DC
3.3V+/ -0.16V
MT5363
Dig Demod
Flash
NVM
1.25V+/ -0.06V
1V8+/ -0.09V
DDR2 x2
+12VS
DC/DC
1.1V+/ -0.05V
Regula tor
5.25V+/ -0.25V
Regula tor
DC/DC
EEPROM
EEPROM
USB
5.25V+/ -0.26V
2.5V+/ - 0.12V
Tuner
+3V3STBY
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The Power Supply Unit (PSU) in this chassis is a buy-in and is a black-box for Service. When defective, a new panel must be ordered and the defective panel must be returned for repair, unless the main fuse of the unit is broken. Always replace the fuse with one with the correct specifications! This part is commonly available in the regular market.
Circuit Descriptions
EN 23LC10.1L LA 7.
Refer to Figure 7-3
and Figure 7-4 for details
The power supply system consists of stand-by, switched and regulated voltages. The stand-by voltage, +3V3STBY, will be available once AC supply is provided to the system. As for the other voltages, namely switched and regulated voltages, these are available once the STANDBY signal is pulled “low” to allow other supplies from the IPB to turn “on”. The switched supplies are generated from the main +12VS supply, while the regulated supplies are derived from the switched supplies. There are a number of detection circuits to detect the following supplies: +12VS, +12Vdisp and +3V3_SW. The +12VS is the main supply voltage from the IPB that enables the switched voltages to be generated. The +12Vdisp is the supply to the display timing controller, while the +3V3_SW is powering the microprocessor and its flash memory.
The mains power supply unit distribute the following voltages to the TV system: +3V3STBY, 12VS, +24Vaudio, and +24Vpanel for panel with inverter (or) high voltage (HV) for inverterless panel. Requirement of the High Voltage depend on the specification of the LCD panel.

Figure 7-4 Power timing overview

Figure 7-3 Power distribution overview

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EEPROM
TFT – LCD Panel
Mini - LVDS
Control Signals
+3V3 +1V2
VGH (+35V) VGL ( − 6V)
+12V
LVDS
(10bit)
Timing
Controller
Power Block
Gamma
Reference
Voltage
Source Drive IC
Gate Drive IC
MTK
LCD Panel
TCONMain Platform
SSB
+ 15.6V
Circuit Descriptions

7.3 Video

7.3.1 Video: Front-End

Key components for the tuner section are:
• Sharp Half NIM tuner VA1E1BF2403,
• Toshiba channel decoder TC90517 (external ISDB-T channel decoder).
• Analog demodulator (using internal MT5363 analog demodulator - pin AH35 VIP, AH37 VIN).
Refer to Figure 7-5
for details.

7.3.2 VIDEO: TCON

The Timing Controller (TCON) is integrated in the SSB (“Forward Integration” concept). Refer to Figure 7-6
Figure 7-5 Front-end functional block diagram
.
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Figure 7-6 TCON system block diagram
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Circuit Descriptions
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EN 25LC10.1L LA 7.

7.4 Audio

In this chassis, audio processing is done by the following key components:
• MT5363 micro-processor for input selection and audio processing,
• TPA3123D2 class-D power amplifier for 2 x 10 W amplification.
The audio profile (optimal setting per screen size and styling) is stored at Option 10 (bit 0 to bit 4). Profile 1 for 32-inch Dali and profile 2 for 40-inch Dali.

Table 7-1 Microprocessor control lines - 1 -

From uP At class D Usage
SW_MUTE SW_MUTE Will pull audio signals to LOW upon DC drops, help
RESET_AUDIO A_STBY Control SHUTDOWN pin of class D amplifier:
MUTE MUTE Corresponding to the MUTE button on Remote
DC_PROT DC_PROT Detecting present of DC at speakers output and

Table 7-2 Microprocessor control lines - 2 -

From uP A_STBY
SW_MUTE LOW - MUTE
HIGH - Operating (unmute)
RESET_AUDIO LOW HIGH Operating (unmute)
HIGH LOW Class D shutdown (mute)
MUTE LOW - Operating (unmute)
HIGH - MUTE
DC_PROT LOW - DC detected -> set going to protection
HIGH - No DC -> normal operating
to eliminate plop sound.
ON/OFF the amplifier
Control, to mute/unmute speakers
feedback to uP. This will trigger TV into protection mode. This is important to protect speakers
to class D
Class D outputs
Figure 7-7 Audio signal flow
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7.5 Inputs

7.5.1 Inputs: HDMI

In this chassis, the main Mediatek MT5363 SoC has an on-chip HDMI multiplexer. Refer to Figure 7-8
Figure 7-8 HDMI implementation
for the implementation.
Circuit Descriptions
Signal description:
• TMDS: Signals that contain audio and video information.
• PWR5V: Signal to detect the presence of any HDMI source connected to the TV’s HDMI input port.
• SIDE_HDMI_HPD1 and HDMI_HPD2: Signal to initiate reading of the TV EDID data by the source device.
• I2C: The EDID data reading and the HDCP authentication process runs via I2C.
• CEC: Signal direct connected between inputs and uP.
• EDID_WC: Signal used to disable the write protect pin of the EEPROM. When updating, the program will temporarily pull this pin “LOW” before writing new data.

7.5.2 Inputs: USB

In this chassis, the main Mediatek MT5363 SoC has an on-chip USB processor. Refer to Figure 7-9
for the implementation.
2010-Apr-06
Figure 7-9 USB implementation
Page 27

8. IC Data Sheets

18980_300_100402.eps
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PIN
CONNECTIONS
1
2
3
4
14
13
12
11
PVDD2
BOOT2
SW2
BP
PVDD1
BOOT1
SW1
GND
5
6
7
10
9
8
SEQ
ILIM2
FB2
EN1
EN2
FB1
Thermal Pad
(bottom side)
HTSSOP (PWP)
(Top View)
BLOCK DIAGRAM
7FB1
+
Soft Start
1
C
COMP
+
SQ
QR
R
+
Current Comparator
BP
f(I
DRAIN1
)+DC(ofst)
2
1
3
Anti-Cross
Conduction
1.2 MHz Oscilator
Divide by 2/4
Ramp Gen 1
Ramp Gen 2
CLK1
CLK2
BP
CLK1
Weak Pull-Down MOSFET
5EN1
6EN2
6A6A
VDD2
Internal Control
10SEQ
150 k
150 k
Output
Undervoltage
Detect
BP
FB1
FB2
CLK1
4GND
8FB2
+
Soft Start
2
C
COMP
+
SQ
QR
R
+
Current Comparator
BP
13
14
12
Anti-Cross
Conduction
BP
CLK2
Weak Pull-Down MOSFET
11BP
9ILIM2
150 k
150 k
BP
CLK2
4GND
Level
Select
5.25-V
Regulator
References
BOOT1
PVDD1
SW1
BOOT2
PVDD2
SW2
f(I
DRAIN2
)+DC(ofst)
0.8 V
REF
I
MAX2
(Set to one of three limits)
f(I
DRAIN1
)
f(I
MAX1
)
Overcurrent Comp
f(I
SLOPE1
)
Level
Shift
Level
Shift
f(I
DRAIN2
)
f(I
MAX2
)
f(I
SLOPE2
)
FET Switch
TSD
PVDD2
f(I
SLOPE1
)
f(I
SLOPE2
)
SD1
SD2
UVLO
0.8 V
REF
SD2
0.8 V
REF
SD1
UDG-07124
Overcurrent Comp
R
COMP
R
COMP
This section shows the internal block diagrams and pin layouts of ICs that are drawn as "black boxes" in the electrical diagrams (with the exception of "memory" and "logic" ICs).

8.1 Diagram B01, Type TPS54386 (IC7116 and 7117)

IC Data Sheets
EN 27LC10.1L LA 8.
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Figure 8-1 Internal block diagram and pin configuration

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Block diagram
Pinning information
PowerSO-8
DFN8 (4 × 4)
IC Data Sheets

8.2 Diagram B01 SSB: DC-DC, Type ST1S10PH (IC7107)

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Figure 8-2 Internal block diagram and pin configuration

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IC Data Sheets
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Block diagram
Pinning information
DPAK
LD1117DT

8.3 Diagram B02B SSB: Digital Demodulator, Type LD1117D (IC7315)

EN 29LC10.1L LA 8.

Figure 8-3 Internal block diagram and pin configuration

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Block diagram
Pinning information
1 2 3
4 5 6 7 8 9
10 11 12
24 23 22
21 20 19 18 17 16
15 14 13
PVCCL
SD
PVCCL
MUTE
LIN
RIN
BYPASS
AGND AGND
PVCCR
VCLAMP
PVCCR
PGNDL PGNDL LOUT BSL AVC C AVC C GAIN0 GAIN1 BSR ROUT PGNDR PGNDR
TERMINAL
I/O/P DESCRIPTION
24-PIN
NAME
(PWP)
Shutdown signal for IC (low = disabled, high = operational). TTL logic levels with compliance to
SD
2I
AVCC
RIN 6 I Audio input for right channel
LIN 5 I Audio input for left channel
GAIN0 18 I Gain select least-significant bit. TTL logic levels with compliance to AVCC
GAIN1 17 I Gain select most-significant bit. TTL logic levels with compliance to AVCC
Mute signal for quick disable/enable of outputs (high = outputs switch at 50% duty cycle, low =
MUTE 4 I
outputs enabled). TTL logic levels with compliance to AVCC
BSL 21 I/O Bootstrap I/O for left channel
PVCCL 1, 3 P Power supply for left-channel H-bridge, not internally connected to PVCCR or AVCC
LOUT 22 O Class-D 1/2-H-bridge positive output for left channel
PGNDL 23, 24 P Power ground for left-channel H-bridge
VCLAMP 11 P Internally generated voltage supply for bootstrap capacitors
BSR 16 I/O Bootstrap I/O for right channel
ROUT 15 O Class-D 1/2-H-bridge negative output for right channel
PGNDR 13, 14 P Power ground for right-channel H-bridge.
PVCCR 10, 12 P Power supply for right-channel H-bridge, not connected to PVCCL or AVCC
AGND 9 P Analog ground for digital/analog cells in core
AGND 8 P Analog ground for analog cells in core
Reference for preamplifier inputs. Nominally equal to AVCC/8. Also controls start-up time via
BYPASS 7 O
external capacitor sizing.
AVCC 19, 20 P High-voltage analog power supply. Not internally connected to PVCCR or PVCCL
Connect to ground. Thermal pad should be soldered down on all applications to properly
Thermal pad Die pad P
secure device to printed wiring board.
1F
SD
PVCCL
PVCCR
VCLAMP
GAIN1
BYPASS
1F
1F
0.22 F
AGND
}
Control
Shutdown
Control
LIN
RIN
BSR
BSL
PGNDR
PGNDL
0.22 F
22 H
22 H
0.68 F
470 F
0.68 F
1F
470 F
GAIN0
AVC C
MUTE
ROUT
LOUT
IC Data Sheets

8.4 Diagram B03 SSB: Class-D & Muting, Type TPA3123 (IC7400)

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Figure 8-4 Internal block diagram and pin configuration

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IC Data Sheets
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Block diagram
DVB-T ATD
CVBS/
YC Input
VADCx4
TV
Decoder
HDMI
Rx
HDMI In
I/F
Audio
Demod
Audio Input
Audio
ADC
Panel
LVDS
CVBS
VDAC
TVE
DDR
DRAM
Controller
ARM
BIM
TS
Demux
VDO-In
PreProc
MDDi
Audio In
JPEG,MPEG
H.264
2-D Graphic
Mix andPost
Processing
OSD
scaler
Vplane
scaler/PIP
Audio DSP
IO Bus
Standby uP CKGEN
Audio I/F
Audio DAC
SPDIF, I
2
S
BScan PVR RTC
UART
MS,SD PWM NAND Flash
JTAG IrDA SIF USB2.0 Watchdog Serial Flash Servo ADC

8.5 Diagram B04 SSB: MTK Power, Type MT5363 (IC7700)

EN 31LC10.1L LA 8.

Figure 8-5 Internal block diagram

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Pinning information
LT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
A
B VCC2IO
C
D RA9
E
F RA5
G
H RBA2
J
K RCKE
L
M RA13
N
P RA8
R
T RDQ19
U
V RDQM2
W
Y RDQS3
AA
AB RDQ16
AC
AD RCLK1
AE
AF VCC2IO
AG
AH GPIO44
AJ
AK JTRST_
AL
AM VCCK
AN
AP OSDA0
AR
AT POCE0_
AU
RCLK0_
VCC2IO
RA12
RA10
RBA1
RCAS_
RA11
VCC2IO
RDQ22
RDQS2_
RDQS3_
RDQ21
VCC2IO
GPIO38
JTDI
VCCK
VCCK
PDD0
POOE_
RCLK0
VCC2IO
RA7
RBA0
RWE_
RA2
RCS_
RDQ20
RDQS2
DVSS
RDQ23
RCLK1_
VCC2IO
GPIO43
JTCK
VCCK
OSCL0
POWE_
RDQ10
RDQ13
VCC2IO
RA3
DVSS
DVSS
RA0
VCC2IO
RDQ17
DVSS
RDQ29
RDQ18
VCC2IO
GPIO41
JTMS
VCCK
VCCK
PAALE
PACLE
RDQ8
RDQ5
VCC2IO
RA1
MEMTN
RA4
RRAS_
RDQ30
RDQ28
RDQ24
REXTDN
VCC2IO
GPIO37
JTDO
VCCK
VCCK
PDD1
PARB_
RDQ15
RDQS1_
RDQ2
VCC2IO
DVSS
DVSS
RODT
VCC2IO
RDQM3
DVSS
RDQ26
VCC2IO
GPIO39
GPIO42
VCCK
VCCK
POCE1_
PDD2
PDD3
RDQS1
RDQ0
RDQ7
VCC2IO
MEMTP
RA6
RVREF
RDQ25
RDQ27
RDQ31
VCC2IO
GPIO40
VCCK
VCCK
VCCK
PDD4
PDD5
RDQS0_
DVSS
DVSS
DVSS
RVREF
DVSS
VCCK
VCCK
PDD6
PDD7
RDQS0
DVSS
DVSS
DVSS
AVSS12_U
SB
AVSS33_U
SB
AVSS33_U
SB
RDQ14
RDQM1
RDQM0
DVSS
AVDD12_U
SB
USB_VRT
USB_DM
USB_DP
RDQ11
RDQ9
RDQ6
RDQ1
AVDD33_U
SB
AVDD12_H
DMI
AVSS33_U
SB
RDQ12
VCC2IO
VCC2IO
RDQ3
VCCK
HDMI_SCL
2
AVSS33_H
DMI
RX2_C
RX2_CB
VCC2IO
VCC2IO
VCC2IO
RDQ4
AVDD12_M
EMPLL
AVSS12_M
EMPLL
VCCK
VCCK
DVSS
DVSS
VCCIO33-1
AVDD33_H
DMI
RX2_0
RX2_0B
VCC2IO
VCC2IO
VCC2IO
DVSS
DVSS
VCCK
DVSS
VCCK
DVSS
VCCK
HDMI_SDA
2
HDMI_CEC
RX2_1
RX2_1B
AO0N
AO0P
AVDD33_L
VDS
AVDD33_L
VDS
DVSS
DVSS
DVSS
VCCK
DVSS
VCCK
VCCIO33-1
PWR5V_2
RX2_2
RX2_2B
AO1N
AO1P
AE0N
AE0P
AVDD12_L
VDS
VCCK
DVSS
DVSS
DVSS
DVSS
VCCK
PWR5V_1
HDMI_HPD
2
RX1_C
RX1_CB
AO2N
AO2P
AE1N
AE1P
AVSS12_L
VDS
DVSS
DVSS
DVSS
DVSS
VCCK
HDMI_SCL
1
RX1_0
RX1_0B
AOCKN
AOCKP
AE2N
AE2P
AVSS33_L
VDS
AVDD12_V
PLL
DVSS
DVSS
DVSS
DVSS
DVSS
VCCK
HDMI_HPD
1
HDMI_SDA
1
RX1_1
RX1_1B
AO3N
AO3P
AECKN
AECKP
TP_VPLL
AVSS12_V
PLL
DVSS
DVSS
DVSS
DVSS
VCCK
OPCTRL1
RX1_2
RX1_2B
AV 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
IC Data Sheets

Figure 8-6 Internal block diagram

2010-Apr-06
Page 33
IC Data Sheets
18850_302_100107.eps
100222
Pinning information
20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 RT
A 0DXRTE 2DXRTE 0DXTTE 3OIPG 12OIPG 53OIPG N4OA
AO4P
AE3N
AE3P
DVSS
DVSS
AE4N
AE4P
GPIO36
DVSS
DVSS
GPIO32
GPIO34
GPIO33
VCCIO33
GPIO28
GPIO30
GPIO29
GPIO31
GPIO26
GPIO27
GPIO24
GPIO25
GPIO22
GPIO20
GPIO19
GPIO23
GPIO17
GPIO18
GPIO16
GPIO15
GPIO11
GPIO12
GPIO14
GPIO13
GPIO9
GPIO10
GPIO8
GPIO7
GPIO4
GPIO6
GPIO5
VCCIO33
FSRC_WR
ETTXD3
ETTXEN
ETPHYCLK
VCCIO33
AOSDATA3
IF_AGC
ETTXD1
ETTXD2
ETCOL
GPIO2
ALIN
ETRXCLK
ETTXCLK
CI_MCLKO
CI_MISTR
T
ASPDIF
RF_AGC
ETRXD3
ETTXER
CI_MIVAL
OPWM0
AOBCK
ETRXD1
ETRXER
CI_MCLKI
CI_MDI0
GPIO0
AOMCLK
ETRXDV B
ETCRS C
ETMDIO D
ETMDC E
CI_MOSTR
T
F
CI_MOVAL G
CI_MDO0 H
OPWM1 J
GPIO1 K
AOSDATA0 L
AOLRCK M
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
VCCK
DVSS
DVSS
DVSS
DVSS
DVSS
VCCK
DVSS
DVSS
DVSS
VCCK
VCCK
AVSS33_A
DAC1
OSCL2
AVDD33_A
DAC1
VCCIO33
AOSDATA4
OSDA1
AL1
OSDA2
OPWM2
AR1
TUNER_DA
TA
OSCL1
AR2
AOSDATA1
U1TX
AL2
TUNER_CL
K
U1RX
AR3
N
AOSDATA2 P
R
VCXO T
U
AL3 V
DVSS DVSS VCCK
AVDD33_R
EF_AADC
VCCIO33 VCCIO33 VCCIO33 W
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
VCCK
VCCK
VCCK
AVSS33_R EF_AADC
VMID_AAD
C
AVDD33_A
ADC
AIN1_L_AA
AIN4_L_AA
DC
AVSS33_A
ADC
AIN4_R_A
AIN5_L_AA
DC
AIN5_R_A
ADC
AIN2_R_A
AIN6_L_AA
DC
AIN6_R_A
ADC
Y
AA
AIN3_R_A
DVSS
VCCK
DVSS
DVSS
VCCK
DVSS
DVSS
DVSS
DVSS
AVDD12_T
VDPLL
AVDD12_A
DC
AIN1_R_A
ADC
AVDD12_S
ADC
AIN0_L_AA
DC
AVDD33_
ADAC0
AIN0_R_A
ADC
AVSS33_A
DAC0
AVDD33_
ADC
AIN2_L_AA
DC
AVICM
AIN3_L_AA
DC
AR0
AVSS33_D
ADC
AB
AC
AD
AE
AL0 AF
OPWRSB
OPCTRL0
ORESET_
AVDD10_L
AVSS33_V
GA_STB
AVDD12_R
AVSS12_P
LL
AVSS33_SI
F
FS_VDAC
PLL
AVSS33_D
IG
AVDD33_S
IF
AVSS12_P
LL
AVDD33_D
IG
BYPASS0
YSPLL
ADIN0_SR
V
AVDD12_A
DCPLL
ADIN1_SR
V
AF
DEMOD1
XTALO
ADIN3_SR
V
ADCINN_D
EMOD
AVDD33_X
TAL_STB
ADIN2_SR
EMOD1 AG
ADCINP_D
EMOD
AH
XTALI AJ
AVSS33_X
TAL
AK
ADIN5_SR
V
AL
ADIN4_SR
OPCTRL2
OPCTRL3
OPCTRL4
U0TX
U0RX
OIRI
HSYNC
VSYNC
DO
SOG
BP
AVDD33_V
GA_STB
COM
GP
GB
SOY1
RP
AVSS12_R
GB
COM1
Y1P
PR1P
PB1P
Y0P
SOY0
PB0P
COM0
AVDD33_V
DAC
AVSS33_V
DAC
PR0P
VDAC_OUT
1
VDAC_OUT
2
AVDD33_C
VBS
AVSS33_C
VBS
SY0
SC0
MPXP
SY1
SC1
V
CVBS2P
CVBS3P
V
AM
MPXN AN
TUNER_BY
PASS
AP
CVBS0N AR
CVBS0P AT
CVBS1P AU
20 21 22 23 24 25 26 27 28 29 3
0 31 32 33 34 35 36 37 R B

Figure 8-7 Internal block diagram

EN 33LC10.1L LA 8.
2010-Apr-06
Page 34
EN 34 LC10.1L LA8.
18520_306_090325.eps
100402
Pinning information
2
(Top View)
1
3
4
8
7
6
5
Output 1
Inputs 1
Output 2
Inputs 2
V
EE
V
CC
1
2

8.6 Diagram B06B SSB: Analog I/O - Audio, Type LM833 (IC7B01)

IC Data Sheets

Figure 8-8 Pin configuration

2010-Apr-06
Page 35
IC Data Sheets
18770_307_100217.eps
100217
Block diagram
Pinning information
1
40
2
3
4
5
6
7
8
9
10
30
29
28
27
26
25
24
23
22
21
39 38 37 36 35 34 33 32 31
11 12 13 14 15 16 17 18 19 20
LDO-CTL
LDO-FB
PVIN1
AGND
PROT
LX2
LX1
PGND2
PGND1
TEMP
COMP
FBB
RSET
HVS
EN
CDEL
CTL
DRN
COM
POUT
PVIN2
CB
LXL1
LXL2
PGND3
PGND4
CM2
FBL
VL
VREF
FBN
SUPN
NOUT
PGND5
C1P
C1N
C2P
C2N
SUPP
FBP
ISL97653A
40 LD 6X6 QFN
TOP VIEW
+
-
+
-
+
-
+
-
+
-
+
-
+
-
+
-
Ε
Ε
CONTROL
LOGIC
SAWTOOTH
GENERATOR
CURRENT
AMPLIFIER
CURRENT LIMIT
COMPARATOR
CURRENT LIMIT THRESHOLD
REFERENCE BIAS
AND
SEQUENCE CONTROLLER
V
REF
GM AMPLIFIER
UVLO COMPARATOR
OSCILLATOR
0.75 V
REF
REGULATOR
SUPN
0.2V
UVLO COMPARATOR
0.4V
0.75 V
REF
V
REF
P
OUT
R
SENSE
BUFFER
CONTROL
LOGIC
V
REF
SAWTOOTH
GENERATOR
SLOPE COMPENSATION
GM AMPLIFIER
SUPP
CURRENT LIMIT
THRESHOLD
CURRENT
LIMIT
COMPARATOR
SUPP
C1- C1+ C2+ C2-P
OUT
CTL COM
BUFFER
LX1
PGND1
CB
LXL1
CM2
FBL
FBP
FBN
N
OUT
P
VIN1,2
EN
CDEL
P
VIN1,2
VL
FBB
CM1
PGND2
LX2
CURRENT AMPLIFIER
SLOPE COMPENSATION
V
REF
FREQ
HVS
LOGIC
RSET HVS PROT
LXL2
DRN
680kHz
VL
LDO
CONTROL
LOGIC2
LDO-CTL
LDO-FB
TEMP
SENSOR
TEMP

8.7 Diagram B08B SSB: TCON DC/DC, Type ISL97653 (IC7J00)

EN 35LC10.1L LA 8.

Figure 8-9 Internal block diagram and pin configuration

2010-Apr-06
Page 36
EN 36 LC10.1L LA8.
Personal Notes:
10000_012_090121.eps
IC Data Sheets
2010-Apr-06
Page 37

9. Block Diagrams

11P
1M95
9P
1M99
2P3
1308
1735
4P
1M95
11P
1M99
9P
1KA2
80P
1KA1
80P
1M20
8P
MAINS CORD
8191
TO DISPLAY TO DISPLAY
3P
J1
SSB
(1150)
B
MAIN POWER SUPPLY IPB 32 PLHC-P984A B IPB 40 PLHE-P986A B
(1005)
LCD DISPLAY
(1004)
8M99
8M95
WIRING DIAGRAM 32"- 40" DALI
18980_400_100329.eps
100402
1M99 (B01)
1. +12VDISP
2. +12VDISP
3. GND
4. GND
5. LAMP-ON
6. PWM-DIMMING
7. BACKLIGHT-PWM
8. GND
9. POWER-OK
1M95 (B01)
1. +3V3STDBY
2. STANDBY
3. GND
4. GND
5. GND
6. +12VS
7. +12VS
8. +12VS
9. +24VAUDIO
10. GNDSND
11. N.C.
1735 (B03)
1. LEFT_SPEAKER
2. GND-AUDIO
3. GND-AUDIO
4. RIGHT_SPEAKER
1M20 (B04c)
1. LIGHT-SENSOR
2. GND
3. RC
4. LED-2
5. +3V3STBY
6. LED-1
7. KEYBOARD
8. +5V
1KA2 (B08E)
1. GND |
11. VLS_15V6
12. VLS_15V6 |
33. VCC_3V3
34. VCC_3V3
|
78. VGH _35V
79. VGL_-6V
80. GND
1KA1 (B08E)
1. GND |
11. VLS_15V6
12. VLS_15V6 |
33. VCC_3V3
34. VCC_3V3
|
78. VGH _35V
79. VGL_-6V
80. GND
L
N
Board Level Repair
Component Level Repair Only For Authorized Workshop
USB
HDMI
TUNER
PHONE
SPDIF
HDMI
HDMI
VGA
LOUDSPEAKER
(5213)
8M20
8KA2
J23PJ1
8P
8KA1
1319
1P3
1316
1P3
HIGH VOLTAGE
TO BACKLIGHT
TO BACKLIGHT
32"
40"
TO BACKLIGHT
8319
8316
IR/LED BOARD
(1112)
J
KEYBOARD CONTROL
(1114)
E

Wiring Diagram 32" - 40" (Dali)

Block Diagrams
EN 37LC10.1L LA 9.
2010-Apr-06
Page 38
B02A
TUNER
B08A
TCON CONTROL
B08C
P GAMMA & VCOM & NVM
B08D
MPD
B08E
MINI LVDS
B04
MT5363:
B06E
VGA
B06C
ANALOG I/O - VIDEO
B06B
ANALOG I/O - AUDIO
B06D
USB
B05
HDMI & MUX
B04B
DDR
B04C
FLASH & EJTAG & DISPLAY INTERFACE
7700 MT5363BHMG
HDMI-LVDS
B05
MAC-CI
B04C
CONTROL
B04C
AUDIO-VIDEO
B06B
MT5363
18980_401_100329.eps
100402
VIDEO
AGC_IF
CI_MCLKI
CI_MDIO
G34
H33
F35
H35
M31
M33
IF_AGC
RF_AGC_SW
+5VTUN_DIG 1201 VA1E1BF2403
7302 TC90517FG
TUNER
DIGITAL
DEMODULATOR
9
IF_AGC
CI_MIVAL
DIF_N
DIF_P
10
9
58
IF_OUT+
3
RF_AGC
RF_AGC
8
+B
5207
SCL
SDA
7
6
(I2C)
4321
USB_DM
USB_DP
USB 2.0
CONNECTOR SIDE
SW UPLOAD
JPEG
MP3
AR10 AU10
USB_DP
USB_DM
AE
AO
1D01
1
2
4
3
AGC_RF
HDMI
B05
RX1
RX2
AP19
AT 19
AR16
AU16
AR18
AU18
AP17
AT 17
AP15
AT 15
AR12
AU12
AR14
AU14
AP13
AT 13
19
1
18 2
1
1902
3
4
7
9 10
12
6
M_RX2_2
M_RX2_2B
M_RX2_1
M_RX2_1B
M_RX2_0
M_RX2_0B
M_RX2_C
M_RX2_CB
M_RX1_2
M_RX1_2B
M_RX1_1
M_RX1_1B
M_RX1_0
M_RX1_0B
M_RX1_C
M_RX1_CB
HDMI 2
CONNECTOR
1
1901
3
4
7
9 10
12
6
19
1
18 2
HDMI 1 (SIDE)
CONNECTOR
PX1
PX2
TO DISPLAY
(TCON ON SSB)
TO DISPLAY
(TCON ON SSB)
1KA2
72
81
61
50
13
33
34
12
11
1KA1
81
72
79
78
61
2
10
1
1
7H01 VPP1501BFG
7K00 ISL24837IRZ
VL/VH
VH
REF
VOLTAGE
GEN
7L00 SL24016IRTZ
L
EVEL
SHIFTER
CS(1-12)
ASIC_CS
VLS_15V6
VCC_3V3
12
11
VLS_15V6
VGL_-6V
VGH_35V
2
10
INTERFACE
B08A
33
34
VCC_3V3
50
13
79
78
VGL_-6V
VGH_35V
VL
VH
VL
LLV(0-7)
RLV(0-7)
7218
7217
RF_AGC_SW
CI_MISTRT
TSO_VALID
11
29
30
IF_OUT-
AGCCNTI
59
TSO_SYNC
61
TSO_CLK
60
TSO_DATA0
DRAM
B04B
CONTROL
B04C
7708 NAND01GW3B2CN6F
FLASH
1G
RDQ
RA
PDD
NAND_PDD(0-7)
A1A1
+1V8_SW
SDRAM
512Mb
7601 H5PS5162FFR
SDRAM
512Mb
7600 H5PS5162FFR
VDD
VDD
RDQ(0-31)
RDQ(0-15)
RDQ(16-31)
RA(0-13)
PB
PR
Y
1C03
CVBS
CVBS_AV3
AP35
2
CVBS_2P
1C02
SC1_B
SC1_G SY0P
SPB0P
SPR0P
AP29
AR28
7
12
9
SC1_CVBS_OUT
AU30
PR0P
Y0P
PB0P
AK22
PBR0N
PB
PR
Y
1C01
PB1P_SC2
SY1P_SC2 SY1P
SPB1P
SPR1P
SY1N
AT27
AU26
7
12
9
PR1P_SC2
AP27
PR1P
Y1P
PB1P
AR26
Y1N
SY0N
Y0P
PB0P
PR0P
Y0N
AT 29
SOY0
2C15
2C06
GND_CVBS
AR36
CVBS_0N
2C06
5C05
5C02
5C01
5C05
5C04
5C03
3B08
3B11
3B07
3B09
SOY1-AV2
AP25
SOY1
3B02
3B05
3B03
3B01
3B00
CVI-1
CVI-2
AVI N
1
1E01
2
3
14
13
VGA_R
VGA_G
VGA_Rp
VGA_Gp
VGA_B
H-SYNC
V-SYNC
VGA_Bp
HSYNC
VSYNC
RP
GP
BP
1
6
10
11
5
15
VGA
CONNECTOR
AU22
AR22
AT23
AU24
AT25
RP
VSYNC
GP
BP HSYNC
SOG
GN
AP23
SOG
AR24
COM
2E08
2E03
RXO
RXE
B04C
Block Diagrams
EN 38LC10.1L LA 9.

Block Diagram Video

2010-Apr-06
Page 39

Block Diagram Audio

AUDIO
B02A
B06B
B06C
TUNER
1201 VA1E1BF2403
TUNER
ANALOG I/O - AUDIO
1B01
1B02
ANALOG I/O - VIDEO
1C12
AV IN
CVI-1
AUDIO
L/R
1C13
AV IN
CVI-2
AUDIO
L/R
IF_OUT+
IF_OUT-
SCL
SDA
IF_AGC
RF_AGC
B04C
1
2
3
1
5
3
5
3
+5VTUN_DIG
8
+B
10
11
6
7 9
3
RF_AGC_SW
5207
DIF_N
DIF_P
(I2C)
AIN1_L-SC1
AIN1_R-SC1
AIN0_L-SC2
AIN0_R-SC2
7302 TC90517FG
29
30
7217
RF_AGC_SW
ASPDIF_OUT
DIGITAL
DEMODULATOR
AGCCNTI
7218
3B28
3B27
3B30
3B29
Block Diagrams
TSO_VALID
58
TSO_SYNC
59
TSO_CLK
61
TSO_DATA0
60
9
IF_AGC
RF_AGC
DVI_AUL_IN
DVI_AUR_IN
AIN1_L
AIN1_R
AIN0_L
AIN0_R
B04
G34
H33
F35
H35
M31
M33
J28
AC36
AC37
V30
V29
V28
V27
MT5363:
7700 MT5363BHMG
MAC-CI
B04C
CI_MIVAL
CI_MISTRT
CI_MCLKI
CI_MDIO
CONTROL
B04C
AGC_IF
AGC_RF
ALI_DAC
B06B
ASPDIF
AIN_AADC_3_L
AIN_AADC_3_R
AIN1_L
AIN_1_R
AIN_0_L
AIN_0_R
EN 39LC10.1L LA 9.
MT5363
B06B
B04C
ALI_ADAC
CONTROL
AL_L
AR_R
USB_DM
USB_DP
PDD
V37
u36
AR10 AU10
B06B
B06D
B04C
NAND_PDD(0-7)
ANALOG I/O - AUDIO
PREAMPL
PREAMPR
B04C
RESET_AUDIO
B04C
B04C
SW_MUTE
USB
FLASH & EJTAG & DISPLAY INTERFACE
USB_DM
USB_DP
7B01
STANDBY
1D01
1
2 3
4
7708 NAND01GW3B2CN6F
FLASH
1G
CLASS-D & MUTING
B03
AOUTL
AOUTR
MUTE
A_STBY
USB 2.0
CONNECTOR SIDE
SW UPLOAD
4321
7400 TPA3123D2PWP
5
6
CLASS D
POWER
AMPLIFIER
4
6
JPEG
MP3
22
15
B04C
LEFT_SPEAKER
GND-AUDIO
RIGHT_SPEAKER
DC_PROT
7408÷7410
DC-DETECTION
5406
1735
1
2
3
4
SPEAKER
LEFT
SPEAKER
RIGHT
AVIN
B05
HDMI 1 (SIDE)
AV IN AUDIO
L/R
HDMI & MUX
1
18 2
19
HDMI 2
CONNECTOR
1
18 2
19
CONNECTOR
1C11
1902
1901
5
8
1
3
4
6
7
9 10
12
1
3
4
6
7
9 10
12
AV3_L_IN
AV3_L_IN
M_RX2_2
M_RX2_2B
M_RX2_1
M_RX2_1B
M_RX2_0
M_RX2_0B
M_RX2_C
M_RX2_CB
M_RX1_2
M_RX1_2B
M_RX1_1
M_RX1_1B
M_RX1_0
M_RX1_0B
M_RX1_C
M_RX1_CB
U29
U28
AP19
AT19
AR18
AU18
AP17
AT17
AR16
AU16
AP15
AT15
AR14
AU14
AP13
AT13
AR12
AU12
AIN_2_L
AIN_2_R
B05
RX0
RX1
HDMI
B04B
DRAM
RDQ
RA
B04B
RDQ(0-15)
DDR
RDQ(0-31)
7600 H5PS5162FFR
SDRAM
512Mb
VDD
RA(0-13)
7601 H5PS5162FFR
RDQ(16-31)
SDRAM
512Mb
VDD
A1A1
+1V8_SW
18980_402_100329.eps
100402
2010-Apr-06
Page 40

Block Diagram Control & Clock Signals

CONTROL + CLOCK SIGNALS
B06D
USB
B04C
CONTROLLER
B04B
DDR
B08A
TCON CONTROL
B08C
P GAMMA & VCOM & NVM
B04
MT5363
B04C
FLASH & EJTAG & DISPLAY INTERFACE
B08D
MPD
CONTROL
B04C
DRAM
B04B
GPIO
B04C
TO IR/LED PANEL
AND
KEYBOARD CONTROL
+3V3STBY
3
2
6
4
5
7
1M20
MT5363
7700 MT5363BHMG
OPWRSB
AT 21
AP21
UART
SERVICE
CONNECTOR
1701
3
2
1
AH14
STANDBYn
B01
STANDBY
OPWM_2
U0_RX
U0_TX
C5
PWM-DIMMI
B01
AG6
GPIO_42
GPIO_26
GPIO_21
PDD
H29
RCLK1#
RCLK1
AD3
AD1
EDID_WC
B06 B07E
A22
LCD-PWR-ONn
B04C
D28
LAMP-ON
B01A
DC_PROT
B03
B29
GPIO_9
RF_AGC_SW
B02A
B23
GPIO_32
BYPASS_MODE
B08C
G30
B25
A26
GPIO_5
USB_PWR_EN
B06D
E30
GPIO_6
USB_OCP
B06D
A30
GPIO_3
AN22
OIRI
RESET_DEMOD
B02B
AM35
ADIN_SRV_2
ORESET
KEYBOARD
RC
HDMI_CEC
AN14
HDMI_CEC
B05
ADIN_SRV_5
AL36
LED-1
OPCTRL_4
AU20
MUTE
B03
OPCTRL_3
AR20
SW_MUTE
B03
B04C
B04C
OPCTRL_0
AM21
POWER_DOWN
B04C
LED-2
2701
SDM
2700
PAN E L
4 3 21
USB_DM0
ADIN_SRV_4
AM37
USB_DM0
AJ5
USB_DP0
AK5
USB_DP0
USB 2.0
CONNECTOR
SIDE
1D01
3
4
2
1
USB_PWR_EN
7D00 TPS2041BD
USB_OCP
EN
OUT
OC
18980_403_100329.eps
100402
7710
CLK
CLK
J8J8 K8K8
TCK
RCLK0#
RCLK0
A2
B3
CLK
CLK
XTAL1
XTALO
1700 54M
AJ34
AJ36
RDQ
RA
SDRAM
512Mb
7601 H5PS5162FFR
SDRAM
512Mb
7601 H5PS5162FFR
TCON
CONTROL
7J00 ISL97653AIRZ
SDRAM
512Mb
7600 H5PS5162FFR
TDQ(0-15)
RDQ(0-15)
RDQ(16-31)
RA(0-13)
TA(0-12)
7708 NAND01GW3B2CN6F
FLASH
1G
NAND_PDD(0-7)
GPIO_7
GPIO_35
GPIO_24
AG4
GPIO_41
POWER-OK
B01A
+3V3STBY
AL22
ORESET
7701 BD45292G
VOUT
VDD
5
4
3
OSC_IN
OSC_OUT
SLOPE
CS
1H00 27M
B1
A1
L2
L1
T9
RST
RESET
B08C
U9
T16
RTC50_60
50Hz_60Hz
B08A
B08B
B08E
B08E
B08E
GSLOP
TCK#
P
GAMMA
7K00 ISL24837IRZ
OUT12
24
B08B
B08E
B08E
B08E
CS_L
OUT12
26
INCOM
OUTCOM
25
OUTCOM
VCOM
VH
VL
LLV(0-7)
RLV(0-7)
VCOM
BUFER
7L00 SL24016IRTZ
LEVEL
SHIFTER
CS(1-12)
ASIC_CS
RDQ(0-31)
Block Diagrams
EN 40LC10.1L LA 9.
2010-Apr-06
Page 41
I²C
DIGITAL Demod
B2B
TCON CONTROL
B08A
P GAMMA & VCOM & NVM
B08C
VGA
B06E
TUNER
B02A
CONTROLLER
B04C
HDMI & MUX
B05
CONTROLLER
B04C
B04B
DDR
1K00
DEBUG ONLY
RES
5
9
10
7700 MT5363BHMG
OSDA_0
OSCL_0
GPIO_44
CONTROL
AH1 7
AP3
AP1
SYS_EEPROM_WE
SDA-MAIN
SCL-MAIN
3718
3719
+3V3_SW
TUNER_DATA
TUNER_CLK
18980_404_100329.eps
100402
56
7702
M24C64
EEPROM
(NVM)
3717
3716
N34
N36
3727
3728
3746
3747
+3V3STBY
3746
3747
+3V3STBY
UART
SERVICE
CONNECTOR
3749
3748
1701
3
2
1
B04C
ERR
15
7703
1
6
10
11
5
15
VGA
CONNECTOR
SDA_VGA
SCL_VGA
1E01
12
15
3E21
3E22
DC_5V
3K40
3K41
VCC_3V3
BYPASS_MODE
56
7E00
M24C02
EEPROM
4E03
4E02
7
EDID_WC
7E01
B04C
MT5363
SDA-TCON
SCL-TCON
2
3
ROM_SDA
ROM_SCL
R7 P7
46 45
7302
TC90517FG
DIGITAL
DEMODULATOR
3352
3351
FE_SDA
FE_SCL
76
1201
VA1E1BF2403
MAIN
TUNER
ERR
16
3228
3230
TUNER_SDA
TUNER_SCL
12
14
7H01
VPP1501BFG
TCON
CONTROL
56
7K04
M24C64
EEPROM
12 13
7K00
ISL24837IRZ
VOLTAGE
GENERATOR
7 8
7
7K03
SL24837IRZ
I2C
SWITCH
HDMI 2
CONNECTOR
HDMI 1 (SIDE)
CONNECTOR
1901
16
15
3907
3908
AL14
AL12
1902
16
15
3915
3916
HDMI_PLUGPWR2
HDMI_PLUGPWR2
AN18
AM17
SIDE_HDMI_SDA1
SIDE_HDMI_SCL1
HDMI_SDA2
HDMI_SCL2
2
1
HDMI_SCL2
HDMI_SCL1
HDMI_SDA2
HDMI_SDA1
7900
M24C02
EEPROM
7901
M24C02
EEPROM
6
4
WP_TCON
RESET
MAIN NVM
SW
Programmable via USB
SW
SW
SW
Programmable via ComPair
Pre-programmed device
EDID
SW
EDID
SW
EDID
SW
3K56
3K55
7708 NAND01GW3B2CN6F
FLASH
1G
PDD
NAND
SDRAM
512Mb
7601 H5PS5162FFR
SDRAM
512Mb
7600 H5PS5162FFR
VDD
VDD
RDQ(0-31)
RA(0-13)
DRAM
B04B
RDQ
RA
3773
3772
+3V3_SW
1703
3
1
4
6
2
FOR DEBUGGING ONLY
4701
4702
B04C
B08A

Block Diagram I2C

Block Diagrams
EN 41LC10.1L LA 9.
2010-Apr-06
Page 42

Supply Lines Overview

SUPPLY LINES OVERVIEW
MAIN
POWER
SUPPLY
B01
DC - DC
B08A
TCON CONTROL
B04C
CONTROLLER
B06A
ANOLOG I/O - HEADPHONE
B04A
MTK POWER
B04B
DDR
B05
HDMI & MUX
B06D
USB
B06E
VGA
B04D
LV DS DISPLAY
B08D
MPD
B08E
MINI LVDS
B02A
TUNER
B02B
DIGITAL Demod
B03
CLASS-D & MUTING
B08B
TCON DC/DC
B06B
ANALOG I/O - AUDIO
B08C
P GAMMA & VCOM & NVM
1M99
11
66
77
88
1M95
+3V3STBY
18980_405_100329.eps
100402
B04d
B03,B04c,B06b
B03,B04a,c,d, B05,B06a,b,d
B02a
B02a,b,B03,B04c,d, B05,B06d,e
B02b,B04a,c B06a,b
B04a,b
B02b
B04a
B03
1M99
11
66
77
22
33
44
55
88
LAMP-ON
1M99
BACKLIGHT-BOOST
+12VDISP
BACKLIGHT-PWM
B04C
B04C
+12VS
99
GND-AUDIO
10 10
+5V_SW
+5V_TUN
+3V3_SW
+1V0_SW
+24VAUDIO
+12V_1
CONTROL
CONTROL
B04C
CONTROL
B06D
CONTROL
99
POWER-OK
22
33
44
55
STANDBY
B04A
CONTROL
11 11
7103 TPS54386PWP
Non
Synchronous
Converter
N.C.
5117
PWR5V_2
+3V3STBY
+3V3STBY
1902
18
HDMI 2
CONNECTOR
B01
+5V_SW
+5V_SW
HDMI_PLUGPWR1
B01
5116
5120
31,14
12
+1V8_SW
+1V2_SW
7116 TPS54386PWP
Non
Synchr
Conv
5104
511
31,14
12
VCC_3V3VCC_3V3
B08b
VCC_1V8VCC_1V8
B08b
VDD3V3IO
5H03
VDD3V3LVR S
5H02
VGH_35VVGH_35V
B08b
5H04
5H06
DDR2VDD
5H05
+1V0_SW
+1V0_SW
B01
+3V3_SW+3V3_SW
B01
+3V3_SW+3V3_SW
B01
+3V3_SW+3V3_SW
B01
+3V3STBY+3V3STBY
N.C.
+5V+5V
B01
+3V3STBY+3V3STBY
B01
+3V3STBY+3V3STBY
B01
B01
+1V8_SW+1V8_SW
S
ENCE+1V0_MT5363
B01
+1V8_SW+1V8_SW
1M20
8
5
TO IR/LED PAN E L
+12VS+12VS
B01
+5V_SW+5V_SW
B01
6125
B04a
SENSE+1V0_MT5363SENSE+1V0_MT5363
7107
IN OUT
COM
+5V_SW
+5V_SW
B01
+5V_SW
+5V_SW
B01
B01
PWR5V_1
1901
18
HDMI 1 SIDE
CONNECTOR
HDMI_PLUGPWR2
VDD1V8PLL
+VDISP+VDISP
B08b
VREF_15V2VREF_15V2
B08c
VLS_15V6VLS_15V6
B08b
B08a,c,d
B08a,c,e
B08c,e
B08a,e
B08e
VGH_35VVGH_35V
B08b
+VDISP-INT
+12VDISP+12VDISP
7802
LCD-PWR-ON
7800
B01
5800
5801
5802
B08b
VCC_3V3VCC_3V3
B08b
VGL_-6VVGL_-6V
B08b
B01
+5V_SW+5V_SW
+5V5_TUN+5V5_TUN
B01
+5VTUN_DIGITAL
+1V2_SW
+1V2_SW
+3V3_SW+3V3_SW
B01
B01
+3V3STBY
+3V3STBY
+5V_SW+5V_SW
B01
+12VS+12VS
B01
+24VAUDIO+24VAUDIO
B01
B01
+VDISP
VLS_15V6_B
VLS_15V6
+VDISP-INT+VDISP-INT
7J00 ISL97653
10
21
B04d
6J06
7J01
VGL_-6V
3J10
3J26
VGH_35V
3,4
VCC_3V3
5J00
B08a,b
39
VCC_1V8
6J02
4J02
4J01
4J04
LCD
SUPPLY
5118 5119
5225
+5VS
7216
IN OUT
COM
B01
+5V_SW+5V_SW
+2V5_SW
5324
7315
IN OUT
COM
5222
6900
6901
DC_5V
1E01
18
VGA
CONNECTOR
5H01
VDD1V8
5H00
3J12
+12VS
+12VS
+3V3_SW
+3V3_SW
B01
B01
32
VREF_15V2
7K00 ISL24837IRZ
VOLTAGE GENERA-
TOR
+VDISP+VDISP
B08b
B08d
VCC_3V3VCC_3V3
B08b
VLS_15V6VLS_15V6
B08b
Block Diagrams
EN 42LC10.1L LA 9.
2010-Apr-06
Page 43
Circuit Diagrams and PWB Layouts
18980_500_100329.eps
100329
DC-DC
B01 B01
2010-01-22
1
3139 123 6483
BR-M-50
PCB SB SSB DIGITIAL
GND
VIN
HSPA
INH
SYNCSWVFB
A
SW
PVDD1 PVDD2
EN1
SW1
BOOT1
SW2
FB2
EN2
BOOT2
FB1
ILIM2 SEQ BP
GND GND_HS
VIA2
VIA1
PVDD1 PVDD2
EN1
SW1
BOOT1
SW2
FB2
EN2
BOOT2
FB1
ILIM2 SEQ BP
GND GND_HS
VIA2
VIA1
VIA
5 3V
PIN
0V
0V
PIN
12V8
I127 C5 I128 C5 I129 C6
I130 C6 I131 C2 I132 C4 I134 C3 I135 C5 I136 F3
I137 E11 I138 E9 I139 F12
1M99
9 3V
B04C
6
2
F121 D10
F122 D10 F123 D10 F124 D4 F125 E2 F131 E7 F132 C1
F133 C7 F134 E12
ON
ON STBY
F135 B1 I104 F1 I105 E3 I106 E3
I107 E4 I117 E5 I118 E5 I119 E6 I120 E6 I122 F4
I123 F5 I125 C3
I126 C4 F107 B10 F108 B10 F109 B10
F110 B10 F111 B10 F112 B10 F113 C10 F114 C10 F115 C10
ROUND 4mm SCREW HOLE
0V
>1.5V6
9
1
1.5V
F116 D10 F117 D10 F118 D10 F119 D10 F120 D10
6122 F5 6123 D3 6124 D5 6125 C2
7107-1 E10 7107-2 F11 7116 E4 7117 B4 F102 A10
7
12V
SLOT SCREW HOLE
3V3
3V
0V
F103 A10
F104 A10 F105 B10 F106 B10
3138 D1 3139 F6 3140 C1
3142 F12 3143 E5 3144 F13 3145 F5
5103 D3 5104 E2
0V
ROUND 4.02mm SCREW HOLE
12V
5115 E6 5116 C6 5117 C3 5118 E9 5119 E11 5120 D3
5121 D3 6103 F3
3108 E3 3109 F3 3119 F6 3122 C7 3125 C7 3126 B11
3127 B11 3128 B11 3129 C11
0V
1M95
0V
0V
3130 D3 3131 D5 3133 F12
3134 F12 3135 C3 3136 C5
2186 E3 2187 E4 2188 F2
2189 F2 2190 F2 2191 F2 2192 F4 2193 F7 2195 F13
2196 F13 2197 F6 2198 B13
3105 F1 3106 F1 3107 D1
2164 D6 2165 E5 2166 F7 2167 E3 2168 B5
2170 C1 2173 F9 2174 F10 2175 F10
STBY
2176 F12 2180 C11
2181 F13 2182 F14 2185 E3
2149 D11 2150 B5
2151 F13 2152 C4 2153 C5 2154 C2 2155 C7 2156 C3
2157 C5
0V
0V
3V3
12V
7
25V
2158 D2 2159 C6 2160 C4 2161 C7 2162 D2
2163 D2
13 14
A
B
C
D
E
F
G
2135 B12 2136 C11 2137 C11 2138 F3
2139 F5 2140 F6 2141 D10 2142 D10 2143 D11 2144 D11
2145 D12 2146 C12 2147 D12
2148 D12 2131 B11 2132 B11
2133 B12 2134 B12
123 45
678 9 10111213 14
123 45678 9 101112
1
H
A
B
C
D
E
F
G
H
1M95 C10 1M99 A10 2123 B5 2124 F12 2125 B12 2126 B12
2127 B10 2128 B10 2129 B11 2130 B11
+12VS
F132
F125
68R3128
100p
2131
4
928
7
35
16
ST1S10PH
7107-1
1n0
2136
EMC HOLE
1X06
4u7
2192
3136 1R0
33n
2153
33n
213
16 17
+12VS_1
2152
6 87
415
9
1
14
10
Φ
TPS54386PWP
7117
312
11
5
I107
10p
2193
GND-AUDIO
RES
1n0
2144
F115
F118
SS34
6103
1X05
EMC HOLE
REF EMC HOLE
1X04
1X03
REF EMC HOLE
+24VAUDIO
10u
2168
10R
3145
I123
1%
390R
3119
2142
100n
F133
F124
2156
470p
1%
1K2
3106
2190
6.3V
100u
2133
100p
100p
1%
2128
3139
220R
2195
10n
I119
7
8
9
1M99
1
10 11 12
2
3
4 5 6
1-2041145-2
213510n
I129
+3V3_SW
I135
33n2167
I125
2187
10u
F116
+1V0_SW
F134
2160
4u7
10R
3109
REF EMC HOLE
1X02
I126
1X01
REF EMC HOLE
I120
22u
5116
2140
100u
6.3V
F104
30R
5120
F107
F103
10u
2186
F105
68R
I138
3126
I137
+3V3STBY
I136
2175
10u
F112
1%
3138
18K
I106
68R
3129
F123
F122
RES
2155
10u
10p
2164
RES
5121
30R
RES
3105
1K2
10p
2188
1%
22u
2182
33R
5118
RES
+12VDISP
1n0
2137
2139
F108
470p
5117
22u
I139
F110
SS34
6123
I104
I118
RES
1n0
2141
2197
10u
GND-AUDIO
2162
10u
22u
5115
8
9
1R03143
1
10 11
2
3
4 5 6 7
1M95
1-2041145-1
+12VS_1
F109
2145
1n0
RES
1%
3142
10K
2130100p
RES
F102
+1V2_SW
F117
RES
2189
10p
1%
4K7
3131
10R
3122
2157
470p
I134
I132
SS36
F111
6125
22u
2151
14
10
213
16 17
13
11
65 87
4
15
9
1
7116 TPS54386PWP
Φ
2
2124
220u 25V
6.3V
100u
2159
SS34
6124
100p2127
100u
2170
I105
GND-AUDIO
16V
F131
10R
3130
3108
1R0
1R0
3135
+12VS
100u 16V
2185
100u
F120
6.3V
2158
F114
10u
2191
6122
I122
SS34
100p2134
2181
22u
F121
SENSE+1V0_MT5363
2154
22n
F135
2165
33n
RES
10p
2163
F113
2129
3144
220R 1%
RES
100p
2176
4n7
1K5
3133
3134
1K0 1%
I131
2u2
2146
2147
100n
GND-AUDIO
100n
2148
2149
100n
100n
2126
2125
100n
3127
68R
RES
10u
5103
100K
3140
5104
22u
1%
RES
2161
10p
470p
2138
3125
1K5
100n
2143
2198
10n
2123
10u
16V
100u
RES
2150
2173
10u
10u
2174
RES
2166
10p
2180
1n0
2u0
5119
RES
+5V5_TUN
F106
I130
+5V_SW
11
+1V8_SW
7107-2
ST1S10PH
10
22u
2196
I128
+12VS
I127
1%1K0
3107
RES
I117
F119
100p
2132
POWER-OK
BACKLIGHT-BOOST
BACKLIGHT-PWM
STANDBY
LAMP-ON

10. Circuit Diagrams and PWB Layouts

SSB: DC-DC

EN 43LC10.1L LA 10.
2010-Apr-06
Page 44

SSB: Tuner

18980_501_100329.eps
100329
Tuner
B02A B02A
2010-01-22
1
3140 123 6483
BR-M-50
PCB SB SSB DIGITIAL
TUNER AGC VIF AGC
SUPPLY
OUTPUT
VIF-PLL
SINGLE REFERENCE QSS MIXER
AND SWITCHES
DEMODULATOR
SIF
AGC
AFC DETECTOR
PORTS
INTERCARRIER MIXER AND
AM-DEMODULATOR
I C-BUS TRANSCEIVER
2
RC VCO
NARROW-BAND FM-PLL
DIGITAL VCO CONTROL
SOUND TRAPS
4.5 to 6.5 Mhz
AUDIO PROCESSING
MAD
COM
OUTIN
I
O2IGND
O1
GND
MT
MT
TDA9886
47n2213
B06B
ATD
I237 F8 I238 F7 I239 G7 I240 G7 I242 H4 I243 H7 I244 H4 I245 H6 I247 H5 I249 H4 I251 H5
F236 A12
I254 A9 I255 F7
I232 E5
3223 -
Reserved
Near Tuner
RE_AGC
F242 A7 F243 A4 F244 B7 F245 C7 F246 C7 I220 A2 I221 A3 I222 A4 I228 E3 I230 E5 I231 E4
A212 C1
I233 E3 I234 E6 I235 E3
-
B04C
TDA9886/V3
4211
SAW FILTERS
F201 B1 F202 B1 F203 B1 F204 B1 F205 B1 F206 B1 F207 B1 F208 B1 F209 C1 F213 B1 F214 E3 F215 F7 F216 E11 F227 G8 F235 A11
5207 B2
F237 E1 F240 I2 F241 I2
8k2
B02B
Int
22u
DIA 1.2MM FT
2V
5225 A11 5226 C11 5227 C12 5228 C10 5229 C11 5230 C12 7212 E2 7213 F7 7216 A10 7217 A3 7218 B4 7219 A3 A210 E12 A211 E12
3247 I4
A213 C1 A214 C1 A225 C1
10K 0R
B04C
39k
RE_AGC
Reserved
2V
Near MTK5363
3262 C10 3263 D10 3264 A3 3265 A2 3266 A3 3267 A4 3268 B2 3269 A4 3270 B7
4208 B4 4209 D6 4210 H1 4211 I1
2289 C12
5212 E12 5213 E10 5222 A9
3224
2293 B6 2294 C2 2295 B2 2296 C2
3223 A7 3224 B7 3228 C6 3230 B6 3231 E4 3232 E2 3234 E7 3235 G7 3236 G7 3238 H7 3241 H4 3244 H4 3246 I4
2262 C6
3254 G8 3255 G8 3261 C7
Test Keep spaceing 3.5mm
2279 A10 2280 A11 2281 A11 2282 A12 2283 B10 2284 B11 2285 C12 2286 C10 2287 C12 2288 C11
B
2290 D12 2291 D10 2292 A4
2V1
2V
2233 E6 2235 F8 2236 G7 2237 G7 2240 G8 2243 H7 2244 H2 2245 H7 2246 H4 2247 H4 2250 H4 2251 I4 2252 I5 2258 C2
9
2263 C7 2277 A9 2278 A10
2V
2V1
13
A
B
C
D
E
F
G
H
I
A
10
C
D
E
2V3
0V
123 45678
2226 B5
10 11 12
DEMODULATOR
312111987654321
1V5
F
G
H
I
1201 B1 1211 E12 1213 E4 2213 B7 2225 C5
2228 E4 2229 E5 2230 E2 2231 E3 2232 E3
2231
470n
Note:
AGND
I238
AGND
AGND AGND
2244
10n
I245
10K
2282
100n
3270
RES
2250
I247
AGND
VPLL
F245
AGND
SIOMAD
14
TAGC
9
TOP
VAGC
16
1VIF1
2VIF2
VP20
19
NC
3 OP1
22 OP2
15
REF
11 SCL
10 SDA
SIF123
24 SIF2
12
6AFD
18 AGND
8AUD
17CVBS
5DEEM
7 DGND
FMPLL 4
13
7212
AFC
21
AGND
I234
4211
RES
1K0
3269
AGND
RES
100K
3267
F242
5213
390n
AGND
AGND
2247
1n0
220n
5227
220n
5226
A225
3255
75R
75R
3254
1213
I228
4M0
BC847B
7217
F202
I222
AGND
2284 10n
F243
F227
220n
I239
AGND
+5V_SW
5229
180p
2286
4208
10n
RES
RES
2243
4209
I243
323010R
F235
I230
F205
F214
AGND
+5VIF
AGND
2251
RES
33p
2288
10n
AGND
AGND
2235
15R
AGND
3234
I242
1n0
2233
3
F216
LD29150DT50R
7216
2
1
10K
3266
AGND
RES
33R
5225
AGND
RES
2262 100p
2290
27p
2
3264
10K
SI1013
7219
3
1
AGND
RES
RES
8K2
3223
+5VTUN_DIGITAL
AGND
100R
3244
RES
10n
2292
22p
3
41 5
2229
+5VS
45M75
1211
OFWM1971M
+5VIF
AGND
+5VIF
RES
3224
39K
1K0
3265
22u
2281
1n0
2246
I249
390p
2245
2213
AGND
RES
22u
3241
100R
A213
AGND AGND
AGND
+5V5_TUN
AGND
F201
47u
2294
2258 100n
10n
2280
F237
F240
F208
AGND
F204
220n
I244
2232
AGND
AGND AGND
100R
3232
I254
RES
22n
2230
3247
F213
1R0
A214
22u
2277
2237
470n
220R
3236
A211
I251
2291
180p
F206
AGND
10n
2236
7213
I255
3246
BC847B
1R0
330n
5228
22u
2279
AGND
7218
KTK5132E
1n5
2228
+5VTUN_DIGITAL
5K6
3238
F241
2296
100u
RES
I221
+5VS
I235
100p
2226
2225
100p
47n
2263
1R0
3235
F209 A212
I220
13
14 15
16
2
NC1
NC2
4
RF_AGC
3
SCL
6
SDA
7
8
+B
ANT_PWR
1
AS
5
IF_AGC
9
IF_OUT+
10
IF_OUT-
11 12
IF_OUT_ANALOG
TUNER
VA1E1BF2403
1201
10R3228
33R5207
AGND
AGND
2240
47p
3263
75R
3262
75R
F236
3231
AGND
I231
330R
100p
2295
AGND
22u
2283
3268
AGND
I233
AGND
+5VIF
10n
2287
2289
10n
27p
2285
AGND
1u0
2278
A210
RES
5212
F244
AGND
RES
2297
1n0
15p
2252
F246
AGND
4210
RES
AGND
F203
I240
5230
220n
F215
10u
5222
AGND
2293
47n
10K
3261
I237
AGND
AGND
F207
I232
IF_ATV
RF_AGC_EX
VIP_ATV
VIN_ATV
FE_SCL TUNER_SCL
FE_SDA
TUNER_SDA
RF_AGC_SW
RF_AGC
FE_SCL
FE_SDA
DIF_N
DIF_P
DIF_N
DIF_P
SIF_OUT_GND
SIF_OUT
IF_AGC
VIF1
CVBS_RF
VIF2
VIF1
VIF2
RF_AGC
TUNER_SCL
TUNER_SDA
Circuit Diagrams and PWB Layouts
EN 44LC10.1L LA 10.
2010-Apr-06
Page 45
Circuit Diagrams and PWB Layouts
18980_502_100329.eps
100329
Digital Demodulator
B02B B02B
2010-01-22
1
3140 123 6483
BR-M-50
PCB SB SSB DIGITIAL
X
XSEL
ADI_AI
ADQ_AI
AD_VREF
TSMD
TN
SLADRS
VSS
DR2VDD
DR1VDD
VDDS
AD_DVDD
AD_AVDD
PLLVDD
VDDC
PBVAL
RERR
RLOCK
RSEORF
SBYTE
SLOCK
SRCK
SRDT
STSFLG1
AGCCNTI
AGCCNTR
STSFLG0
SYRSTN
0 1
SCL SDA
FIL
AD_AVSS
AD_DVSS
PLLVSS
I
O
0 1
P N
P N
P N
AD_VREF
DTCLK
DTMB
S_INFO
0 1
AGCI
CKI
SCL SDA
COM
OUTIN
D
E
F
G
H
1301 D3 2301 C6 2302 C6
123 456
91011
123 45678
B
C
11
A
B
C
D
E
F
G
7 8
2303 C6 2304 C6 2305 C7 2306 B6 2307 B6 2308 B6 2309 B6 2310 B7 2311 C6 2312 C6 2313 C7
910
25.4M
2316 D7 2317 D6 2318 C3 2319 C3 2320 B3 2321 B3 2322 B4 2332 F7 2333 D2
H
A
2336 E3 2337 E3 2338 E3 2339 E3 2340 E3 2341 E2 2372 A2 2373 A2
2314 C3 2315 C3
2376 A4 2377 E3 2378 E3
3331 E1 3332 E2 3335 H7 3336 H7 3337 F3 3339 F6
2334 D3 2335 D6
3349 F3 3350 G7 3351 G3 3352 G3 3353 E6 3354 D6 3355 D10 3356 D9
2374 A3 2375 A3
3359 E6 3360 G7
4300 H8 4301 H8 4303 E2
4304 E2 4305 G10 4306 G10 4307 H10
3343 H7 3344 H7
FOR DEVELOPMENT USE
5302 B7 5303 C7 5304 C3 5305 D7 5306 B3 5307 B3 5308 E2 5309 H10 5310 H10 5311 H11 5323 A1 5324 A3 6301 D10 7301 D9 7302 D4 7315 A2 F300 G2 F301 G2 F302 H7 F303 H7
3357 E6 3358 E6
I300 B4 I301 B4 I302 C4 I303 B5 I304 B5 I305 C5 I306 D6 I307 D3 I308 D3
4308 H10 4309 H11
B04C
B02A
B04A
B04C
4310 H10 4311 H11 5301 B7
I311 E4 I312 E4 I313 E4 I314 F4 I315 F4 I316 G4 I317 G4 I318 F3 I319 D6 I320 D6 I321 E6 I322 E6 I323 E6 I324 E6 I325 F6 I327 H7 I328 H7 I336 A2 I337 A3 I338 H10
F305 A4 F306 G7
AGND
DGND
I309 E4 I310 E4
DGND
I301
I303I300
2334
F305
18p
2332
100n
DGND
I324
I323
I337
I304
30R
5306
I302
1u0
2318
DGND
1n2
5308
DGND
I312
RES
AGND
DGND
DGND
4304
4303
I328
F300
100n
2302
AGND
+3V3_SW
DGND
AGND
I308
2309
100n
F303
F302
+3V3_SW
2310
1u0
DGND
I315
DGND
DGND
DGND
DGND
AGND
+3V3_SW
DGND
DGND
100n2338
I307
100n
2376
5324
33R
2333
2319
100n
18p
30R
5305
AGND DGND DGND
I320
100n
2315
AGND
AGND
DGND
5323
33R
DGNDDGNDDGND
3344
2K7
DGND
DGND
DGND
AGND
AGND
DGND
F306
2317
100n
57
62
19
18
3
2
I325
49
64
4
1533374447
50
12 14
1 41
163656
63
13
35
45 46
6 5
52
61
60
51
38
42
8
39
40
21
58
20
17
53
54
55
59
31
26
25
24
9
10
7
11
34
48
43
29
30
27
28
2223
32
AGND
7302
TC90517FG
Φ
2301
100n
DGND
10K
3336
5307
30R
I309
I318
100n
2321
RES
2339
100n
2341
DGND
DGND
1u0
33R3354
12
AGND
1u02340
30R
5301
1u0
2305
100n
2312
2311
100n
2337 100n
1n5
I336
2335
I327
100n
2308
100n
2375
100n2336
2320
1u0
DEB
3355
1K0
DEB
SML-310
6301
AGND
+1V2_SW
I322
3 2
30R
5303
LD1117DT25
7315
1
10K
3335
2K7
3331
+5V_SW
AGND
2K7
3343
4301
4300
100n
2373
16V100u
2372
F301
1u0
2316
I306
AGND
I305
3332
2K7
3350
4K7
RES
3351
5310
100R
30R
1u0
2313
I321
I317
+2V5_SW
AGND
I316
333920K
10n
2322
10K
3337
16V47u
2374
I310
12
2314
1u0
12
3357 33R
2
33R3359
335833R
1
I313
3353
33R
7301 BC847BW
DEBDEB
3356
AGND
1K0
1301
2
4
1 3
3352 100R
100n
2378
DGND
2377
100n
4K7
3360
I314
RES
30R
5311
2307
4305
100n
4306
4307
43094308
4311
5302
30R
4310
30R
5309
I311
3349
10K
I338
DGND
+3V3_SW
I319
DGND
+2V5_SW
+1V2_SW
+3V3_SW
DGND
+2V5_SW
100n
2304
2303
100n
2306
100n
5304
30R
RESET_DEMOD
FE_SDA
FE_SCL
IF_AGC
DIF_P
DIF_N
TUNER_SCL
TSO_CLK
TSO_DATA0
TSO_SYNC
TSO_VALID
TUNER_SDA

SSB: Digital Demodulator

EN 45LC10.1L LA 10.
2010-Apr-06
Page 46

SSB: Class-D & Muting

18980_503_100329.eps
100329
Class-D & Muting
B03 B03
2010-01-22
1
3140 123 6483
BR-M-50
PCB SB SSB DIGITIAL
VCLAMP
MUTE
IN
BSL
SD
R
AVCC
L
BSR
GND_HS
L
PGND
AGND L R
L
OUT
R
BYPASS
1
R
0
PVCC
GAIN
VIA VIA
VIA
VIA
123 4
F
G
H
1402 B10 1403 C10 1735 B11 2400 B5 2401 B5
5678 9
2402 B6 2403 B6 2404 B4 2405 B4 2406 B4 2407 C4 2408 C4 2409 C4 2411 B6 2412 C6 2413 B8 2414 B8
A
B
C
D
E
5678 91011
123 4
RESERVED
2427 D10 2430 E9 2431 F9 2432 G3 3400 A3
10 11
A
B
C
D
E
F
G
H
3418 E5 3419 F5 3420 F7 3421 G7 3422 C9
DC-DETECTION
2415 C8 2416 C8 2417 D7 2418 D7 2419 B11 2420 B10 2421 B11 2422 F4 2423 G4 2424 F6 2425 G6 2426 D9
6400 E2 6401 F3 6402 F5 6403 H2 7400-1 B5
B04C
3401 B4 3405-1 B7 3405-2 B7 3405-3 B7 3405-4 B7 3406-1 D7 3406-2 D6 3406-3 D6 3406-4 D6 3408 F2 3409 F2 3410 F2 3411 E3 3412 E3 3413 E3 3414 F3 3415 F3 3416 F4 3417 G5
7409 D10 7410 D11 7411 E9 7412 E10 7413 F10
3423 D9 3424 D9 3425 D10 3426 F5 3427 G6 3428 F6 3430 E9 3431 E9 3432 E9 3433 E8 3434 F9 3435 F9 34
36 D4 3437 G2 3438 G3 3439 G4
4401 E5 5400 A5 5401 A6
5402 C7 5403 C7 5404 C8 5405 C8 5406 B10
I414 C6 I415 C7 I416 C7 I417 C7 I418 C7
B04C
B04C
B06A
B06B
7400-2 D3 7401 A4 7402-1 E3 7402-2 F3 7403 E5 7404 F6 7405 F5 7406 F7 7407 G7 7408 C10
I438 D10 I440 E5 I441 F6 I442 F9 I443 G3
7414 H3 F400 A4 F401 B2 F402 C2 F404 B11 F405 B11 F406 B11 F408 E2 F409 E5 F410 C10 F411 C2 F412 C2 F413 F3 F414 G2 F415 E7 F416 E4 F417 G2 I401 B5 I403 C4 I405 C4 I406 C4 I407 C4 I410 B3 I411 A5 I412 A6 I413 B6
RES
I419 C8 I420 C8 I421 B4 I422 F2 I423 F2 I424 E3 I425 E3 I429 F5 I430 F5 I431 F7 I432 G7 I433 E4 I434 C9 I435 E8 I436 E9 I437 F9
220n
2411
GND-AUDIO
GND-AUDIO
2424
4n7
RES
2432
1u0
3438
22K
3424
100K
GND-AUDIO
100K
F412
RES
3416
F411
2SD2653K
+24VAUDIO
7413
+12VS
BAT54C
6402
3430
47K
F406
GND-AUDIO
F405
7414 BC847BW
3405-2 22K27
F415
F414
5401
220R
6400
BAS316
RES
3405-1 1 8
3436
4K7
22K
I413
22u
5402
3415
RES
7408
1R0
+3V3STBY
BC857BW
3406-1 22K1 8
2SD2653K
7412
1K0
3435
15
2
11
22
4
23
24
13
14
1
3
10
12
6
8
9
19
20
21
16
7
18 17
25
5
7400-1
TPA3123D2PWP
CLASS-D
Φ
AUDIO AMP
RES
2431
4n7
6401
BAS316
I411
2
6403
BAT54C
7403 BC847BW
1
3
4
F410
BC857BS(COL)
5
3
1
3
2
7402-2
3426
BC857BW
7404
1
3
2
47K
7401
BC847BW
GND-AUDIO GND-AUDIO
GND-AUDIO
+24VAUDIO
39
40
27 28 29
30
31
32
33
34
VIA
26
35
36
37
38
10K
+3V3STBY
7400-2
TPA3123D2PWP
3417
RES
3414
100K
220n
2414
F402
2425
RES
4n7
F401
I440
I419
BC857BW
1
3
2
I435
2417
220n
7411
GND-AUDIO
I420
2404
220n
I436
2426
I434
4u7
2408
1u0
3406-33 6
F413
I407
22K
22K3406-2 2 7
GND-AUDIO
I416
35V10u
2405
I415
I441
I442
3427
1K0
7406 2SD2653K
2402
220n
35V220u
2403
47K
100K
3425
2421
3421
10n
I424
F417
I429
I443
3439
10K
3437
3K0
2407
47n
6
I401
3405-3 22K
3
3423
100K
100K
220n
3422
470u 16V
2418
2422
1K8
3413
4401
4K7
3410
BC857BW
7409
4R7
22K
3400
3401
GND-AUDIO
GND-AUDIO
I430
3433
3431
47K
10K
BC847BW
GND-AUDIO
+3V3STBY
7410
+5V_SW
220n
2413
2406
47n
2416
220u
I412
25V
22u
5403
3432
1K0
I403
1u0
2409
F404
2SD2653K
7407
3428
I433
I422
1K0
I405
10n
2419
F409
I414
2427
4u7
220R
I437
5400
2420
10n
1 2
3
4
RES
2041145-4
1735
4n7
2430
10K
3419
47K
3420
I423
2400
220n
I417
3434
47K
4K7
3411
220R
5405
220R
5404
47K
3408
RES
I432
I431
F408
+12VS
220u
2401
3
1
2
35V
BSS84
7405
2412
220n
22K45
3405-4 22K45
3406-4
1K0
3412
F400
I410 I421
GND-AUDIO
1403
V_NOM
F416
1402
V_NOM
5406
220R
I418
2
6
1
I438
BC857BS(COL)
7402-1
I425
2415
220u25V
RES
3409
56K
2423
100n
3418
1K0
A_STBY
RESET_AUDIO
I406
LEFT_SPEAKER
RIGHT_SPEAKER
HP_LOUT
SW_MUTE
DC_PROT
AOUTL
HP_ROUT
AOUTR
MUTE
A_STBY
LEFT_SPEAKER
RIGHT_SPEAKER
AOUTR
AOUTL
Circuit Diagrams and PWB Layouts
EN 46LC10.1L LA 10.
2010-Apr-06
Page 47

SSB: MTK Power

18980_504_100329.eps
100329
MTK Power
B04A B04A
2010-01-22
1
3140 123 6483
BR-M-50
PCB SB SSB DIGITIAL
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
VCCK
VCCK
VCC2IO
VCCK
VCCK
VCCK
VCCK
VCCK
VCC2IO
VCCIO33-1
VCC2IO
VCCIO33
VCC2IO
VCC2IO
AVSS33
AVSS12AVDD12
AVDD33
CVBS
DEMOD1
DIG
HDMI
LVDS
REF_AADC
SIF USB_1 USB_2 USB_3
VDAC
VGA_STB
XTAL
LVDS
MEMPLL
PLL_1 PLL_2
RGB USB
VPLL
AADC ADAC0 ADAC1
USB VPLL
AADC ADAC0 ADAC1 CVBS DEMOD1 DIG HDMI LVDS_1 LVDS_2 REF_AADC SIF USB VDAC VGA_STB XTAL_STB
AVDD10_LDO
ADCPLL APLL HDMI LVDS MEMPLL RGB SYSPLL TVDPLL
B01
F503 B8 I502 D3 I503 B5 I504 C5 I505 D4 I506 D4 I507 E3
2584 C3 2588 C3 2592 D3 2593 E3 2595 E3 2596 E3 2597 D4 2598 C5 2599 D4 3500 B5 5500 B6 5501 B3 5502 D3 5503 D3 5504 D3 5505 E3 5506 A8 7700-7 C5 7700-8 A10 F500 B3 F501 F6 F502 B6
2553 B4 2558 B5 2559 B5
2560 B5 2561 B5 2562 B5 2563 B5 2564 B5 2565 B6 2566 B6 2567 B6 2568 C3 2569 E3 2570 E4 2571 C3 2573 C3 2574 C4 2575 C4 2576 C4 2577 C3 2579 E4 2580 C4 258
1 C3
2582 C3
2532 F8 2533 F8 2534 F8 2535 F8 2536 F8 2537 F8 2538 F8 2540 F7 2541 F7 2542 F7 2543 F7 2544 F7 2545 F7 2549 F7 2550 F6 2551 F6 2552 B4
2516 B8 2517 B8 2518 B8 2519 B9 2520 B9 2521 B9 2522 B9 2523 F9 2524 F9 2525 F9 2526 F9 2527 F9 2528 F9 2529 F8 2530 F8 2531 F8
2501 C8 2502 C8 2503 C9 2504 C9 2505 C9 2506 C9 2508 D8 2509 D9 2510 D9 2512 D9 2513 D9 2514 B8 2515 B8
3 45678 910
123 45678 91011
12 11
A
B
C
D
E
F
G
A
B
C
D
E
F
G
2500 C8
+3V3STBY
SENSE+1V0_MT5363
100n2502
2503 100n
100n
2506
2571 1u0
100n2565
100n
2570
2573 100n
100n2504
100n
2532
2531100n
100n
2530
2528
2529 100n
2527 100n
100n
F503
F502
F500
F501
+1V8_SW
1R0
3500
2595 10u
4u7
100n
2536
2550
100n2513
4u7
2512 100n
2567
100n2508
2509 100n
100n2510
2593 100n
1u0
2599
2592 1u0
30R5504
AE20 AE22
Y13 Y15 AA14 AD15 AD17 AD19
AN2 AN4 N22
V13
N24 T25 V25 W24 Y25 AA24 AB25
AK7 AL2
U14
AL4 AL6 AL8 AM1 AM3 AM5 AM7
W34 W36
R16
AE14 AE16 AE18 AG12 AH7 AJ6 AJ8 AK5
D13 E4 E12 E14
AF13 AF15
H23 H31 J30 V31 W32
B13
AD5 AD7 AE2 AE4 AF1 AF3
C2 C12 D3
B1
F5 F13 G6 G14 H7 J14 R2 R4 R6 AC6
AB23
AC20
J4
AC22 AC24 AD21 AD23 AD25
AE24
J6 L4
V21
G10
V23 W20 W22
Y21
Y23
AA20 AA22 AB21
P23
G8
P25
R20
R22
R24
T21
T23
U20
U22
U24
AC18
F9
AD13
AE8
AF9
B21
D21
E22
G22
N20
P21
E8
Y19
AA16 AA18 AB13 AB15 AB17
AB19 AC14 AC16
D9
V15 V17 V19
W4
W6 W14 W16 W18
Y3
Y17
C8
L6 N14 P15 R14 R18 T15 T17 T19 U16 U18
POWER-MAIN
MT5363BHMG
7700-8
+1V0_SW
+1V2_SW
100n
2574
100n2576
2575 100n
100n2501
2535100n
30R
5500
2569
100n
100n2568
2566 100n
2518
2598
4u7
100n
6.3V100u
2551
2582
100n2552
2579
4u7
100n
2515 100n
2542
100n
100n
2526
2525 100n
2580 100n
2562 100n
+3V3_SW
+3V3STBY
+3V3_SW
100n
2564 100n
2596
30R
5506
100n2563
I506
2500
4u7
2577 100n
2505 100n
I505
I507
100n
2543
100n
2541
I503
2584 100n
2560 100n
100n
2545
100n
2544 100n
2553
4u7
30R5505
2588
I502
2519 100n
I504
100n2520
100n2522
2521 100n
4u7
2514
2597
1u0
100n2516
2517 100n
5502
100n
30R
2537100n
2581
2533 100n
100n
2549
550330R
100n2561
100n2559
2558
5501
30R
100n
100n
2534
100n2524
2523 100n
2540 100n
100n2538
AN12
J18
Y29
AK29
AP9
AT9
AT11
AR30
AL24
AK37
AH29 AH31 AN26
AM9
P19
Y33
AE34
U30 AR32 AG36
AJ30 AM13 F15 H15 W30 AL30 AM11 AN30 AN24 AK35
P17 T13
AG32 AF29 AL10 N18
Y31 AF33 T31 AN32 AG34 AK31
AM23
AH33 AG30 AP11 N16 P13 AM25
POWER-MISC
MT5363BHMG
7700-7
Circuit Diagrams and PWB Layouts
EN 47LC10.1L LA 10.
2010-Apr-06
Page 48

SSB: DDR

18980_505_100329.eps
100329
DDR
B04B B04B
2010-01-22
1
3140 123 6483
BR-M-50
PCB SB SSB DIGITIAL
12
11
10
9
8
7
6
5
4
3
0 1 2
3
4 5 6 7
8
9 10 11 12
CK
VDDL
VREF
VSSDL
14
VDDQ
QSSVSSV
BA
A
LDQS
UDQS
NC
DQ
CKE WE
ODT
RAS
1
CS
CAS
0
0 1 2
VDD
LDM
UDM
15
13
RDQS0
RDQS1
RDQS2
RDQS3
RDQM
RDQ
RA
RBA
RVREF
11 12 13
0 1 2
RCLK0
RRAS
RCLK1
RCAS
RCKE
REXTDN RODT RCS RWE
19 20 21 22 23 24 25 26 27 28 29
30 31
0 1 2
3
1 2
0 1 2
3
4 5 6 7
8
9 10
0 1 2
3
4 5 6 7
8
9 10 11 12 13 14 15 16 17 18
12
11
10
9
8
7
6
5
4
3
0 1 2
3
4 5 6 7
8
9 10 11 12
CK
VDDL
VREF
VSSDL
14
VDDQ
QSSVSSV
BA
A
LDQS
UDQS
NC
DQ
CKE WE
ODT
RAS
1
CS
CAS
0
0 1 2
VDD
LDM
UDM
15
13
F601 I9
3611-4 H6 3612 D6 3613 D6 3614 D6 3615 D10 3616 D9 3617 H6 3618 I6 3619 I6 3620 I10 3621 I9 3622 A1 3623 B1 3624 D1
7600 B7 7601 G7 7700-3 A2 F600 D9
3609-2 H6 3609-3 G6 3609-4 G9 3610-1 G6 3610-2 G6 3610-3 G6 3610-4 G6 3611-1 G6 3611-2 G6 3611-3 G6
3607-4 H6 3608-1 H6 3608-2 H6 3608-3 H6 3608-4 H6 3609-1 H6
3604-4 C6 3605-1 D6 3605-2 B6 3605-3 B6 3605-4 B6 3606-1 G6 3606-2 G6 3606-3 G9 3606-4 H6 3607-1 H6 3607-2 H6 3607-3 H6
3601-2 D6 3601-3 C6 3601-4 C6 3602-1 D6 3602-2 C6 3602-3 C6 3602-4 C6 3603-1 B6 3603-2 B6 3603-3 C6 3603-4 C6 3604-1 B9 3604-2 C6 3604-3 D6
F
2623 F9 2624 F9 2625 F10 2626 F10 2627 F10 2628 F10 2629 I9 2630 B1
3600-1 C6 3600-2 C6 3600-3 C9 3600-4 C6 3601-1 D6
7 8 9101112
123 45678 9101112
A
B
C
D
E
2606 B10 2607 B10 2608 B10 2609 D9 2620 F9 2621 F9 2622 F9
123 456
F602 A2
G
H
I
A
B
C
D
E
F
G
H
I
2600 B9 2601 B9 2602 B9 2603 B9 2604 B9 2605 B10
56R3604-3
3608-1
56R
56R
3602-4
56R
3602-3
56R3605-3
3605-4 56R
56R3607-2
3600-2
56R
56R3608-2
56R
3608-3
100R
3624
3604-2
56R
56R3601-1
22R 1%
3612
3603-3 56R
D2
D8
E7
F2
F8
H2
K3
100n
2602
J2
A3
E3
J3
N1
P9J7A7
H8
B2
B8
A9G9C1C3C7C9E9G1G3
G7
K9
K7
B3
B7 A8
A1E1J9M9R1
J1
C2
F3 F7 E8
A2
E2
L1
R3 R7 R8
D1 D9
B1
B9
H7 H3 H1 H9
F1
F9
C8
L3
L7
J8
K2
K8
L8
G8 G2
D7 D3
P7 R2
M7 N2 N8 N3 N7 P2 P8 P3
L2
SDRAM
H5PS5162FFR-S6C
7600
M8 M3
M2
Φ
56R
3609-3
F602
56R
3606-2
47u
2608
16V
3610-4 56R
56R3610-3
56R3602-1
56R
3609-2
3606-3
56R
56R
3602-2
N6
P5
N8 P7
K3
56R3600-1
U6
B9 A8 B7 C6 V3
W2
Y1
AA2
AB5
T5
Y7
H13
D5
F11
F7
B5
D11
E10
C10
V1
T3
AC2
U2
AB3
Y5
T7
AA6
V7 V5
AA4
G12
B11 A12
C4
A10
A6
AB1
U4
AC4
T1
E6
H1
L2
K1
B3 A2 AD1 AD3
P3
D7
H11
A4
M1
M3 G4 M5 F1 M7 F3 P1 D1
H3 J2
DRAM
MT5363BHMG
7700-3
N4 H5
G2 N2 E2
3609-4
56R
3611-1 56R
3606-4
+1V8_SW
56R
1%22R
3613
3604-4
56R
56R3611-3
3621
1%
1K0
1%1K0
3620
100n2621
56R3610-2
1%22R
3617
56R
3611-4
3611-2 56R
56R3603-4
3603-2 56R
56R
56R
3604-1
3610-1
3601-2 56R
56R
3607-3
3607-4
56R
2600
100n
2607
100n
100n
2606
3608-4
56R
3609-1
56R
3614
100R
3600-4 56R
3616
1K0 1%
100n
2623
2622 100n
2620 100n
+1V8_SW
3606-1 56R
56R
47u 16V
3607-1
2628
56R3605-2
56R
3603-1
3605-1
56R
56R
3601-3
F601
F600
2609
100n
100n2627
2626 100n
2630
100n
56R
3600-3
+1V8_SW
3622
1K0 1%
100n
2629
3615
1K0 1%
K3
100n
2601
J7
A7
H8
B2
B8
D2
D8
E7
F2
F8
H2
C9E9G1G3G7
J2
A3
E3
J3
N1
P9
E1J9M9
R1J1A9G9C1C3C7
L1
R3 R7 R8
K9
K7
B3
B7 A8
A1
H1 H9
F1
F9
C8 C2
F3 F7 E8
A2
E2 L8
G8 G2
D7 D3 D1 D9
B1
B9
H7 H3
N7 P2 P8 P3
L2 L3
L7
J8
K2
K8
M8 M3
M2 P7 R2
M7 N2 N8 N3
7601
H5PS5162FFR-S6C
SDRAM
Φ
100R
3619
+1V8_SW
3618
22R 1%
2624 100n
3601-4
56R
100n2625
3623
1K0 1%
+1V8_SW
100n
2605
2604
100n
RDQ(4)
RDQ(3)
RDQ(2)
RDQ(1)
RDQ(0)
2603
100n
RDQM(1) RDQM(0)
RA(13)
RBA(2)
RDQ(15)
RDQ(14)
RDQ(13)
RDQ(12)
RDQ(11)
RDQ(10)
RDQ(9)
RDQ(8)
RDQ(7)
RDQ(6)
RDQ(5)
RDQM(3)
RDQS(2) RDQS(2)# RDQS(3)
RDQM(2)
RCLK1
RCLK1#
RCAS#
RBA(2)
RA(13) RBA(0) RBA(1)
RCKE RWE# RCS#
RODT
RRAS#
RA(1) RA(2) RA(3) RA(4) RA(5) RA(6) RA(7) RA(8) RA(9) RA(10) RA(11) RA(12)
RCAS#
RCKE RWE#
RBA(0) RBA(1)
RODT
RCS# RRAS#
RCLK0
RCLK0#
RDQ(29) RDQ(30) RDQ(31)
RA(0) RA(1) RA(2) RA(3) RA(4) RA(5) RA(6) RA(7) RA(8) RA(9) RA(10) RA(11) RA(12)
RA(0)
RDQS(0)#
RDQS(0)
RDQ(16) RDQ(17) RDQ(18) RDQ(19) RDQ(20) RDQ(21) RDQ(22) RDQ(23) RDQ(24) RDQ(25) RDQ(26) RDQ(27) RDQ(28)
RDQ(23) RDQ(24) RDQ(25) RDQ(26) RDQ(27) RDQ(28) RDQ(29) RDQ(30) RDQ(31)
RDQS(3)#
RDQS(1)#
RDQS(1)
RA(6) RA(7) RA(8) RA(9) RA(10) RA(11) RA(12) RA(13)
RBA(1) RBA(2)
RDQ(1) RDQ(2) RDQ(3) RDQ(4) RDQ(5) RDQ(6) RDQ(7) RDQ(8)
RDQ(9) RDQ(10) RDQ(11) RDQ(12) RDQ(13) RDQ(14) RDQ(15) RDQ(16) RDQ(17) RDQ(18) RDQ(19) RDQ(20) RDQ(21) RDQ(22)
RA(0)
RBA(0)
RCAS#
RCKE
RCLK0 RCLK0# RCLK1 RCLK1#
RCS#
RDQM(0)
RDQS(0)
RODT
RRAS#
RWE#
RDQ(0)
RDQS(1)
RDQS(0)#
RDQS(2)
RDQS(3)
RDQS(1)#
RDQS(2)#
RDQS(3)#
RDQM(1) RDQM(2) RDQM(3)
RA(1) RA(2) RA(3) RA(4) RA(5)
Circuit Diagrams and PWB Layouts
EN 48LC10.1L LA 10.
2010-Apr-06
Page 49

SSB: Controller

18980_506_100329.eps
100329
Controller
B04C B04C
2010-01-22
1
3140 123 6483
BR-M-50
PCB SB SSB DIGITIAL
SUBERGND
VOUT
VDD
SCL
ADR
0 1 2SDA
WC
GPIO GPIO
23 24 25 26 27 28 29
30 31 32 33 34 35 36 37 38 39
40 41 42 43 44
18 19 20 21 22
0 1 2
3
4 5 6 7
8
9 10 11 12 13 14 15 16 17
B
R
WP
VCC
VSS
IO
NC
0 1 2
3
4 5 6 7
CLE ALE CE RE WE
PDD
USB
ADIN_SRV
O
SDA
OSCL
TUNER
OPCTRL
OPWM
U0
RX TX
U1
POCE
HDMI
AGC
DEMOD
CLK
DATA
BYPASS
BYPASS0
ADCINP ADCINN
IF
RF
3
4 5 6 7
0 1
PARB
PAALE
PACLE
POWE
POOE
RX TX
PWR5V
SCL2
0 1 2
OIRI
0 1 2
3
4
OPWRSB
CEC
SDA1
SCL1
SDA2
0 1 2
ORESET FSRC_WR MEMTN MEMTP TP_VPLL
JTCK JTDO JTRST JTDI JTMS
0 1 2
0 1 2
0 1 2
3
4 5
DP DM VRT
XTALI
XTALO
VCXO
ETRXETTX
CICI
D0
D1
D2
D3
ER
EN
CLK
ETMDC
ETMDIO
MCLKO
MDO0
MOVAL
MOSTRT MISTRT
D0
D1
D2
D3
DV
ER
CLK
ETPHYCLK
ETCOL
ETCRS
MCLKI
MDI0
MIVAL
B06D
PWM DIMMING
ICE mode +ROM mode
FOR DEBUGGING
I739 I5 I741 D12 I742 F9 I743 F9 I744 H5 I745 H5 I746 H5 I747 I4 I749 H6 I750 I5 I752 J9 I753 I4 I754 H4 I755 I8 I756 G4 I757 G4
B05 B01
I737 K11 I738 K11
B03
F759 C7 F760 C7 F761 D8 F763 E16 F764 G16 F765 G16 F766 H16 F770 H7 F771 H6 I700 B3 I701 B3 I707 B2 I708 D10 I710 B3 I711 D7 I713 E6 I714 I13 I715 J11 I716 I12 I718 G16 I725 G2 I726 G8 I727 G8 I731 E10 I732 G8 I733 I4 I734 I5 I735 I4
B04D
F756 J16 F757 J15
B01
F758 J16
B05 B02B B06A
B02A
B04D
RES
F740 C5 F741 H2 F742 H2 F743 J9 F744 J9 F745 E16 F746 E16 F747 E16 F748 E16 F749 E16 F750 E16 F751 E14 F752 F16 F753 I16 F754 J16 F755 J16
B03
B2B
B02
B05
7709-2 K11 7710 I9 F701 D3 F702 C2 F704 C11 F705 D10 F706 D10 F707 D10 F708 D10 F716 J10 F717 H10 F718 H10 F719 H11 F721 G3 F723 F16 F724 K12 F725 J10 F736 D10 F737 B5 F738 C5 F739 C5
B06D
FRONT CONTROL
4708 I6 5700 C11 5705 E11 6700 H10 6701 H10 6706 F3 6707 G2 6708 K10 6709 K12 7700-1 F4 7700-4 B4 7700-6 A12 7701 F2 7702 D11 7703 D10 7705 I12 7708 E10 7709-1 K11
XTAL 54MHZ
B01
37A2 G15 37A3 G15 37A4 H14 37A5 G3 37A6 I8 37A7 I8 37A8 K5
4700 B6 4701 F14 4702 F14 4703 H3 4704 H3 4705 J8 4706 J8 4707 H6
SDM
PANEL
0
1
3774 G8 3775 G8 3776 E8 3777 E8 3778 E8 3779 G8 3780 E14 3781 J11 3782 E7 3783 H5 3784 K6 3785 K6 3786 C6 3787 I3 3788 H3 3789 J4 3790 I14 3791 I15 3792 I15
3793 J15 3794 J15 3795 K15 3796 C5 3798 J14 37A1 G15
0
TRAP2
ASPDIFAOLRCK
3759 F16 3760 F15 3761 H4 3762 D15 3763-1 E15 3763-2 E14 3763-3 E14 3763-4 E14 3764 J11 3765 E14 3767 J11 3768 F3 3769 G2 3770 K12 3771 K12 3772 F16 3773 F16
UART (SERVICE)
0
3736 H13 3737 I3 3738 I6 3739 E7 3740 D7 3741 D7 3742 I11 3743 J12 3744 I6 3745 I13 3746 G8 3747 G8 3748 H8 3749 H8 3751 I6 3752 I7 3753 I7 3754 I7 3755 I7 3756 K8 3757 J3 3758 H2
PDWNC Normal
1
AOBCK
TRAP1
3715 D9 3716 D10 3717 D10 3718 H3 3719 H3 3720 H3 3721 H3 3722 I10 3723 I10 3724 I10 3726 B6 3727 H6 3728 H6 3729 I8 3730 I8 3731 I3 3733 I8 3734 H6 3735 I3
0
0
2728 J16 2729 B13
3700 B2 3701 B2 3702 I9 3703 C6 3704 B2 3705 B2 3706 C2 3707 C2 3708 B2 3709 C7 3710 C7 3711 D11 3712 D10 3713 C10 3714 D10
RES
1M20 I17 2700 D2 2701 D2 2702 C11 2703 D10 2704 D10 2705 D5 2706 D7 2709 F2 2710 F2 2711 G3 2712 E11 2713 E11 2716 E2 2717 E3 2719 K7 2720 K7 2721 K12 2722 I15 2723 I15 2724 J15 2725 J15 2726 K15 2727 J16
ICE mode + Serial Boot
OPCTRL3(0)
0
2 3 45678 910111213 14 15 16 17
A
B
C
D
E
0
AOSDATA0
123 45678 9 10111213 14 15 16 17
1
ONLY
F
G
H
I
J
K
A
B
C
D
E
F
G
H
I
J
K
1700 E2 1701 H12 1702 E16 1703 F16 1705 H10 1706 H10 1707 G16
TRAP0
2
6
1
OPWM1
RES FOR ITV
10p
BC847BS
7709-1
2716
54M
1700
3735100R
100R 3734
F757
I713
F758
F718
+5V_SW
3741
1K0
4K7
F736
3706
I700
+3V3_SW
2727
100p
3774 4K7
1 2
3
4 5 6 7
8
1M20
2041145-8
F751
100n2702
3742
680R
3761
10K
330R3777
2721
220n
15K
3767
F725
5
3
4
F724
BC847BS
7709-2
F770
F755
3733 10K
DEB
+3V3_SW
3763-1
10K
2704
10K
10p
DEB
3760
4K73718
1 2
3
6
5
84
7
M24C64-WDW6
7702
EEPROM
Φ
(8K × 8)
I747
I752
+3V3STBY
I746
I715
1
3
2
5
4
F759
Φ
7701
BD45292G
6708
BZX384-C3V3
1R0
3724
F708
F752
I710
1705
I716
22R3717
F766
RES
3782
10K
1R0
F761
RES
3723
+3V3STBY
+3V3_SW
I745
DEB
4K7
3773
DEB
3772
4K7
10K3785
RES
3752 1K0
4K73783
RES
I735
4704
1n0
2724
I757
F739
F743
F742
100R
3781
F747
3787100R
3776
RES
4703
F717
4K7
3714 10K
I732
RES
3757
10K
4K7
6 7
8
9
12
13
3756
DEB
1
10 11
2
3
4 5
502382-1170
1702
10K
3703
I755
37A7
RES
10K
I701
F702
I733
2712
100n
2725
1n0
3729
10K
2717
10p
2703
10p
BC847BW
7705
10K
3701
3700
3705
100R
10K
F764
100n
2726
4705
5705
220R
RES
10n
2705
RES
6700
BZX384-C6V8
2728
100n
100R
3791
I718
I742
2
1
3
+3V3_SW
1701
MSJ-035-29D PPO
+3V3_SW
+3V3_SW
+3V3_SW
3792
100R
3778 10K
4K7
3779
RES
F746
I708
F756
3769
100K
DEB
4K7
F754
F753
37A2
3794
I727
100R
6K8
3798
47n
2720
2710
4u7
100R
3744
+3V3_SW
1R0
3739
DEB
100R37A3
I754 I753
I744
F744
33R3748
3728100R
BAS316
6707
BAS316
6706
F765
RES
3740
2706
10K
1u0
47n
2719
F704
F748
I750
+3V3_SW
DEB
37A4
4K73775
100R
F707
+3V3_SW
+3V3_SW
F719
I734
I756
3754 4K7
+3V3STBY
F749
+3V3_SW
+3V3STBY
+3V3_SW
+5V_SW
H29 F29 B29
AG2 AE6
C30
AF7 AG4 AG6 AH3 AH1
G30 E30
C24 G24
A30
E24
J24 B23 F23 D23 A22 C22 AF5
D27 G26
J32
E26 A26 C26
J26 F25 H25 B25 D25
K35 K37
D29 C28 E28 J28 G28 H27 F27 B27
GPIO
MT5363BHMG
7700-4
+3V3STBY
3759
10K
DEB
+3V3_SW
F738
3770
1K0
F716
4K73721
4K73720
RES
3751
RES
100R
2729
10p
F771
RES
I743
I741
I749
DEB
33R
I711
3765
I725
5700 30R
+3V3STBY
F705
4K73753
4707
RES
4706
3727
100R
3709
100R
+3V3STBY
4
56
DEB
B4B-PH-SM4-TBT(LF)
1707
1 2
3
100R3704
+3V3_SW
1706
3
4
56
DEB
1703
B4B-PH-SM4-TBT(LF)
1 2
100n
I737
2713
F745
4700
37A8
3712
2K2
33R
7703 BC847BW
RES
1K03755
DEB
3780
10K
100n
2711
RES
1K0
3768
RES
3790
100K
3795
10R
BZX384-C6V8
6701
3731
10K
3758 10K
3796 100R
+3V3_SW
+3V3_SW
+3V3STBY
3738
100R
3762
DEB
1K0
4K7
3710
RES
4708
F750
F737
I726
F741
F721
3715 10K
4K7
37A6
3745
10K
RES
1K0
I707
3708
4702
DEB
2723
1n0
10 11 14
8
7
12
37
13
36
18 19
40 45 46 47 48
3
4 5 6
24 25 26 27 28
2
33 34 35 38 39
41 42 43 44
1
15 20 21 22 23
7708 NAND01GW3B2CN
Φ
17 9
16
29
30 31 32
[FLASH]
1G
F701
4K7
3726
+5V
+12VS
100n
100n
RES
2700
RES
4K7
37A5
2701
1K0
RES
3743
10K
3713
1K0
3764
F740
F760
4K7
3707
10K
3786
10K
I731
3763-3
DEB
DEB
4701
100R3737
5K1
3789
1n0
2722
RES
1%
I738
3747
33R3749
4K7
+3V3_SW
AJ36
AJ34
AP37
N36 N34
AT21 AP21
R36
T35
AR10
AU10
AN10
T37
AR8 AU8
AT1 AN6
AU2
AT3
AL16 AM15
M33
M19
P33
AR4 AU4
AT5
AR2 AP5 AR6 AU6 AP7 AT7
AU20
J34 J36 T33
AL20
AL22
AP3 R34 P31
AP1 R32
AJ2
AH5
AJ4
AK1
K5 K7
AN22
AM21 AM19 AN20 AR20
AL36
AM31
L30
AN14
AM17
AL12
AN1
8
AL14
M31
AK3
MT5363BHMG
7700-1
AH35
AH37
AL32 AK33 AM35 AL34 AM37
+3V3_SW
CONTROL
F763
22R3716
B37
D35
D33
A32
C32
E32
B31
D31
E34
G36
G32
C36
E36
D37
F31
B33
A36
B35
A34
C34
MAC-CI
MT5363BHMG
7700-6
F35F33
H35H37
H33
G34
F37
+5V_SW
10K3784
37A1
4K7
DEB
3711
4K7
BZX384-C8V2
6709
4u7
2709
7710
BC847BW
3746
4K7
3722
1R0
RES
DEB
3763-4
10K
3719 4K7
I739
+3V3_SW
+3V3STBY
F706
3736
4K7
+3V3_SW
RES
100R3788
3763-2
10K
DEB
100R
3793
I714
F723
3730
10K
3702
4K7
3771
+3V3_SW
1K0
+3V3_SW
BYPASS_MODE
POWER-OK
LAMP-ON
RF_AGC_SW
IF_AGC
VIN_ATV
RF_AGC
VIP_ATV
BACKLIGHT-PWM
BACKLIGHT-BOOST
RC
MUTE
SW_MUTE
DC_PROT
TUNER_SDA
RESET_DEMOD
TUNER_SCL
BACKLIGHT_CONTROL
BOOST_CONTROL
U1TX
U1RX
NAND_PCLE
NAND_PARB
NAND_POCE
HP_DET
NAND_PALE
LED-1
LED-1
JTCK
ORESET
PWR5V_1
PWR5V_2
SIDE_HDMI_SCL1
SIDE_HDMI_SDA1
HDMI_SCL2
HDMI_SDA2
HDMI_CEC
SCL-MAIN
JTMS
JTDI
JTRST
JTRST
JTDO
JTDO
SYS_EEPROM_WE
DDC_RESET
LCD-PWR-ONn
USB_DM
USB_DP
SDA-MAIN
SDA-MAIN1
SDA-LCD
EDID_WC
PBS_SPI_DO
SCL-DISP
SCL-LCD
STANDBYn
SCL-MAIN1
KEYBOARD
KEYBOARD
SDA-DISP
LIGHT-SENSOR
LIGHT-SENSOR
LED-2
LED-2
SDA-MAIN
SCL-MAIN
PBS_SPI_CLK
PBS_SPI_DI
RESET_AUDIO
POWER_DOWN
POWER_DOWN
TSO_DATA0
TSO_SYNC
TSO_VALID
JTMS
JTDI
JTCK
NAND_PDD(0) NAND_PDD(1) NAND_PDD(2) NAND_PDD(3) NAND_PDD(4) NAND_PDD(5) NAND_PDD(6) NAND_PDD(7)
NAND_POWE
NAND_PARB
NAND_POOE
STANDBY
U1RX
U1TX
HP_DETECT
NAND_POWE
NAND_POCE
NAND_PDD(0) NAND_PDD(1) NAND_PDD(2) NAND_PDD(3) NAND_PDD(4) NAND_PDD(5) NAND_PDD(6) NAND_PDD(7)
NAND_POOE
SDA-MAIN
SCL-MAIN
RC
USB_PWR_EN
USB_OCP
RC1
RC2
NAND_PALE NAND_PCLE
TSO_CLK
Circuit Diagrams and PWB Layouts
EN 49LC10.1L LA 10.
2010-Apr-06
Page 50

SSB: LVDS Display

18980_507_100329.eps
100329
LVD S Display
B04D B04D
2010-01-22
1
3140 123 6483
BR-M-50
PCB SB SSB DIGITIAL
NC
7 8 9
A
B
C
D
E
F
A
B
C
D
E
NC
NC
F
1G51 A9 2803 C8 2804 E9 2805 E9 2806 E1 2807 F3
3802 E1 3803 E1 3804 E2 3805 E2 3806 F2 3807 F1 3808 F1 3809 F3 3900 F3
4800 D1
NC
LVDS#1
B04C
123 45678 9
123 456
4801 D1 4802 D1 4803 D1 4804 D1 4805 D1 4806 D2 4807 D2 4808 D2 5800 D3 5801 D3 5802 D3 6800 E1 7800 E2 7801 E3 7802 F2
F828 D8 F829 D9 F831 C8 I800 D1 I801 D2 I802 E1 I804 E3 I805 E2 I806 F1 I807 F2 I808 F2 I809 F3
7802 F2 7
803 F1 F800 E4 F801 A9 F805 B8 F806 B8 F807 B8 F808 B8 F809 B8 F810 B8 F811 B8 F812 B8 F813 B8 F814 C8 F815 C8 F816 C8 F817 C8 F818 C8 F819 C8 F820 C8 F821 C8 F822 C8 F823 C8 F824 C8 F825 D
8
F826 D8 F827 D8
10K
1K0
3808
3112
5
3
4
1K0
3809
2
6
1
BC847BS
7802-2
BC847BS
7802-1
2807
220n
47K
3805
15K
3806
10K
3807
7803
BC857BW
F806
I807
+12VDISP
I808
I809
+VDISP-INT
+3V3STBY
I806
BZX384-C6V8
6800
F817
F816
RES4806 RES4807
100n
2805
2804
100u 16V
61
53
54 55
56 57
58 59
60
48
49
5
50
51
6
7
8
9
52
39
4
40
41
42
43
44
45
46
47
29
3
30
31
32
33
34
35
36
37
38
19
2
20
21
22
23
24
25
26
27
28
1
10
11
12
13
14
15
16
17
18
RES
FX16S-51S-0.5SH
1G51
2806
1u0
I801
30R
5801
F815
4803
F814
F812
F829
I805
F831
F818
I800
F813
I804
RES 4802
2
3
F800
F801
SI4835DDY
5
6
7
8
4
1
+VDISP-INT
7800
F819
3802
47K
3803
47R
+5V_SW
RES4808
7801
RES
PDTC114ET
47K
3804
RES
F828
F827
F810
F826
RES
4800
F825
4805
RES 4801
10n2803
RES
I802
F807 F808
5802
30R
5800
30R
4804
F824
F823
F821 F822
F820
F811
F805
F809
PX1B+
LCD-PWR-ONn
PX1D-
PX1D+
PX1C­PX1C+
PX1B-
PX1CLK+
PX1E­PX1E+
PX2B­PX2B+
PX2A­PX2A+
PX1CLK-
PX2D­PX2D+
PX2C­PX2C+
PX2CLK­PX2CLK+
PX2E­PX2E+
PX1A­PX1A+
Circuit Diagrams and PWB Layouts
EN 50LC10.1L LA 10.
2010-Apr-06
Page 51

SSB: HDMI & Multiplexer

18980_508_100329.eps
100329
HDMI & Multiplexer
B05 B05
2010-01-22
1
3140 123 6483
BR-M-50
PCB SB SSB DIGITIAL
AE
0P 0N 1P 1N 2P 2N
3P 3N
4P
4N CKP CKN
AO
RX1
0 0B 1 1B 2 2B C CB
RX2
0B 1 1B 2 2B C CB
HDMI_HPD1
HDMI_HPD2
3N
4P
4N CKP CKN
0P
0N
1P
1N
2P
2N
3P
0
SCL
ADR
0 1 2 SDA
WC
SCL
ADR
0 1 2 SDA
WC
HDMI PORT 1 (SIDE)
H : WRITE
I903 F8 I904 G7 I905 H8 I906 B8 I907 C8
F906 F13 F907 G13 F908 G13 F909 G12 F911 I12 F912 H7 F913 D12 I900 B7 I901 B6 I902 C8
6917 G9 7700-5 F4 7900 B12 7901 F12 7902 C13 7903 G13 7904 B7 7905 D7 7906 G8 7907 H8 7908 B9 F900 D6 F901 B13 F902 B13 F903 C13 F904 C12 F905 C12
4904 C9 6900 D12 6901 I12 6902 B7 6903 C10 6904 D9 6905 D9 6906 D8 6907 D8 6909 H10 6910 H9 6911 H9 6912 H9 6913 A3 6914 B3
HDMI PORT 2
6915 C3 6916 E3
3921 H7 3922 G7 3923 H12 3924 C12
4900 C7 4901 D7 4902 H8 4903 H8
3904 G12 3905 H12 3906 B8 3907 C8 3908 C7 3910 C7 3911 B6 3912 C7 3913 D7 3914 D6 3915 G9 3916 G8 3917 G8 3918 G7 3919 G8 3920 H8
12 13
123 45678 910111213
A
L : WP
C
D
E
F
G
H
I
1901 B11 1902 F10 2900 B11 2901 F11
3111 C6 3900 B13 3901 C13 3902 C12 3903 F13
B04C
B04C
B04C
B04C
123 45678 91011
B
C
D
E
F
G
H
I
A
B
3924
68K
HDMI_PLUGPWR1
F903
DEB
HDMI_PLUGPWR1
3922
RES
5.6V
12
100K
12
RES
6912
CDS2C05HDMI2
RES
CDS2C05HDMI2
6911
5.6V
100K
3920
12
3
5.6V
RES
12
6901
BAT54C
CDS2C05HDMI2
6907
3916
4K7
I907
7904 BC847BW
RES
5.6V
6906
RES
12
AU16
AP13 AT13 AR14 AU14 AP15 AT15 AR12 AU12
CDS2C05HDMI2
C18
AL18
AN16
AP17 AT17 AR18 AU18 AP19 AT19 AR16
B15
D15
A16
C16
B17
D17
B19
D19
A20
C20
A18
G16
F17
H17
E18
G18
E20
G20
F21
H21
F19
H19
7700-5
MT5363BHMG
HDMI-LVDS
E16
5.6V
6904
CDS2C05HDMI2
RES
12
F912
F905
F900
F904
3917
RES
BC847BW
7906
4
RES
100R
RES
3
8
67 910
21
5
6913
IP4281CZ10
HDMI_PLUGPWR2
HDMI_PLUGPWR2
F909
I904
F908
3913
100K 1K0
DEB
HDMI_PLUGPWR2
3912
I905
68K
3923
F902
I903
+5V_SW
4K7
RES
3915
PWR5V_1
4901
3900
10K
3907
4K7
10K
7903 MMBT3904
2
3904
6910
CDS2C05HDMI2
5.6V
1
3906
27K
RES
F901
7905
RES
MMBT3904
F907
HDMI_PLUGPWR2
RES
F906
3911
2K2
4K7
3902
5.6V
CDS2C05HDMI2
6903
12
4903
RES
4902
21
45
IP4281CZ10
6916
RES
3
8
67 910
9
20 21 22 23
17 18 19
2
3
4 5 6 7
8
1
10 11 12 13 14 15 16
1901
10029449-001RLF
HDMI_PLUGPWR1
21
45
RES
3910
100R
IP4281CZ10
6914
RES
3
8
67 910
10
21
45
IP4281CZ10
RES
3
8
67 9
6915
I900
I901
3914
4K7
RES
6 7
8
9
20 21 22 23
14 15 16 17 18 19
2
3
4 5
10029449-001RLF
1
10 11 12 13
6
5
84
7
1902
7901
M24C02-WMN6
1 2
3
(256 × 8)
Φ
EEPROM
HDMI_PLUGPWR1
10K
3903
4K7
3921
RES
I906
F913
2900
100n
12
3
MMBT3904
RES
BAT54C
6900
7907
100n
2901
5.6V
12
RES
CDS2C05HDMI2
6909
6902
BAT54 COL
4K7
3908
RES
12
CDS2C05HDMI2
6905
5.6V
2
3
6
5
84
7
+5V_SW
M24C02-WMN6
7900
EEPROM
Φ
(256 × 8)
1
4900
F911
I902
+3V3STBY
3905
4K7
3919
12
1K0
+3V3STBY
RES
6917
CDS2C05HDMI2
5.6V
BSH111
7908
4904
RES
2K2
3901
RES
3918
10K
MMBT3904
7902
PWR5V_2
3111
100K
RES
HDMI_CEC_A
HDMI_CEC_A
M_RX1_2B
M_RX1_1
EDID_WC
EDID_WC
HDMI_CEC
M_RX1_0 M_RX1_0B
M_RX2_2 M_RX2_2B M_RX2_1
M_RX2_1B
M_RX2_1B
M_RX2_2
M_RX2_0 M_RX2_0B
M_RX2_C
M_RX2_CB
M_RX2_CM_RX2_CB
M_RX2_0 M_RX2_0B
M_RX1_1B
M_RX1_2B
M_RX1_2
M_RX1_CB
M_RX1_C
M_RX1_2B
M_RX1_2
M_RX1_1B
M_RX1_1
M_RX1_0B
M_RX1_0
M_RX1_2
M_RX1_1
M_RX1_1B
M_RX1_0 M_RX1_0B M_RX1_C
M_RX1_CB
M_RX1_C
SIDE_HDMI_SCL1
HDMI_HPD2
M_RX2_CB
M_RX2_C
M_RX2_2B
M_RX2_2
M_RX2_1B
M_RX2_1
M_RX2_0B
M_RX2_0
SIDE_HDMI_HPD1
M_RX2_1
M_RX2_2B
DDC_RESET
HDMI_SCL2
HDMI_SDA2
SIDE_HDMI_SDA1
PX1D+
PX1C-
PX1C+
PX1B-
PX1B+
PX2A-
PX2A+
PX1CLK-
PX1CLK+
PX1E-
PX1E+
PX1D-
PX2D-
PX2D+
PX2C-
PX2C+
PX2B-
PX2B+
PX1A-
PX1A+
PX2CLK-
PX2CLK+
PX2E-
PX2E+
SIDE_HDMI_SCL1
SIDE_HDMI_SDA1
HDMI_SCL2
HDMI_SDA2
PWR5V_1
PWR5V_2
M_RX1_CB
DDC_RESET
M_RX2_2
M_RX2_2B
M_RX2_CB
M_RX2_C
M_RX2_0B
M_RX2_0
M_RX2_1B
M_RX2_1
HDMI_CEC_A
HDMI_HPD2
M_RX1_2
M_RX1_2B
M_RX1_CB
M_RX1_C
M_RX1_0B
M_RX1_0
M_RX1_1B
M_RX1_1
SIDE_HDMI_HPD1
Circuit Diagrams and PWB Layouts
EN 51LC10.1L LA 10.
2010-Apr-06
Page 52
Circuit Diagrams and PWB Layouts
18980_509_100329.eps
100329
Analog I/O - Headphone
B06A B06A
2010-01-22
1
3140 123 6483
BR-M-50
PCB SB SSB DIGITIAL
VIA
GND_HS
VO
IN-
VDD
1
SHUTDOWN
BYPASS
2
GND
2
1
7A00 F7 FA00 C6 FA01 C6 FA02 C6 FA03 C6 FA04 C7 FA06 F3 FA07 F3 FA08 F10 FA09 G10 IA00 F8 IA01 F8 IA02 F5 IA03 F5 IA04 F5 IA05 F4 IA08 E7 IA09 E7 IA10 G6
LEFT
HEADPHONE
3A16 F5 3A17 G4
4A00 C5 4A01 D5 4A02 F3 4A03 G3 6A00 C5 6A01 D5
3A10 E7 3A11 F9 3A12 F9 3A13 G9 3A14 G9 3A15 F4
E
F
G
RESERVED
RIGHT
2A10 F7 2A11 G6
3A00 C6 3A01 B4 3A02 B5 3A03 C5 3A04 D5 3A09 E7
678 91011
A
B
C
D
E
F
G
A
B
C
D
567
B04C
B06B
B03
8 91011
123 45
2A07 F4 2A08 F4 2A09 G8
123 4
1A01 C7 1A02 C6 1A03 D5 2A00 B5 2A01 C5 2A02 D4 2A04 E7 2A05 E7 2A06 F8
RES
2A02
1n0
1R0
3A04
22K
3A09
RES
2A04
47p
RES
RES
RES3A17
10K
RES
1n0
2A00
IA03
IA05
FA06
RES
3A16
10K
6A00
PESD5V0S1BA
3A12
33R
RES
+3V3_SW
RES
FA02
+3V3_SW
IA02
3A02
22K
IA01
RES
5
8
10 11
1
7
3
4
9
2
6
3A00
RES
7A00
TPA6111A2DGN
AMPLIFIER
Φ
2K0
RES
IA04
RES
33R
3A13
RES
2A01
1n0
3A03
1R0
2A08
1u0
RES
RES
1R0
1
2
3
4
5
RES
3A01
RES
1A01
LGM1019-0100F
FA09
4A02
RES
4A03
FA03
RES
10K
RES
3A15
RES
PESD5V0S1BA
6A01
4A01
FA01
2A11
1u0
RES
FA04
RES
4A00
FA07
RES
3A10
RES
22K
RES
1u0
2A07
RES
47p
2A05
IA09
IA10
IA08
1A02
RES
1A03
RES
33R
RES
3A11
FA08
2A06
RES
2A10
1u0
RES
4V 100u
2A09
100u4V
RES
IA00
RES
33R
3A14
FA00
HP_ROUT
HP_LOUT
PBS_HPL
PBS_HPR
HPOUTL
HPOUTR
HP_LOUT
HP_ROUT
RC2 RC1
HP_DET
RESET_AUDIO

SSB: Analog I/O - Headphone

EN 52LC10.1L LA 10.
2010-Apr-06
Page 53

SSB: Analog I/O - Audio

18980_510_100329.eps
100329
Analog I/O - Audio
B06B B06B
2010-01-22
1
3140 123 6483
BR-M-50
PCB SB SSB DIGITIAL
PR
0P 1P
PB
0P 1P
Y
COM
SOY
SY
SC
CVBS
VDAC
MPX
AIN_AADC
AOSDATA
AR
0 1 2
3
AL
AOMCLK
0 1 2
3
4
ASPDIF
ALIN
0 1 2
3
AVICM
HSYNC VSYNC
SOG RP
GP BP
COM
0P 1P
FS_VDAC
0 1
0 1 0 1 0 1
0N 0P 1P 2P 3P
OUT1 OUT2
AF
P N
0_L
0_R
1_L
1_R
2_L
2_R
3_L
3_R
4_L
4_R
5_L
5_R
6_L
6_R
VMID_AADC
AOBCK
AOLRCK
IB20 D7 IB21 D8 IB22 D7 IB23 B2 IB24 B2
IB00 B11 IB01 B11 IB02 B10 IB03 B10 IB04 A8
B06C
B02A
B06C
IB05 A8 IB06 A8 IB07 B8 IB08 B11 IB09 B11 IB10 A7 IB12 A7 IB13 B7 IB14 C7 IB15 C7 IB16 C7 IB17 C7 IB18 D7 IB19 D8
3B50 F3 3B51 F5 3B52 H3 3B53 H5
6B00 B12 6B01 C12 7700-2 A6 7B01-1 F3 7B01-2 G3 FB00 B12 FB01 C12 FB02 A7 FB03 C9 FB04 C12 FB06 B13 FB07 D13 FB08 C2
3B29 A8 3B30 A8 3B31 B10 3B32 B11 3B33 B11 3B34 B10 3B35 C7 3B36 C7 3B37 C8 3B38 C7 3B39 D7 3B40 F3 3B41 F2 3B42 G4 3B43 G2 3B44 G2 3B45 H2
3B46 H3 3B47 D5 3B48 E9 3B49 E10
3B08 C3 3B09 B3 3B11 B3 3B12 C3 3B14 D3 3B15 C11 3B16 D11 3B27 B8 3B28 A8
2B51 F2 2B52 F2 2B53 G4 2B54 G2 2B55 H2 2B56 H2 2B57 H3 2B58 F4 2B59 H4
3110 D5 3B00 C1 3B01 C1 3B02 C1 3B03 B1 3B05 B1 3B06 C3 3B07 B3
2B33 A9 2B34 B11 2B35 B11 2B36 B12 2B37 B11 2B38 C11 2B39 C12 2B40 C9 2B41 C8 2B42 C7 2B43 E8 2B44 E8 2B50 F3
2B07 B4 2B08 C4 2B09 B4 2B11 B4 2B12 C4
AUDIO IN
2B14 D4 2B15 C3 2B16 A8 2B17 A8 2B19 D12 2B20 D11 2B24 D7 2B25 D7 2B30 B9 2B31 A9 2B32 A9
8 9 101112
SPDIF
1B02 B13 1B03 B12 1B04 C12 1B05 D12 2B00 C2 2B01 C2 2B02 C2 2B03 B2 2B05 B2 2B06 C4
123 45
678 9 10111213
123 4567
B03
B03
DEB
13
A
B
C
D
E
F
G
H
A
B
C
D
E
F
G
H
1B01 C13
IB29 B2 IB30 B2 IB31 B2 IB32 C2 IB33 C2 IB34 C2 IB35 C2 IB36 C2 IB37 C2 IB38 B4 IB39 B4 IB40 B4 IB41 B4 IB42 B4 IB43 B4 IB44 C4 IB45 C4 IB46 C4 IB47 C4 IB48 F2 IB49 F3 IB50 G3 IB51 G3 IB52 H3 IB53 H2 IB59 C2 IB61 C4 IB62 C4
1
2
3
4
5
7
8
IB63 D4 IB64 A7 IB65 A7 IB66 A2 IB67 A2
IB25 B2 IB26 B2 IB27 B2 IB28 B2
1B02
MSJ-035-10A B AG PPO
3B09 68R
FB00
2B01
3B16
10n
100R
33p
2B19
3110
75R
220p
2B50
DEB
FB02
IB61
IB67
IB66
FB08
IB64 IB65
100R 3B14
IB04
10u
2B59
IB40
2B58
10u
47K
3B51
5K1
3B52
3B07 68R 2B07 10n
1n0
2B35
RES
IB29IB28
6B01
PESD5V0S1BA
RES
IB43
3B41
10K
1u0
2B53
1B05
FB04
47n 2B12
3B39
4K7
RES
IB31
2B44
100n
3B53
47K
47K
3B49
3B48
47K
3B50
5K1
10n2B02
IB62
68R3B01
68R
3B03
3B05
68R
47K
3B44
2B37
IB03
10u
2B42
100n
2B32
10u
2B55
10u
FB03
10n2B11
3B11
68R
IB32
IB08
IB41
10u2B24
2B25 10u
3B47
560R
IB02
3B34
30K
1u0 2B15
RES
3B42
2B38
1n0
30R
1B04
2B39
1n0
RES
IB30
10n2B16
1u0
2B41
IB18
+12VS
IB63
IB53
IB50
2B1447n
IB23
IB21
3B12
100R
IB00
30K
IB01
3B29
IB19
3B33
1R0
3B32
1R0
PESD5V0S1BA
6B00
RES
IB48
IB13
IB14
IB10
2B30
IB51
10u
2B05 10n
IB20
IB22
3B02
100R
IB36IB37
IB09
3B354K7
2B17 10n
10K
3B45
10u
2B54
IB17
+12VS
IB16
2B31
FB07
10u
10u
2B51
47K
3B43
3B00 1R0
2B03 10n
3B31
30K
10n2B09
2B06
1n5
IB45
IB46
IB44
2B34
10u
3B15 240R
2B56
820p
10n2B08
10u2B33
2B43
1u0
IB12
+3V3_SW
2B57
220p
IB39IB38
3B37
4K7
4K73B36
30K3B30
3B08 100R
IB05
IB15
FB06
FB01
IB24
IB25
3B38
IB27
4K7
AR28 AU26
IB26
AT33 AU34
AP23
AU28 AP25 AP33 AR34
AP31 AT31
AA30
AU22
AM29
AU24
AR22
AN36
AN34
AP29 AT27
AU30 AP27
AT25
AF35
AT23
AR24
AT29 AR26
AR36 AT37 AU36 AP35 AT35
M35
L36 P35 P37 K31 N32
AE36
V33 U34 U36
K33
AA34
Y35
AA36
Y37
AF37
U32 V35 V37
L32
L34
M37
AD33 AC34 AB31 AC32 AD35 AB35 AC36 AB37 AA32 AB33
7700-2
MT5363BHMG
AUDIO-VIDEO
AM33
+3V3_SW
IB34
8
4
1B03
LM833
7B01-2
5
6
7
LM833 7B01-1
3
2
1
8 4
1R03B06
2
1
22K
3B46
1B01
CON_JACK
YKB11-0946V
1n52B00
RES
1n0
2B36
IB59
100n
2B40
IB47
IB49
22K
820p
2B52
3B40
2B20
33p
IB52
IB35
IB42
IB33
3B28
30K
3B27
IB07
30K
IB06
CVBS_RF
PREAMPL
PREAMPR
AOUTL
AOUTR
Y0N
PR0P
SOY0
Y0P
PB0P
HPOUTL
HPOUTR
SIF_OUT
SIF_OUT_GND
SY0P
AIN1_R-AV2
AIN0_L-AV1
HSYNC
AIN1_R
AIN1_L
AIN0_R
AIN0_L
SPB0P
SY0N
ASPDIF_OUT
GND_CVBS
SPB1P
SY1P
SPR1P
AIN1_L-AV2
AIN0_R-AV1
CVBS_AV3
PREAMPR
PREAMPL
SOY0-AV1
SPR0P
BP
GN
GP
RP
SOG
VSYNC
SOY1-AV2
SY1N
DVI_AUR_IN
DVI_AUL_IN
SAV_L_IN SAV_R_IN
Circuit Diagrams and PWB Layouts
EN 53LC10.1L LA 10.
2010-Apr-06
Page 54

SSB: Analog I/O - Video

18980_511_100329.eps
100329
Analog I/O - Video
B06C B06C
2010-01-22
1
3140 123 6483
BR-M-50
PCB SB SSB DIGITIAL
IC11 C9 IC13 E9 IC14 E9
AV3
B06B
B06B
LEFT
FC14 D11 FC15 B11 IC01 A4 IC02 C4 IC03 C4 IC04 G4 IC05 H4 IC06 H4 IC07 I4 IC08 I4 IC09 A10 IC10 B10
RIGHT
(WHITE)
(RED)
FC01 I2 FC02 H2 FC03 G2 FC04 D6 FC05 D6 FC06 D6 FC07 D6 FC08 C6 FC09 C6 FC10 C12 FC11 C12 FC12 D11 FC13 D11
CVBS
5C01 E5 5C02 E5 5C03 C10 5C04 E10 5C05 E10 6C00 A5 6C01 C5 6C02 D5 6C03 D5 6C04 E5 6C05 G3 6C06 H3 6C07 I3 6C08 D11 6C09 D11 6C10 E11 6C19 A11 6C20 C11 FC00 I2
3C10 H4 3C11 I4 3C12 A10 3C13 B10 3C14 D10 3C16 D10 3C17 E10
3C18 E9 3C19 I4 3C20 C4 3C21 C10 3C22 E4 3C23 E10 3C24 E10 3C25 E4
5C00 C5
2C16 D9 2C17 D10 2C18 C10 2C19 C10 2C20 A10 2C21 A10
3C00 A4 3C01 C4 3C02 D4 3C04 D4 3C05 E4 3C06 E4 3C07 G4 3C08 G3 3C09 H4
AV2
(YELLOW)
1C19 E5 2C00 A4 2C01 A5 2C02 C4 2C03 C5 2C04 D4 2C05 D4 2C06 E4 2C07 G4 2C08 G3 2C09 H4 2C10 H4 2C11 H3 2C12 I3 2C13 I4 2C14 I4 2C15 E9
AV1
1C01 C6 1C02 C12 1C03-1 I1 1C03-2 H1 1C03-3 G1 1C05 G2 1C06 H2 1C07 I2 1C08 E11 1C09 D11 1C10 D11 1C14 A11 1C15 C11 1C16 C5 1C17 D5 1C18 D5
123 45678 9101112
123 45678 9101112
A
B
C
D
E
F
G
H
I
A
B
C
D
E
F
G
H
I
1C00 A5
3C08
75R
18R
3C23
56R
3C04
2C04
15p
FC10
1C09
FC09
1C08
IC02
0001
1C00
RES
2C02
1n0 1n0
2C00
RES
RES
1n0
2C11
1C18
RES
PESD5V0S1BA
6C02
1C07
PESD5V0S1BA
6C00
RES
RES
6C01
FC05
PESD5V0S1BA
5C04
60R
1C15
3C18
1R0
2C18
1n0
RES
30K
3C19
56R
3C17
FC11
3C21
18R
3C22
18R
15p
2C05
1C17
60R
5C03
3C11
1R0
FC07
FC14
FC08
11 12
2
3
4
5
6
7
8
9
MSP-636H1-01
1C02
1
10
IC01
1R0
IC14
3C13
3C12
1R0
1C16
56R
3C14
IC10
PESD5V0S1BA
6C09
IC09
5
6
7
8
9
RES
1
10 11 12
2
3
4
1C01
MSP-636V1-01
2C20
1n0
RES
3C02
56R
2C16
15p
15p
5C05
60R
2C15
FC03
5C00
60R
PESD5V0S1BA
6C03
FC12
RES
FC13
3C24
18R
3C25
18R
FC04
FC01
FC02
FC15
IC13
2C03
1n0
RES
2C01
1n0
6
RES
MSP-305H-BBB-432-03 NI
RED
1C03-1
5
MSP-305H-BBB-432-03 NI
YELLOW
1C03-3
1
2
IC08IC07
IC04
1R0
3C00
5C02
60R
RES
6C06
PESD5V0S1BA
1n0
2C10
RES
10u
2C14
2C09
10u
PESD5V0S1BA
6C05
RES
RES
2C12
1n0
FC06
FC00
MSP-305H-BBB-432-03 NI
WHITE
1C03-2
3
4
RES
6C10
RES
1n0
2C21
1C14
PESD5V0S1BA
1R0
3C09
15p
2C08
RES
6C19
PESD5V0S1BA
RES
RES
PESD5V0S1BA
6C04
IC06
3C10
30K
3C16
56R
6C20RES
PESD5V0S1BA
3C07
1R0
IC11IC03
2C06
15p
1C19
2C13
1n0
2C07
47p
RES
1C10
3C01
1R0
1C05
1C06
RES
1n0
2C19
60R
5C01
6C08
RES
PESD5V0S1BA
18R
3C20
3C06
1R0
56R
RES
PESD5V0S1BA
6C07
3C05
15p
IC05
2C17
AIN0_L-AV1
SPB0P
SY0N
CVBS_AV3
GND_CVBS
SC1_CVBS_OUT
SPB1P
SY1P
SPR1P
AIN1_L-AV2
AIN0_R-AV1
SY0P
AIN1_R-AV2
PR1P_SC2
PB1P_SC2
SY1P_SC2 SC1_G
SC1_B
SPR0P
SOY1-AV2
SY1N
SAV_L_IN
SAV_R_IN
SOY0-AV1
Circuit Diagrams and PWB Layouts
EN 54LC10.1L LA 10.
2010-Apr-06
Page 55

SSB: USB

18980_512_100329.eps
100329
USB
B06D B06D
2010-01-22
1
3140 123 6483
BR-M-50
PCB SB SSB DIGITIAL
1
2
IN
1
23OUT
USB
FD04 B5 FD05 C5 FD06 C5 ID04 C4
D
B04C
2D16 D6
3D09 D5 3D10 D6
5D00 C4 6D00 C3 6D01 C4 6D02 C3 7D00 B5 FD00 C2 FD01 C3 FD02 C3 FD03 C3
2 3 45678
A
B
C
D
A
B
C
2D15 D5
123 45678
1
1D00 C3 1D01 C2 1D02 C3 1D03 C3 2D11 C4 2D12 C5 2D14 C6
6D02
NUP1301ML3
2
3
OC_
5
6
7
8
TPS2041BD
7D00
4
EN_
GND
1
FD03
RES
FD02
2D15
4p7
FD00
30R
5D00
1D03
1D00
1D02
BZX384-C6V8
6D00
FD05
FD04
56
1D01
1 2
3
4
USB-01-PBT-B-30-CU2
15K
RES
3D10
RES
4p7
2D16
2D11
10u
FD01
100u
16V
2D14
100n
2D12
15K
FD06
RES
3D09
6D01
NUP1301ML3
+5V_SW
ID04
USB_DP
USB_DP
USB_DM
USB_DM
USB_OCP
5V
USB_PWR_EN
Circuit Diagrams and PWB Layouts
EN 55LC10.1L LA 10.
2010-Apr-06
Page 56

SSB: VGA

18980_513_100329.eps
100329
VGA
B06E B06E
2010-01-22
1
3140 123 6483
BR-M-50
PCB SB SSB DIGITIAL
SCL
ADR
0 1 2SDA
WC
IE01 C3 IE02 C3 IE03 D3 IE04 D3 IE05 D3 IE06 E8
6E04 G5 6E05 E5 6E06 A10 7E00 E10 7E01 B9 FE00 B8 FE01 C7 FE02 D7 FE03 E7 FE04 F7 FE05 F7 FE06 F7 FE07 F8 FE08 E10 FE09 E10 FE10 E10 FE11 D10 FE12 E11 IE00 B9
3E27 B7 4E02 E9 4E03 E9 4E04 D10 5E00 C6 5E01 C6 5E02 D6 5E03 E4 5E04 F5 5E05 F5 6E00 C6 6E01 D6 6E02 E6 6E03 F5
3E15 D5 3E16 C5 3E17 F5 3E18 G5 3E19 E9 3E20 E9 3E21 E9 3E22 E9 3E23 E9 3E24 D11 3E25 B8 3E26 B10
2E08 D5 2E09 E5 2E10 E5 2E11 E6 2E12 F5
B04C
B06B
2E13 G5 2E14 E9 2E15 E9 2E16 D11 3E00 C3 3E02 C3 3E03 D3 3E04 D3 3E05 D3 3E10 D5 3E13 E5 3E14 E5
A
B
C
D
2E04 D3 2E05 D3 2E07 C5
A
B
C
D
E
F
G
1234567891011
1234567891011
E
F
G
1E00 C7 1E01 E8 1E02 E7 1E03 F6 1E04 G6 1E05 D7 2E00 C3 2E02 C3 2E03 D3
5E05
30R
BAS316
6E06
FE06
FE05
RES 3E20
6K2
1%
5p6
2E08
60R
5E03
3E23
33R
1%
RES 3E19
6K2
100R
3E04
330p
2E14
2E15
330p
RES
RES
PESD5V0S1BA
6E03
2K2
3E17
6E04
RES
PESD5V0S1BA
2E07
5p6
DC_5V
5p6
2E13
5 6 7 8 9
16 17
10 11 12 13 14 15
2 3 4
1E01
MDS-15P-V-05-B-8.5-U4-ZN
1
5p6
2E12
1E03
4E04
RES
PESD5V0S1BA
6E02
FE07
7E01 BC847BW
2E09
5p6
1E02
0001
2E04
10n
0001
1E05
1E04
3E05
68R
10n
2E02
2E05
10n
2E03
1n5
3E02
68R
1E00
4E03
FE02
1R0
3E15
3E03
75R
3E10
1R0
2K2
RES
3E18
DC_5V
3E14
75R
1n0
2E11
FE09
FE03
FE04
DC_5V
FE00
1%
RES
3E24
6K2
5E01
60R
IE01
5E02
60R
4E02
3E22
10K
10K
3E21
2E16
100n
6E05
BAS316
6
5
8
4
7
FE01
(256x8)
Φ
EEPROM
7E00 M24C02-WMN6
1 2 3
DC_5V
RES
68K
3E27
2E10
100n
3E13
150R
30R
5E04
RES
PESD5V0S1BA
6E01
FE08
2E00
3E00
10n
75R
68R
3E16
IE00
IE06
FE12
FE11
IE04
IE05
IE03
IE02
FE10
PESD5V0S1BA
6E00
+5V_SW
RES
10K
3E26
3E25
10K
5E00
60R
VGA_R
VGA_G
EDID_WC
SOG
RP
GN
VSYNC
VSYNC
SDA_VGA
SCL_VGA
H_SYNC
HSYNC
BP
VGA_B
VGA_Bp
GP
VGA_Gp
VGA_Rp
VGA_Gn
Circuit Diagrams and PWB Layouts
EN 56LC10.1L LA 10.
2010-Apr-06
Page 57

SSB: Hospitality

18980_514_100329.eps
100329
Hospitality
B07 B07
2010-01-22
1
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BR-M-50
PCB SB SSB DIGITIAL
FF12 B5
FF03 B2 FF04 B1
FF05 C2 FF06 C2
FF07 C2 FF08 C2
FF09 D2 FF10 D2
FF11 B5
B04C
1F02 C1 2F00 B6
2F01 B6
3F00 B2 3F01 B2
3F02 C2 3F03 C2
5F00 B2 5F01 B2
FF00 B2 FF01 B2
FF02 B2
123 4567
1
DMMC1
DMMC2
DMMC3
1F01 B5
A
B
C
D
A
B
C
D
1F00 B1
B06A
8
910
FF13 B5
2 3 4567
502382-0870
1F02
1 2
3
4 5 6 7
2F00
1n0
1n0
2F01
FF11
+5V_SW
+3V3STBY
FF01 FF02
FF05
1 2
3
4
5
FF04 502382-0370
1F01
FF03
30R
5F00
FF09 FF10
FF08
FF07
FF06
3F03 22R
3F02 22R
FF00
5F01
30R
3F01 100R
100R3F00
FF13
3
4 5
67
FF12
1F00
502382-0570
1 2
+12VS
SCL-LCD
SDA-LCD
PBS_HPL
PBS_HPR
PBS_SPI_DI
PBS_SPI_CLK
SDA-MAIN1
SCL-MAIN1
RC1 RC2
SDA_CLOCK SCL_CLOCK
Circuit Diagrams and PWB Layouts
EN 57LC10.1L LA 10.
2010-Apr-06
Page 58

SSB: TCON Control

18980_515_100329.eps
100329
TCON Control
B08A B08A
2010-01-22
1
3140 123 6483
BR-M-50
PCB SB SSB DIGITIAL
1
1
C1QQ
R
S
1D
C1QQ
R
S
1D
RXE RXO
RXORXE
4N
CLKP CLKN
0P 0N 1P
0P 0N 1P 1N 2P 2N
3P 3N
4P 4N
CLKP CLKN
1N 2P 2N
3P 3N
4P
CS
LLV
LLV
STH
B1 B2
STH
0P 0N 1P 1N 2P 2N
3P 3N
4P 4N 5P 5N 6P 6N 7P 7N
CKP CKN
RLV
RLV
1 2
3
4 5 6 7
8
9 10 11 12
RESPI
F1 F2
POL
TP
CPV
OE
STVU STVD
SLOPE
GP01 GP02
L|R_ U|D_
SELLVOS
0P 0N 1P 1N 2P 2N
3P 3N
4P 4N 5P 5N 6P 6N 7P 7N
CKP CKN
DQ
A
BA
0 1 2
3
4 5 6 7
8
9 10 11 12 13 14 15
LDQS
UDQS
CAS WE
CK
CKE
ODT
0 1
RESIMP
0 1 2
3
4 5 6 7
8
9 10 11 12
CS RAS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD18PLL
VSS
VDD18
VDD18
VDD18
VDD18
VDD33LVML
VDD33IO
VDD18
VDD18
VDD18
VDD18
NC
DB
EE
OSC
OUT
IN
0 1 2
3
TESTSE
RST
SCL SDA
ATTN
RTC50_60
SCL SDA
TESTAGN
TESTMOD
12
11
10
9
8
7
6
5
4
3
0 1 2
3
4 5 6 7
8
9 10 11 12
CK
VDDL
VREF
VSSDL
14
VDDQ
QSSVSSV
BA
A
LDQS
UDQS
NC
DQ
CKE WE
ODT
RAS
1
CS
CAS
0
0 1 2
VDD
LDM
UDM
15
13
7H01-5 A3 7H02-1 C8 7H02-2 D8 7H03 D9 7H04 D10 7H05 C11 FH00 G4 FH01 H4 FH02 H4 FH03 H4 FH04 I4 FH05 H5 FH06 H6 FH34 I16 FH35 H8
3H19 J16 3H20 I16 3H21 C7 3H22 C7 3H23 E8 3H25 H4 3H26 H4 3H27 H6 3H28 H6
4H04 D5 4H05 D11 5H00 D2 5H01 E2 5H02 F2 5H03 G2 5H04 E13 5H05 F13 5H06 F14 7H00 G13 7H01-1 H4 7H01-2 J6 7H01-3 F9 7H01-4 B14
2H48 J15 2H50 G13 2H51 G14 2H52 F13 2H53 F13 2H54 D10
3H00 E13 3H01 C6 3H02 C6 3H03 D5 3H04 D5 3H05 G8 3H06 H8 3H07 J4 3H08 J4 3H09 J5 3H10 J5 3H11 J5 3H12 J5 3H13 J8 3H14 J8 3H15 J8 3H16 J8 3H17 J9 3H18 J9
2H30 A11 2H31 A12 2H32 A12 2H33 A13 2H34 A13 2H35 A13 2H36 A13 2H37 A13 2H38 A14 2H39 A14 2H40 C5 2H41 C5 2H42 D5 2H43 E2 2H44 E2 2H45 F2 2H46 F2 2H47 J15
B
C
D
E
F
G
H
I
J
K
A
B
C
D
E
F
2H28 A11 2H29 A11
678 910111213 14 15 16
123 45678 910111213 14 15 16
A
K
1H00 B5 2H01 A5 2H02 A5 2H03 A5 2H04 A5 2H05 A6 2H06 A6 2H07 A6 2H08 A6 2H09 A6 2H10 A7 2H13 A7 2H25 A10 2H26 A10 2H27 A10
123 45
3H14
100R
G
H
I
J
3H15
100R
7H02-1
74LVC2G04
1
25
6
DDR2VDD
100n
2H48
3H19
100R
100R
3H20
2H52
100n
VCC1V8
5H04
60R
DDR2VDD
3H10
100R
VCC1V8DDR2VDD
FH34
VCC_3V3
VDD1V8PLL
100n
2H02
VDD3V3LVRS
VCC1V8
VCC_3V3
2H44
10u
5H01
60R
10u
2H45
1M0
3H02
2
1
4
5
36
7
8
VDD1V8
5
4
7H03
74LVC1G74DC
74LVC1G86GW
7H05
2
1
3
2
1
4
5
36
7
8
5
4
74LVC1G74DC
7H04
7H02-2
74LVC2G04
3
2
FH35
VCC_3V3
FH04
2H39
100n
100n
2H36
100n
2H37
2H35
100n
2H10
100n
100n
2H27
D11
P6 P8 P9
D9
P10 P11 P12 P13 P14
U4
D10
M13
N4
D8
N5 N8
N9 N12 N13 N14
P5
K11
L4
D7
L6
L7 L10 L11
M5 M8 M9
M12
J5
J8
D6
J9 J12 J13 J14 J16
K6
K7 K10
G11
D5
H5 H8
H9 H12 H13
J1 J2 J4
E13
C4
E14
F6
F7 F10 F11
G4 G6 G7
G10
R13
C3
D12 D13 D14
E2
E4
E5
E8
E9 E12
C6 R6 R9 R12
C8 C11 C13 E15 J15 N15
N10 N11 P15 R5
E6
R8 R11
E7 E10 E11 F5
L9 L12 L13 M6
E3
M7 M10 M11 N3 N6 N7
J11 K5 K8
D15
K9 K12 K13 L3 L5 L8
G12 G13 H6
C9
H7 H10 H11 J3 J6 J7 J10
C10 C12 G3
C5
F8 F9 F12 F13 G5 G8 G9
7H01-5
VPP1501BFG
POWER
C7
100R
G2 G1
M4
M3
E1
C2 C1
M2
3H12
F4 D1 D4
K3
K2
K1
K4 H1 H4 D3 D2
N1
L2
M1
L1
N2
H3 H2
F3
F2
F1U3
P3 T1 R4 T2 R3 U1 T4 U2
P1 P2
DRAM
P4 R2
R1 T3
U15 U14
U12
T12
U13
U10
7H01-4
VPP1501BFG
K16
L15
L14
L17
L16
M15
M14
T17
T16
H15 H14
F17
F16
G15
G14
G17
G16
H17
H16
K15
K14
K17
D17
D16
E17
E16
F15
F14
T10
U11
T13
J17
A14
A17
A16
B15
B14
B17
B16
C15
C14
C17
C16
M17 N16 N17 P16 P17 R14 R15 R16
U16 U17
A15
T11
M16
R17 T14 T15
B11
A9
B9
A8
B8
A10
B10
7H01-3
VPP1501BFG
LCD
A3
B3
A2
B2
A4
B4
A13
B13
A12
B12
A11
A7
B7
A6
B6
A5
B5
LVDS
VPP1501BFG
7H01-2
1K0
3H00
RES
VDD3V3IO
2H47
100n
100n
2H13
5H03
60R
100n
2H26
2H25
100n
10p
560R
3H01
2H41
4
1 3
10p
2H40
1H00
DSX321G
27M
2
FH05
FH06
100n
2H42
FH00
VGH_35V
4H05
VCC_3V3
2H54
1u0
3H23
100R
33R
RES
3H21
3H22
2K2
2H05
100n
2H08
100n
10u
2H43
FH03
60R
5H00
VDD1V8PLL
3H05
2K4
10u
2H50
60R
5H05
2H31
100n
100n
2H30
2H01
100n
100n
2H03
RES
VDD3V3LVRS
1R0
3H25
150K
3H03
3H17
100R
16K
3H04
RES
3H11
1K0
3H06
100R
VDD3V3IO
100R
3H07
FH01
3H26
RES
FH02
1R0
4H04
VDD1V8
2H38
100n
100n
2H32
2H34
100n
RES
3H27
RES
1R0 3H28
1R0
2H46
10u
100n
2H28
2H29
100n
100R
3H16
100n
2H04
100n
2H06
T9
U9
R10
U5 T5 U6 T6
U7
T7
P7 R7
T8 U8
A1
B1
3H08
7H01-1
VPP1501BFG
MISC
100R
3H09
100R
60R
5H02
100n
2H07
2H09
100n
100R
3H18
VCC1V8
3H13
100R
2H51
10u
5H06
60R
100n
2H53
RES
F8
H2
K3
N1
P9J7A7
H8
B2
B8
D2
D8
E7
F2
C3
C7
C9
E9
G1
G3
G7
J2
A3
E3
J3
A8
A1
E1J9M9
R1
J1
A9
G9
C1
A2
E2
L1 R3 R7 R8
K9
K7
B3
B7
H7 H3 H1 H9
F1
F9 C8 C2
F3
F7 E8
K2
K8
L8
G8 G2
D7 D3 D1 D9
B1
B9
N8 N3 N7 P2 P8 P3
L2 L3
L7
J8
Φ
M8 M3
M2 P7 R2
M7 N2
DDR2VDD
7H00
H5PS5162FFR-S6C
SDRAM
2H33
100n
GCK
RESET
GSP2
GSP1
REV
U_D
U_D_INV
RESET
OSCOUT
OSCIN
TDQ13 TDQ14 TDQ15
TDQ2 TDQ3 TDQ4 TDQ5 TDQ6 TDQ7 TDQ8 TDQ9
TA11
TA2 TA3 TA4 TA5 TA6 TA7 TA8 TA9
TA12
TDQ0 TDQ1
TDQ10 TDQ11 TDQ12
TBA0 TBA1
TODT
TCS# TRAS#
TLDQS TLDQS#
TUDQS TUDQS#
TCK
TA0 TA1
TA10
TCK#
TCAS#
TCKE TWE#REV
SCL-TCON SDA-TCON
SCL-TCON SDA-TCON
PX2D-
PX2C-
PX2B+ PX2B-
PX2A-
PX1C-
PX1B+ PX1B-
PX1A+ PX1A-
PX1CLK+
PX1CLK-PX2CLK-
PX1E+ PX1E-
PX1D+ PX1D-
PX1C+
TBA1
TCAS#
TCK
TCKE
TCK#
TCS#
TDQ0 TDQ1
TDQ10 TDQ11 TDQ12 TDQ13 TDQ14 TDQ15
TDQ2 TDQ3 TDQ4 TDQ5 TDQ6 TDQ7 TDQ8 TDQ9
TLDQS
TLDQS#
TODT
TRAS#
TUDQS
TUDQS#
TWE#
GSLOP
RDIO1 RDIO2
LDIO1 LDIO2
GSP1
GSP2
LS
U_D
TA0 TA1
TA10 TA11 TA12
TA2 TA3 TA4 TA5 TA6 TA7 TA8 TA9
TBA0
LLV2-
LLV2+
LLV1-
LLV1+
LLV0-
LLV0+
LLV7-
LLV7+
LCK-
LCK+
SELLVDS
RCK-
RCK+
R_L
GOE
LLV6-
LLV6+
LLV5-
LLV5+
LLV4-
LLV4+
LLV3-
LLV3+
RLV4+
RLV3-
RLV3+
RLV2-
RLV2+
RLV1-
RLV1+
RLV0-
RLV0+
RLV7-
RLV7+
ROM_SDA
OSCIN
OSCOUT
RESET
50Hz_60Hz
GCK
ASIC_CS1
ASIC_CS11
ASIC_CS3
ASIC_CS5
ASIC_CS7
ASIC_CS9
RLV6-
RLV6+
RLV5-
RLV5+
RLV4-
PX2E+ PX2E-
PX2D+
PX2C+
PX2A+
PX2CLK+
ROM_SCL
Circuit Diagrams and PWB Layouts
EN 58LC10.1L LA 10.
2010-Apr-06
Page 59

SSB: TCON DC/DC

18980_516_100329.eps
100329
TCON DC/DC
B08B B08B
2010-01-22
1
3140 123 6483
BR-M-50
PCB SB SSB DIGITIAL
DRN COM
VREF
FBN
NOUT
CB
1 2
FBL
LDO-CTL
LDO-FB
TEMP
FBP
C1
P N
C2
LX
LXL
PGND
PVIN
SUPP
SUPN
AGND
GND_HS
COMP
HVS
EN PROT
P N
CTL CDEL
VL
CM2
1 2
FBB
RSET
POUT
VIA VIA
VIA
VIA
7J04 I11 7J05 J11 FJ00 A9 FJ01 A12 FJ02 C10 FJ03 D10 FJ04 E3 FJ05 F9 FJ06 I8 FJ07 I10 FJ09 J11 FJ10 F12 FJ11 E12 FJ13 E13 FJ14 E14 FJ55 G16 cK00 F6
DISPLAY INTERFACING - VDISP
4J04-2 H15 4J04-3 H15 4J04-4 H15 4J05 J7 5J00 E12 5J06 A9 5J07 G14 5J08 G14 6J00 I11 6J01 E14 6J02 I5 6J05 E12 6J06 A8 6J07 G16 7J00-1 C6 7J00-2 G6 7J01 A8 7J02 A11 7J03 E8
3J18 I7 3J19 H10 3J20 H10 3J21 I11 3J22 I12 3J23 J11 3J24 E12 3J25 F12 3J26 E13 3J27 E14 3J28 G16 3J29 E14
4J00-1 A8 4J00-2 A8 4J00-3 A8 4J00-4 A8 4J01-1 A11 4J01-2 A11 4J01-3 A11 4J01-4 A11 4J02-1 I11 4J02-2 I11 4J02-3 I11 4J02-4 I11 4J03 F5 4J04-1 H15
2J44 B5 2J45 B5 2J46 B5 2J47 B5 2J48 B5 2J49 B6 2J50 E15
3J00 B7 3J01 B7 3J02 B10 3J03 B10 3J04 C10 3J05 B10 3
J06 D8 3J07 D5 3J08 E5 3J09 D10 3J10 E9 3J11 E8 3J12 E8 3J13 F6 3J14 F7 3J15 G8 3J16 G8 3J17 H7
2J29 I8 2J30 I10 2J31 I10 2J32 D9 2J33 E9 2J34 E9 2J35 E11 2J36 E13 2J37 F13 2J38 E13 2J39 E13 2J40 E13 2J41 E14 2J42 G14 2J43 G15
2J05 B9 2J06 B10 2J07 B11 2J08 B11 2J09 B11 2J10 B12 2J11 B10 2J12 C10 2J13 C7 2J14 C6 2J15 D5 2J16 D8 2J17 D5 2J18 D5 2J19 E5 2J20 E5 2J21 E5 2J22 F6 2J23 E7 2J24 F8 2J25 F9 2J26 G9 2J27 G9 2J28 H8
16 17
123 45678 9 10111213 14 15 16 17
A
B
C
D
E
F
G
F
G
H
I
J
K
1J00 G15 1J01 G15 2J00 B7 2J01 B7 2J02 B7 2J03 B8 2J04 B9
123 45678 9101112
13 14 15
FOR DEBUG ONLY
H
I
J
K
A
B
C
D
E
6J07
LTST-C190KGKT
3J14 27K
4n7
2J15
RES
SGND1
4J05
2J50
100n
2K2
3J29
220n2J34
SGND1
2J09
10u
3J16
2K2
RES
16V
22u
2J25
2K2
3J28
2J43
10u
+VDISP
RES1J00
T3.0A
3J05
100K
RES
VCC1V8SGND1
4
1
2
3
FDS9435A
7J02RES
5
6
7
8
4J01-445
SS24
FJ14
6J05
cK00
3J07
10K
3J24
20K
10u
2J04
5J06
SS34
6J06
6u8
4n72J21
SGND1
+VDISP
SGND1
4J03
VLS_15V6_B
RES
1
2
3
VCC_3V3
7J03
KTA1663
13K3J12
SGND1
1u0
2J35
SGND1
RES
5J08
30R
30R
+VDISP-INT
RES
5J07
RES
2J36
1n0
1n0
2J37
RES
SGND1SGND1
VLS_15V6
3J25
12K
100n2J16RES
100p
2J29
100n
2J28
RES
4J02-445
4J02-33 6
FJ01
1 8
4u72J20
4J01-1
220n2J19
FJ00
3
4J02-11 8
7J04 2SB1767
RES
1
2
100n
2J31
RES
31
9
10
4u7
2J30
5
6
14
21
36
38
1
28
12
41
27
40
39
34 35
3
4
13
32
33
7
22
30
24
23
26
29
8
11
20
37
16
15
18
17
225
Φ
ISL97653AIRZ
7J00-1
220n2J32
3J26 240K
VGL_-6V
FJ02
3J18
750K
3J17
27K
3 6
4J00-227
RES 4J00-3
4J00-11 8
RES
5
6
7
8
4
1
2
3
RES
FDS9435A
7J01
3J00
2K2
RES
100n
2J02
2J42
22u
RES
2u2
2J03
10K
4J00-445
3J01
27
RES
4J02-2
RES
3J02
39K
10n
2J06
VLS_15V6_B
RES
312
RES
3 6
7J05
2N7002
4J01-227 4J01-3
3J27
2K2
16V 22u
2J41
10u
2J01
2u2
2J00
T3.0A
1J01
+VDISP
RES
FJ11
SGND1
FJ03
FJ05
RES
RES
2J27
120p
1n0
2J11
2J12
1n0
SGND1
RES
RES
2K2
3J09
3K6
RES
SGND1
VCC_3V3
VGH_35V
3J23
2J24
2u2
2u2
2J39
RES
RES
22u
2J38
RES
3J10 39K
4
2
820p2J33
6J01
RB550EA
1
3
5
FJ09
120p
2J26
RES
VGL_-6V
2J40
SGND1
100p
RES
10u
2J07
25V47u
2J08
10n
2J23
1
3
5
4
2
VLS_15V6
SGND1
6J02
RB550EA
2u2
2J10
RES
10u
2J05
2K2
3J15
RES
4J04-33 6
FJ06
FJ55
FJ07
FJ10
48
49
50
FJ13
53
54
55
56
57
43 44 45
46
47
VIA
7J00-2
ISL97653AIRZ
42
51
52
3J13
2K2
RES
RESRES
2J48
10u
10u
2J47
10u
2J45
RES
2J49
47u 25V
RES
2J44
2u2
2J46
10u
+VDISP
2K2
RES
3J20
4J04-445
8
4J04-227
4J04-11
3J04
3K3
3J03
39K
RES
3J19
2K2
SGND1
10K
3J22
4u7
2J13
2u2
2J22
VLS_15V6
100n2J18
3J08
VCC_3V3
RES
2K2
3J06
2K2
RES
2u2
2J14
3J11 10K
100n2J17
4u5
5J00
RES
FJ04
3J21
RES
6J00
PMEG1030EJ
2K2
GSLOP
GSLOP
Circuit Diagrams and PWB Layouts
EN 59LC10.1L LA 10.
2010-Apr-06
Page 60
Circuit Diagrams and PWB Layouts
18980_517_100329.eps
100329
P Gamma, VCOM & NVM
B08C B08C
2010-01-22
1
3140 123 6483
BR-M-50
PCB SB SSB DIGITIAL
-BUS CTRL
FIL
I2C
INP
INPCOM|DVR_OUT
REFIN_INN
REFIN
SET
SCL SDA
SET_COMP
V_THERM
BANKSEL
GND_HS
VIA
GND
OUT10
OUT11
OUT12
OUTCOM
INNCOM
AVDD
OUT1
OUT2
OUT3
OUT4
OUT5
INN5
OUT6
INN6
OUT7
INN7
OUT8
INN8
OUT9
VSD
SCL
ADR
0 1 2 SDA
WC
I2C SWITCH (VGA VCOM)
FK15 D10 FK16 D10 FK18 E10 FK19 F10 FK20 F10 FK22 F10 FK23 F10 FK24 F10 FK27 B15 FK28 B15 FK29 B15 FK33 J13 FK35 G12 FK36 H12 FK37 H13 FK38 B15 FK40 C10 FK42 C10 FK44 C10 FK46 D10 FK47 E10 FK51 F10 FK52 F10 FK53 H12
4K16 E9 4K17 F9 4K18 F9 4K19 F9 4K20 F9 4K21 F9 4K22 C9 6K00 G12 7K00 B4 7K01 G4 7K02 H4 7K03 D13 7K04 G12 7K05 E13 7K06 F13 FK00 B2 FK01 C2 FK02 B3 FK03 B4 FK04 D3 FK05 D3 FK06 D3 FK07 F4 FK08 G4 FK10 C10 FK11 C10 FK14 D10
3K49 C13 3K50 C14 3K51 C13 3K52 G13 3K53 G13 3K54 G14 3K55 H14 3K56 H14 3
K60 B12
3K61 C12 3K62 H12
4K00 C9 4K01 C9 4K02 D9 4K03 E9 4K04 F9 4K05 F9 4K06-1 F4 4K06-2 F4 4K06-3 F4 4K06-4 F4 4K07 C9 4K08 C9 4K09 C9 4K10 C9 4K11 D9 4K12 D9 4K13 D9 4K14 E9 4K15 E9
3K05 B5 3K06 D3 3K07 D5 3K08 D3 3K10 E3 3K11-1 C8 3K11-2 C8 3K11-3 C7 3K11-4 C7 3K12-1 E7 3K12-2 E7 3K12-3 E8 3K12-4 E8 3K13-1 G7 3K13-2 G7 3K13-3 G8 3K13-4 G8 3K14 G4 3K15 G4 3K16 G5 3K17 G5 3K34 G
8 3K35 J13 3K36 K13 3K40 B11 3K41 B11 3K44 B13 3K45 B13 3K46 B14
2K06 D7 2K07 D7 2K08 D8 2K09 D8 2K10 E7 2K11 E7 2K12 E8 2K13 E8 2K14 G7 2K15 G7 2K16 G8 2K17 G8 2K18 G5 2K19 G4 2K20 G3 2K21 G4 2K24 C13 2K25 C13 2K26 C14 2K27 D13 2K28 G12 2K30 C12
3K00 B2 3K01 B2 3K02 C2 3K03 B3 3K04 C3
NC
ASIC OPTIONS
5678 910111213 14 15
A
B
C
D
E
F
G
H
NC
SSB-TCON EEPROM
NC
NC
11 12 13 14 15
123 4
123 45678 910
VCOM BUFFER
I
J
K
A
B
C
D
E
F
G
H
I
J
K
U3 F5 1K00 J14 2K00 B2 2K01 B2 2K02 B3 2K03 B4 2K04 B4 2K05 B5
7K02
PBSS5330X
FK33
10K
06K316K3
10K
RES
FK00
2K27
100n
FK01
FK03
FK02
FK08
FK06
4K02
10K
3K08
RES
RES 4K11
FK44
3K50
10K
1n0
2K30RES
100n
2K10
2K11
100n
4K18 4K04
RES
FK14
FK19
FK11
RES 4K07
4K22RES
4K03
4K15RES
RES 4K14
0.5%6K2
3K01
RES
10K
3K46
10K
3K51
RES
3K45
10K
3K49
K01K01
3K44
3K34
RES
2K2
2K05
10u
0.5%2K2
3K05
10K
3K35
DEB
274K06-2
DEB
3K36
10K
+VDISP
FK47
SD1 7SDA2
VDD
3
VSS 6
SC0 5
SC1 8
SCL 40DS1
VCC_3V3
RES
PCA9540B
7K03
FK16
6
FK10
3K13-3
10R
3
45
PBSS4540X
7K01
3 6
4K06-4
4K06-3
2K03
100n
FK24
VLS_15V6
2K07
100n
FK20
FK42
4K10RES
FK40
FK18
100n
2K08
FK22
FK15
1 8
FK38
3K11-1
10R
FK28 FK29
FK27
RES 4K08
RES 4K21
4K06-11 8
3K15
0R51 0R51
3K14
VLS_15V6VLS_15V6
100n
2K04
4K09RES
1 8
FK36
3K13-1
10R
100n
2K17
10K
FK07
45
3K10
FK46
10R
3K11-4
3K11-3
10R
3 6
27
VREF_15V2
10R
3K11-2
27
1 8
3K12-2
10R
10R
3K12-1
2K13
100n
2K14
100n
100n
100n
2K15
2K16
6
5
8
4
7
EEPROM
Φ
(8K × 8)
1 2
3
4K01
M24C64-WDW6
7K04
1n0
2K25
FK52
RES
FK53
3K3
3K06
0.5%
100n
100n
2K06
2K09
VCC_3V3
10 11
2
3
4 5 6 7
8
9
1213
BM11B-SRSS-TBT
DEB
1
18K
3K04
1K00
3K03
0.5%
VCC_3V3
0.5%22K
3K02
37 38 39
40 41
29
31
0.5%10K
19
25
32
1
13 12
28
30
34 35 36
22
23
24
3
4
7
8
10
16
18
14
6
20
33
9
11
15
17
26
27
2
7K00
ISL24837IRZ-T13
5
21
4K17RES
0.5%100K
3K00
2K01
1u0
2K00
1u0
100R
3K62
6K8
3K40
4K12RES
4K05
2K2
3K07
RES
10R
45
100n
2K12
3 6
3K12-4
10R
3K12-3
2K02
100n
4K16
FK35
RES
U3
VCC_3V3
RES 4K13
0.5%750R
3K16
0.5%
5K1
3K17
1n0
RES
VCC_3V3
FK23
2K24
FK51
RES 2K21
100n
2K19
10u
FK37
VCC_3V3
2K18
68p
3K56 2K0
4K20RES
6K00
VCC_3V3
6K8
3K54
MSS1P4
6K8
3K53
2K03K55
100n
2K28
RES
VLS_15V6
2K26
1n0
3K52
2K0
4K19RES
4K00
312
VCC_3V3
2
7K06
BSH111
BSH111 7K05
3
1
10R
3K13-2
27
3K41
6K8
FK04 FK05
2K20
22u 16V
45
10R
3K13-4
RESET
WP_TCON
SDA-TCON
SCL-TCON
VL31
SCL-TCON
SDA-TCON
SDA_VGA
WP_TCON
ROM_SCL
ROM_SDA
50Hz_60Hz
VH63
VH247
VH95
VH191
VL0
VH0
CS_L
ROM_SDA
ROM_SCL
BYPASS_MODE
SDA-TCON
VH255
VH95 VH31 VH63
VL159
VL95
VL63
VH159
VL95
VL191
SCL-TCON
SDA-TCON
SELLVDS
R_L U_D
SCL_VGA
SCL-TCON
VL127
VL31
VH31
OUTCOM
INNCOM
VCOM
VL63
INNCOM
OUTCOM
VH127
VL127
VH127
VL247
VH127
VL127

SSB: P Gamma, VCOM & NVM

EN 60LC10.1L LA 10.
2010-Apr-06
Page 61

SSB: MPD

18980_518_100329.eps
100329
MPD
B08D B08D
2010-01-22
1
3140 123 6483
BR-M-50
PCB SB SSB DIGITIAL
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
+
REFL
REFH
7
6
5
4
3
2
1
AVDD
VIA
-
GND_HS GND
NC
OUTB
OUTA
-
INA
+
INB
IN
OUT1
4L02-2 F2 4L02-3 E2 4L02-4 E2 7L00 C8 7L01 B10 7L02 B8 FL00 C5 FL01 C5 FL02 C5 FL03 D5 FL04 D5 FL05 D5 FL06 E5 FL07 E5 FL08 E5 FL09 E5 FL10 F5 FL11 F5 FL12 C10 FL13 B10 FL14 A9 FL15 B8
3L02-1 F5 3L02-2 F5 3L02-3 F5 3L02-4 F5
NC NC
NC
3L12 C10 3L13 C10 3L14 B10 3L15 B9 3L16 B9 3L17 B8
4L00-1 D2 4L00-2 C2 4L00-3 C2 4L00-4 C2 4L01-1 E2 4L01-2 E2 4L01-3 D2 4L01-4 D2 4L02-1 F2
2L11 G5 2L12 D9 2L13 C11 2L14 C8 2L15 C8 2L16 B11
3L00-1 F3 3L00-2 F3 3L00-3 F3 3L00-4 F3 3L01-1 F4 3L01-2 F4 3L01-3 F4 3L01-4 F4
8 91011
FOR 32" / 40"
2L08 G5 2L09 G5 2L10 G5
2L04 G4 2L05 G4 2L06 G4 2L07 G4
123 45678 91011
123 4567
A
B
C
D
E
F
G
A
B
C
D
E
F
G
2L00 G3 2L01 G3 2L02 G3 2L03 G3
100n
2L00
3L00-4
45
10R
3 6
10R
27
3L00-3
27
10R
3L00-2
4L02-1
1 8
VREF_15V2
RES
4L01-2
4L02-2
27
RES
+VDISP
RES
FL15
3L16
33R0.5%
3L17
1R0
100n
2L16
4L00-1
1 8
100n
2L14
RES
FL12
FL13
2L13
100n
1n0
2L12
3 6
4L00-4
45
RES
4L01-3
4L00-3
3 6
RES
RES
4L00-2
27
RES
2L11
100n
45
3 6
10R
3L02-4
27
3L02-3
10R
10R
3L02-2
100n
2L07
10R
1 8
3L00-1
3L13
10K 0.5%
3L14
82K 0.5%
4L02-4
45
3
4
52
RES
+VDISP
NJM2125F
7L01
1
3L15
4L02-3
3 6
0.5%33R
RES
16V22u
2L15
RES
4L01-1
1 8
FL14
3 6
27
10R
3L01-3
3L01-2
10R
2L02
100n
2L03
100n
RES
4L01-4
45
FL08
FL07
FL06
100n
2L10
2L09
100n
100n
2L08
FL02
FL00
FL01
3L02-1
10R
1 8
2
3
7L02
2SC5886A
1
34 35 36 37 38 39
40 41 42
8
19 20 21 22 23 24
18
17
10 11
14 15 16
9
1 2
3
4 5 6 7
12
33
32 31 30
29 27 26 25
13
ISL24016IRTZ
7L00
28
2L06
100n
100n
2L05
1 8
10R
3L01-1
2L01
100n
FL10
FL11
FL09
3L12
62K
FL05
FL04
45
FL03
3L01-4
10R
2L04
100n
CS6 CS7 CS8 CS9 CS10 CS11 CS12
VCOM
ASIC_CS1 ASIC_CS3 ASIC_CS5 ASIC_CS7 ASIC_CS9
ASIC_CS11
CS9
CS10
CS11
CS12
CS1
CS2
CS3
CS4
CS5
CS6
CS7
CS8
CS1 CS2 CS3 CS4 CS5
CS_L
Circuit Diagrams and PWB Layouts
EN 61LC10.1L LA 10.
2010-Apr-06
Page 62

SSB: Mini LVDS

18980_519_100329.eps
100329
Mini LVDS
B08E B08E
2010-01-22
1
3140 123 6483
BR-M-50
PCB SB SSB DIGITIAL
FM80 E10 FM81 E10 FM82 E10 FM83 E10 FM84 E10 FM85 E10 FM86 E10 FM87 E10 FM89 F10 FM90 F10 FM91 F10 FM92 F10 FM93 F10 FM94 F10 FM95 F10 FM96 F10 FM97 C5 FM98 B10
FM53 G5 FM54 G5 FM65 H5 FM69 B10 FM70 B10 FM71 B10 FM72 B10 FM73 D10 FM74 D10 FM75 D10 FM76 D10 FM77 D10 FM78 D10 FM79 E10
FM31 E5 FM32 E5 FM33 E5 FM34 E5 FM35 E5 FM36 E5 FM38 F5 FM40 F5 FM41 F5 FM42 F5 FM43 F5 FM44 F5 FM45 F5 FM46 F5 FM47 F5 FM48 F5 FM49 G5 FM50 G5 FM51 G5 FM52 G5
4M04-3 E4 4M04-4 E4 4M08-1 F9 4M08-2 F9 4M08-3 F9 4M08-4 F9 4M11 F4 4M13-1 F9 4M13-2 F9 4M13-3 F9 4M13-4 F9 FM00 B5 FM01 B5 FM02 B5 FM03 B5 FM04 B5 FM05 B5 FM06 C5 FM30 E5
10 11 12
A
B
C
D
E
3M10 C4 3M13 E7 3M14 E7 3M15 E2 3M16 F2 3M17 H10 3M18 H5
4M00-1 E4 4M00-2 E4 4M00-3 E4 4M00-4 E4 4M04-1 E4 4M04-2 E4
2M04 H5
3M00 B9 3M01 B9 3M02 B4 3M03 B9 3M07 B4 3M08 B9 3M09 B4
123 45678 9101112
123 45678 9
F
G
H
I
A
B
C
D
E
F
G
H
I
1KA1 B10 1KA2 B5 2M01 E11 2M02 E6 2M03 H9
FM70
FM69
FM71
FM44
FM31
FM43
FM41 FM42
FM47
FM40
FM72
FM54
FM53
RES
FM52
2M01
100n
FM83
FM49
FM82
FM89
FM81
FM80
FM51
FM79
FM50
FM03 FM04
FM02
FM78
FM01
FM77
4M13-11 8
FM76
4M13-227
RES
45
RES
FM96
4M13-4 RES
FM94
FM95
FM93
FM91 FM92
FM30
FM45
FM34
FM33
FM48
FM32
FM46
FM38
VLS_15V6
VCC_3V3
FM06
FM05
FM7
3
FM86
FM85
FM84
FM87
FM90
FM00
3M09
FM74
68R
68R3M00
68R3M10
RES
2M03
10u
3M17
20R
FM35 FM36
3M07
3M02
68R
68R
4M13-3
RES
3 6
VCC_3V3
FM65
FM75
68R
3M14
RES3M13
68R
4M08-445
27
4M08-33 6
1 8
4M08-2
VGH_35V
4M08-1
VGL_-6V
FM97
FM98
RES
1 8
4M04-227
4M00-1
68R
3M15RES
20R
3M18
6
4M00-4 RES45
RES
27
4M00-3
RES
3
4M00-2
RES
100n
2M02
68R3M08
68R3M03
3M01 68R
75
76
77
78
79
8
80
9
81 82
66
67
68
69
7
70
71
72
73
74
56
57
58
59
6
60
61
62
63
64
65
46
47
48
49
5
50
51
52
53
54
55
37
38
39
4
40
41
42
43
44
45
27
28
29
3
30
31
32
33
34
35
36
18
19
2
20
21
22
23
24
25
26
1KA2
196250-80041
1
10
11
12
13
14
15
16
17
VGH_35V
4M11
VLS_15V6
3M16 68R
10u
2M04
VGL_-6V
RES
75
76
77
78
79
8
80
9
81 82
66
67
68
69
7
70
71
72
73
74
56
57
58
59
6
60
61
62
63
64
65
46
47
48
49
5
50
51
52
53
54
55
37
38
39
4
40
41
42
43
44
45
28
29
3
30
31
32
33
34
35
36
18
19
2
20
21
22
23
24
25
26
27
1
10
11
12
13
14
15
16
17
1KA1
196250-80041
1 8
45
4M04-1
3 6
4M04-4
4M04-3
U_D_INV
LLV6-
LLV7+ LLV7-
LLV1-
LLV2-
LLV2+
LCK-
LCK+
LDIO2 R_L LDIO1
LLV6+
GOE
GCK
U_D
LLV3+
LLV4-
LLV4+
LLV5-
LLV5+
LLV1+
LLV0-
LLV0+
CS3
CS2
CS1
GSP1
GSP2
VL63
VL31
LS
GSP1
GSP2
VH255
VL127
VCOM
CS12
CS11
CS10
CS9
CS8
CS7
CS6
CS5
CS4
VL95
VL191
VL159
VH0
VH31
VH63
VH95
VH127
VH159
VH191
VH247
RLV3-
RLV3
+
RLV4-
RLV4+
RLV5-
RLV5+
LLV3-
VL0
VL247
REV
VL159
VL127
VL95
VL63
VL31
RLV0-
RLV0+
RLV1-
RLV1+
RLV2-
RLV2+
RCK-
RCK+
VH127
VH159
VH191
RLV7+ RLV7­RLV6+ RLV6-
RDIO2 R_L RDIO1
GSP2 GSP1
LS
VL191
CS1
CS12
CS11
CS10
CS9
CS8
CS7
CS6
CS5
CS4
CS3
CS2
VH31
VH63
VH95
VL0
VL247
REV
VH0
VH247
VH255
VCOM
GOE
GCK
GSP1
GSP2
Circuit Diagrams and PWB Layouts
EN 62LC10.1L LA 10.
2010-Apr-06
Page 63
Circuit Diagrams and PWB Layouts
1201
1211
1402
1403
1700
1701
1702
1703
1705
1706
1707
1735
1901
1902
1A01
1A02
1A03
1B01
1B02
1B05
1C00
1C01
1C02
1C03
1C05
1C07
1C08
1C09
1C10
1C14
1C15
1C16 1C17 1C18
1C19
1D01
1E01
1F00
1F01
1F02
1H00
1J00
1J01
1K00
1KA11KA2
1M20
1M95 1M99
2123
2124
2140
2147
2148
2150
2151
2158
2159
2162
2164
2168
2170
2173
2174
2175
2181
2182
2185
2186
2187
2190
2191
2195
2196
2197
2213
2285
2286
2287
2288
2289
2290
2291
2293
2296
2297
2301
2302
2303
2304
2305
2306
2307
2308
2309
2310
2311
2312
2313
2314
2315
2316
2317
2318
2319
2320
2321
2322
2372
2374
2375
2376
2400
2401
2402
2403
2404
2405
2406
2407
2408
2409
2411
2412
2415
2416
2422
2424 2425
2514
2549
2551
2608
2609
2628
2700
2701
2702
2703
2704
2706
2716
2717
2719
2720
2722
2723
2724
2725
2726
2727
2728
2729
2803
2804
2806
2807
2900
2901
2A00
2A01
2A04
2A05
2A06
2A07
2A09
2A10
2A11
2B00
2B01
2B02
2B03
2B05
2B06
2B07
2B08
2B09
2B11
2B12
2B14
2B15
2B19
2B20
2B24
2B25
2B30
2B31
2B32
2B33
2B34
2B35
2B36
2B37
2B38
2B39
2B40
2B41
2B43
2B44
2B50
2B51
2B52
2B54
2B55
2B56
2B57
2B58 2B59
2C00
2C01
2C02
2C03
2C04
2C05
2C06
2C07
2C08
2C092C14
2C15
2C16
2C17
2C18
2C19
2C20
2C21
2D14
2E00
2E02
2E04
2E05
2E08
2E11
2E12
2E13
2E14
2E15
2E16
2F002F01
2H40
2H41
2H45 2H46
2J00
2J01
2J02
2J03
2J04
2J05
2J08
2J11
2J12
2J13
2J14
2J15
2J16
2J17
2J18
2J19
2J22
2J23
2J26
2J27
2J34
2J35
2J38
2J39
2J42
2J43
2J44
2J46
2J49
2K00
2K01
2K02
2K03
2K04
2K05
2K10
2K11
2K12
2K13
2K14
2K15
2K16
2K17
2K18
2K19
3110
3112
3267
3268
3269
3270
3350
3353
3355
3356
3360
3411
3414
3415
3420 3421
34273428
3436
3600
36023605
3606
3607
3608
3609
36103611
3612 3613
3614
3615
3617 3618
3619
3706
3707
3709
3711
3715
3716
3717
3718
3719
3735
3741
3748
3749
3758
3767
3770
3782
3784
3785
3787
3788
3790
3791
3792
3793
3794
3795
3796
3798
37A8
3805
3806
380738083809
3900
3901 3902
3904
3905
3914
3923
3924
3A00
3A02
3A03
3A09
3A10
3A15
3B00
3B01
3B02
3B03
3B05
3B06
3B07
3B08
3B09
3B11
3B12
3B14
3B15
3B16
3B27
3B28
3B29
3B30
3B31
3B32
3B33
3B34
3B40
3B41
3B433B44
3B45
3B46
3B48
3B49
3B50
3B51
3B52
3B53
3C00
3C01
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3C13
3C14
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3E00
3E02
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3E14
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3E18
3E19
3E20
3E21
3E22
3E23
3E24
3E25
3E26
3E27
3H01
3H02
3H05
3H07 3H08
3H093H10
3H11
3H123H13
3H14
3H15 3H16
3H173H18
3J00
3J01
3J03
3J04
3J06
3J07
3J08
3J09
3J13
3J153J16
3J19
3J28
3K00 3K01
3K02
3K05
3K06
3K07
3K08
3K10
3K12
3K13
3K14
3K15
3K16
3K17
3K34
4209
4306
4307
4308
4309
4701 4702
4900 4901
4A00
4E02
4E04
4H05
4J00
4J03
4J04
4K02
4K04
4K05
4K06
4K08
4K09
4K11
4K12
4K13
4K17
4K18
4K19
4K21
4K22
4L00
4L01
4L02
4M00 4M04
4M08 4M13
5103
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5115
5116
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5119
5120 5121
5213
5226
5227
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5310
5324
5402
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5506
5700
5C00
5C01
5C02
5C03 5C04
5C05
5E01
5E02 5E045E05
5H02
5H03
5J00
5J06
6103
6122
6123
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6125
6301
6401
6402
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6700
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6800
6900
69136914
69156916
6917
6A00
6B00
6B01
6C00 6C01 6C02 6C03
6C04
6C05
6C066C07
6C08 6C09
6C10
6C19
6C20
6E016E02 6E036E04
6E05
6E06
6J05
6J06
6J07
7107
7116
7117
7216
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7219
7301
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7411
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7709
7800
7801
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7902
7D00
7E01
7H00
7H01
7H02
7H05
7J00
7J01
7K01
7K02
7K03
7K04
C400
CK00
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EN 63LC10.1L LA 10.
2010-Apr-06
Page 64
Circuit Diagrams and PWB Layouts
1213
1301
1B03
1B04
1C06
1D00 1D021D03
1E00
1E02
1E03
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1E05
1G51
2125
2126
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2A02
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2B16
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2B42
2B53
2C10
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2C12
2C13
2D11
2D12
2D15 2D16
2E03
2E07
2E09
2E10
2H01
2H02
2H03
2H04
2H05
2H06
2H07
2H08
2H09
2H10
2H13
2H25
2H26
2H27
2H28
2H29
2H30
2H31
2H32
2H33
2H34
2H35
2H36
2H37
2H38
2H39
2H42
2H43
2H44
2H47
2H48
2H50
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2H52
2H53
2H54
2J06
2J07
2J09
2J10
2J20
2J21
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2J28
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2J31
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2J33
2J36
2J37
2J40
2J41
2J45
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2J50
2K06
2K07
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2K20
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2K30
2L00
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2L10 2L11
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2M01
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3105
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3119
31223125
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3223
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3772 3773
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37A1
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37A337A4
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3912 3913
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3A01
3A04
3A11
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3A14
3A16
3A17
3B35
3B36
3B37
3B38
3B39
3B42
3B47
3C09
3C11
3D09 3D10
3E03
3E10
3E13
3E16
3E17
3F00
3F01
3F02
3F03
3H00
3H03
3H04
3H06
3H19
3H20
3H21
3H22
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3H25
3H26
3H27
3H28
3J02
3J05
3J10
3J11
3J12
3J14
3J17
3J18
3J20
3J21
3J22
3J23
3J24 3J25
3J26
3J27
3J29
3K03
3K04
3K11
3K35
3K36
3K40
3K41
3K44
3K45
3K46
3K49
3K50
3K51
3K52
3K53
3K54
3K55
3K56
3K60
3K61
3K62
3L00 3L01
3L02
3L12
3L13
3L14
3L15
3L16
3L17
3M00
3M01
3M02
3M03
3M07
3M08
3M09
3M10
3M13
3M14
3M15
3M16
3M17
3M18
4208
4210
4211
4300
4301
4303
4304
4305
4310
4311
4401
4700
4703
4704
4705
4706
4707
4708
4800
4801
4802
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4804
4805
4806
4807
4808
4902
4903
4904
4A01
4A02
4A03
4E03
4H04
4J01
4J02
4J05
4K00
4K01
4K03
4K07
4K10
4K14
4K15
4K16
4K20
4M11
5207
5212
5222
5225
5308
5309
5311
5323
5400 5401
5406
5500
5501
5502
5503
5504
5505
5705
5800
5801
5802
5D00
5E00
5E03
5F00
5F01
5H00
5H01
5H04
5H05
5H06
5J07
5J08
6400
6706
6707
6708
6709
6901
6902
6903 6904
6905
6906 6907
6909
6910
6911
6912
6A01
6D00
6D01
6D02
6E00
6J00
6J01
6J02
6K00
7212
7213
7302
7315
7401
7408
7409
7410
7414
7701
7702
7703
7705
7708
7710
7900
7901
7903
7904
7905
7906
7907
7908
7A00
7B01
7E00
7H03
7H04
7J02
7J03
7J04
7J05
7K00
7K05
7K06
7L00
7L01
7L02
A210 A211
A212
A213
A214
A225
CXXX
F102
F103
F104
F105
F106
F107
F108
F109
F110
F111
F112
F113
F114
F115 F116
F117
F118
F119
F120
F121
F122
F123
F124
F125
F131
F132
F133
F134
F135
F201
F202
F203
F204
F205
F206
F207
F208
F209
F213
F214
F215
F216
F227
F235
F236
F237
F240
F241
F242
F243
F244
F245
F246
F300
F301
F302F303
F305
F306
F400
F401
F402
F404
F405
F406
F408
F409
F410
F411
F412
F413
F414
F415
F416
F417
F500
F501
F502
F503
F600
F601
F602
F701
F702
F704
F705
F706
F707
F708
F716
F717F718
F719
F721
F723
F724
F725
F736
F737
F738
F739
F740
F741
F742
F743
F744
F745
F746
F747
F748
F749
F750
F751
F752
F753
F754 F755
F756
F757 F758
F759
F760
F761
F763
F764
F765
F766
F770
F771
F800
F801
F805F806
F807F808
F809F810
F811
F812
F813F814
F815F816
F817
F818
F819
F820
F821
F822
F823F824
F825F826
F827F828
F829
F831
F900
F901
F902
F903
F904
F905
F906
F907F908
F909
F911
F912
F913
FA00
FA01
FA02
FA03
FA04
FA06
FA07
FA08
FA09
FB00
FB01
FB02
FB03
FB04
FB06
FB07
FB08
FC00
FC01
FC02
FC03
FC04FC05
FC06
FC07
FC08
FC09
FC10
FC11
FC12
FC13FC14
FC15
FD00
FD01
FD02
FD03
FD04
FD05
FD06
FE00
FE01
FE02
FE03
FE04
FE05
FE06
FE07
FE08
FE09
FE10
FE11
FE12
FF00
FF01
FF02
FF03
FF04
FF05
FF06
FF07
FF08
FF09
FF10
FF11
FF12
FF13
FH00
FH01
FH02
FH03
FH04
FH05
FH06
FH34
FH35
FJ00
FJ01
FJ02
FJ03
FJ04
FJ05
FJ06
FJ07
FJ09
FJ10
FJ11
FJ13
FJ14
FJ55
FK00
FK01
FK02
FK03
FK04
FK05
FK06
FK07
FK08
FK10
FK11
FK14
FK15
FK16
FK18
FK19
FK20
FK22
FK23
FK24
FK27
FK28
FK29
FK33
FK35
FK36
FK37
FK38
FK40
FK42
FK44
FK46
FK47
FK51
FK52
FK53
FL00
FL01
FL02
FL03
FL04
FL05
FL06
FL07
FL08
FL09
FL10
FL11
FL12
FL13
FL14
FL15
FM00
FM01
FM02
FM03
FM04
FM05
FM06
FM30
FM31
FM32
FM33
FM34
FM35
FM36
FM38
FM40
FM41
FM42
FM43
FM44
FM45
FM46
FM47
FM48
FM49
FM50
FM51
FM52
FM53
FM54
FM65
FM69
FM70
FM71
FM72
FM73
FM74
FM75FM76
FM77
FM78
FM79
FM80
FM81
FM82
FM83
FM84
FM85
FM86
FM87
FM89
FM90
FM91
FM92
FM93 FM94
FM95
FM96
FM97
FM98
I104
I105 I106
I107
I117I118
I119
I120
I122
I123
I125
I126
I127 I128
I129
I130
I131
I132
I134
I135
I136
I137
I138
I139
I220
I221
I222
I228
I230
I231
I232
I233
I234
I235
I237
I238
I239
I240
I242
I243
I244
I245
I247
I249
I251
I254
I255
I300
I301
I302
I303
I304
I305
I306
I307 I308
I309
I310
I311
I312
I313
I314
I315
I316
I317
I318
I319
I320
I321
I322
I323
I324
I325
I327
I328
I336
I337
I338
I401
I403
I405
I406
I407
I410
I411
I412
I413
I414
I415
I416
I417
I418
I419
I420
I421
I422
I423
I424
I425
I429
I430
I431
I432
I433
I434
I435
I436
I437
I438
I440
I441
I442
I443
I502
I503
I504
I505
I506
I507
I700
I701
I707
I708
I710
I711
I713
I714
I715
I716
I718
I725
I726
I727
I731
I732
I733
I734
I735
I737
I738
I739
I741
I742
I743
I744
I745
I746
I747
I749
I750
I752
I753
I754
I755
I756
I757
I800
I801
I802
I804
I805
I806
I807
I808
I809
I900
I901
I902
I903
I904
I905
I906
I907
IA00
IA01
IA02
IA03
IA04
IA05
IA08
IA09
IA10
IB00
IB01
IB02
IB03
IB04
IB05
IB06
IB07
IB08
IB09
IB10
IB12
IB13
IB14
IB15
IB16
IB17
IB18
IB19
IB20
IB21
IB22
IB23
IB24
IB25
IB26
IB27
IB28
IB29
IB30
IB31
IB32
IB33
IB34
IB35
IB36
IB37
IB38
IB39
IB40
IB41
IB42
IB43
IB44
IB45
IB46
IB47
IB48
IB49
IB50
IB51
IB52
IB53
IB59
IB61
IB62
IB63
IB64
IB65
IB66
IB67
IC01
IC02
IC03
IC04
IC05
IC06
IC07
IC08
IC09
IC10
IC11
IC13
IC14
ID04
IE00
IE01
IE02
IE03
IE04
IE05
IE06
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Page 65

SSB: SRP List Explanation

1 . 1 . Introduction
Example
SRP (Service Re ference Protocol) is a softw are too l that creates a list w i th all refer e n c es to signal lines. The list contains references to the signals w i thin all schemat ics of a PWB. It replaces the text refe r ences currentl y p r inted next t o the signal names in the s
chematics. These printed refe rences are created man ually an d are t h e r efore n o t guar an teed to be 100 % correct. In additio n , in the current crowded schema t ics there is often none or ver y little pl ace for these references. Either there will be an SRP
reference list for a schematic, or there will be printed references in the schematic.
1.2. Non-SRP Schematics
There are several different signals available in a schematic:
1.2.1. Power Supply Lines
All power supply lines are available in the supply line overview (see chapter 9). In the schematics (see chapter 10) is not indicated where supplies are coming from or going to. It is however indicated if a supply is incoming (created elsewhere), or outgoing (created or adapted in the current schematic).
+5V +5V
Outgoing Incoming
1.2.2. Normal Signals
For normal signals, a schematic reference (e.g. B14b) is placed next to the signals.
signal_name
B14b
1.2.3. Grounds
For normal and special grounds (e.g. GNDHOT or GND3V3 etc.), nothing is indicated.
1.3. SRP Schematics
SRP is a tool, which automatically creates a list with signal references, indicating on which schematic the signals are used. A reference is created for all signals indicated with an SRP symbol, these symbols are:
+5V +5 V
Power supply line.
name name
Stand alone signal or switching line (used as less as possible).
name name
Signal line into a wire tree.
name name
Switching line into a wire tree.
name
Bi-directional line (e.g. SDA) into a wire tree.
name
Signal line into a wire tree, its direction depends on the circuit (e.g. ingoing for PDP, outgoing for LCD sets).
Remarks:
• When there is a black dot on the “signal direction arrow” it is an SRP symbol, so there will be a reference to the signal
name in the SRP list.
• All references to normal grounds (Ground symbols without additional text) are not listed in the reference list, this to keep
it concise.
•
Signals that are not used in multiple schematics, but only once or several times in the same schematic, are included in the SRP reference list, but only with one reference.
Additional Tip:
When using the PDF service manual file, you can very easily search for signal names and follow the signal over all the schematics. In Adobe PDF reader:
• Select the signal name you
want to search for, with the “Select text” tool.
• Copy and paste the signal name in the “Search PDF” tool.
• Search for all occurrences of the signal name.
• Now you can quickly jump between the different occurrences and follow the signal over all schematics. It is advised to
“zoom in” to e.g. 150% to see clearly, which text is selected. Then you can zoom out, to get a
n overview of the complete
schematic.
PS. It is recommended to use at least Adobe PDF (reader) version 6.x, due to better search possibilities in this version.
10000_031_090121.eps
100323
Net Name Diagram
+12-15V AP1 (4x) +12-15V AP4 (4x) +12-15V AP5 (12x) +12-15V AP6 (4x) +12-15V AP7 (8x) +12V AP1 (4x) +12V_NF AP1 (2x) +12VAL AP1 (2x) +25VLP AP1 (4x) +25VLP AP2 (1x) +3V3-STANDBY AP5 (3x) +400V-F AP1 (2x) +400V-F AP2 (2x) +400V-F AP3 (2x) +5V2 AP1 (6x) +5V2 AP2 (1x) +5V2-NF AP1 (1x) +5V2-NF AP2 (1x) +5V-SW AP1 (6x) +5V-SW AP2 (1x) +8V6 AP1 (3x) +AUX AP1 (2x) +AUX AP2 (1x) +DC-F AP1 (2x) +DC-F AP3 (2x) +SUB-SPEAKER AP5 (1x) +SUB-SPEAKER AP6 (2x)
-12-15V AP1 (4x)
-12-15V AP4 (6x)
-12-15V AP5 (14x)
-12-15V AP6 (6x)
-12-15V AP7 (8x) AL-OFF AP1 (2x) AUDIO-L AP4 (1x) AUDIO-L AP5 (1x) AUDIO-PROT AP5 (3x) AUDIO-R AP4 (1x) AUDIO-R AP5 (1x) AUDIO-SW AP5 (1x) AUDIO-SW AP7 (1x) BOOST AP1 (2x) CPROT AP4 (2x) CPROT AP5 (1x) CPROT-SW AP5 (1x) CPROT-SW AP6 (2x)
-DC-F AP1 (2x)
-DC-F AP3 (2x) DC-PROT AP1 (1x) DC-PROT AP5 (2x) DIM-CONTROL AP1 (2x) FEEDBACK+SW AP6 (2x) FEEDBACK-L AP4 (2x) FEEDBACK-R AP4 (2x) FEEDBACK-SW AP6 (2x) GND-AL AP1 (2x) GNDHA AP1 (40x) GNDHA AP2 (20x) GNDHA AP3 (2x) GNDHOT AP3 (2x) GND-L AP1 (2x) GND-L AP4 (4x) GND-L AP5 (34x) GND-LL AP4 (7x) GND-LL AP5 (1x) GND-LR AP4 (7x) GND-LR AP5 (1x) GND-LSW AP5 (1x) GND-LSW AP6 (15x) GND-S AP1 (11x) GND-SA AP4 (
8x) GND-SA AP5 (2x) GND-SA AP6 (8x) GND-SA AP7 (6x) GNDscrew AP3 (2x) GNDscrew AP5 (2x) GND-SSB AP5 (3x) GND-SSP AP1 (51x) GND-SSP AP2 (15x) IN+SW AP6 (2x) IN-L AP4 (2x) IN-R AP4 (2x) IN-SW AP6 (2x) INV-MUTE AP4 (1x) INV-MUTE AP5 (1x) INV-MUTE AP6 (1x) LEFT-SPEAKER AP4 (1x) LEFT-SPEAKER AP5 (1x) MUTE AP4 (2x) MUTE AP5 (1x) MUTE AP6 (2x) ON-OFF AP1 (3x) OUT AP6 (1x) OUT AP7 (2x) OUTN AP6 (1x) OUTN AP7 (1x) POWER-GOOD AP1 (2x) POWER-OK-PLATFORM AP1 (2x) RIGHT-SPEAKER AP4 (1x) RIGHT-SPEAKER AP5 (1x)
SOUND-ENABLE AP5 (3x) STANDBY AP1 (5x) STANDBY AP2 (1x)
-SUB-SPEAKER AP5 (1x)
-SUB-SPEAKER AP6 (2x) V-CLAMP AP1 (1x) V-CLAMP AP3 (2x)
Personal Notes:
Circuit Diagrams and PWB Layouts
EN 65LC10.1L LA 10.
2010-Apr-06
Page 66

SSB: SRP List

18980_520_100329.eps
100329
2010-01-22
1
3139 123 6483
SRP LIST PART 1
Netname Diagram
+12VDISP B02A (1 ×) +12VDISP B05 (1 ×) +12VS B02A (3 ×) +12VS B04A (2 ×) +12VS B04D (1 ×) +12VS B06C (2 ×) +12VS B08A (1 ×) +12VS_1 B02A (2 ×) +1V0_SW B02A (1 ×) +1V0_SW B04B (1 ×) +1V2_SW B02A (1 ×) +1V2_SW B03 (2 ×) +1V2_SW B04B (2 ×) +1V8_SW B02A (1 ×) +1V8_SW B04B (1 ×) +1V8_SW B04C (5 ×) +24VAUDIO B02A (1 ×) +24VAUDIO B04A (2 ×) +2V5_SW B03 (3 ×) +3V3_SW B02A (1 ×) +3V3_SW B03 (5 ×) +3V3_SW B04B (3 ×) +3V3_SW B04D (25 ×) +
3V3_SW B06B (2 ×) +3V3_SW B06C (2 ×) +3V3STBY B02A (1 ×) +3V3STBY B04A (3 ×) +3V3STBY B04B (2 ×) +3V3STBY B04D (10 ×) +3V3STBY B05 (1 ×) +3V3STBY B06A (2 ×) +3V3STBY B08A (1 ×) +5V B04D (1 ×) +5V_SW B02A (1 ×) +5V_SW B02B (1 ×) +5V_SW B03 (1 ×) +5V_SW B04A (1 ×) +5V_SW B04D (6 ×) +5V_SW B05 (1 ×) +5V_SW B06A (2 ×) +5V_SW B06E (1 ×) +5V_SW B07 (1 ×) +5V_SW B08A (1 ×) +5V5_TUN B02A (1 ×) +5V5_TUN B02B (1 ×) +5VIF B02B (4 ×) +5VS B02B (2 ×) +5VTUN_DIGITAL B02B (2 ×) +VDISP B08C (4 ×) +VDISP B0
8D (1 ×) +VDISP B08E (2 ×) +VDISP-INT B05 (2 ×) +VDISP-INT B08C (1 ×) 50Hz_60Hz B08B (1 ×) 50Hz_60Hz B08D (1 ×) 5V B06E (1 ×) A_STBY B04A (1 ×) AGND B02B (46 ×) AGND B03 (17 ×) AIN0_L B06C (1 ×) AIN0_L-AV1 B06C (1 ×) AIN0_L-AV1 B06D (1 ×) AIN0_R B06C (1 ×) AIN0_R-AV1 B06C (1 ×) AIN0_R-AV1 B06D (1 ×) AIN1_L B06C (1 ×) AIN1_L-AV2 B06C (1 ×) AIN1_L-AV2 B06D (1 ×) AIN1_R B06C (1 ×) AIN1_R-AV2 B06C (1 ×) AIN1_R-AV2 B06D (1 ×) AOUTL B04A (2 ×) AOUTL B06C (1 ×) AOUTR B04A (2 ×) AOUTR B06C (1 ×) ASIC_CS1 B08B (1 ×) ASIC_CS1 B08E (1 ×) ASIC_CS11 B08B (1 ×)
ASIC_CS11 B08E (1 ×) ASIC_CS3 B08B (1 ×) ASIC_CS3 B08E (1 ×) ASIC_CS5 B08B (1 ×) ASIC_CS5 B08E (1 ×) A
SIC_CS7 B08B (1 ×) ASIC_CS7 B08E (1 ×) ASIC_CS9 B08B (1 ×) ASIC_CS9 B08E (1 ×) ASPDIF_OUT B06C (1 ×) BACKLIGHT-BOOST B02A (1 ×) BACKLIGHT-BOOST B04D (1 ×) BACKLIGHT-PWM B02A (1 ×) BACKLIGHT-PWM B04D (2 ×) BP B06C (1 ×) BP B07 (1 ×) BYPASS_MODE B04D (1 ×) BYPASS_MODE B08D (1 ×) CS_L B08D (1 ×) CS_L B08E (1 ×) CS1 B08E (2 ×) CS10 B08E (2 ×) CS11 B08E (2 ×) CS12 B08E (2 ×) CS2 B08E (2 ×) CS3 B08E (2 ×) CS4 B08E (2 ×) CS5 B08E (2 ×) CS6 B08E (2 ×) CS
7 B08E (2 ×) CS8 B08E (2 ×) CS9 B08E (2 ×) CVBS_AV3 B06C (1 ×) CVBS_AV3 B06D (1 ×) CVBS_RF B02B (1 ×) CVBS_RF B06C (1 ×) DC_5V B07 (4 ×) DC_PROT B04A (1 ×) DC_PROT B04D (1 ×) DDC_RESET B04D (1 ×) DDC_RESET B06A (1 ×) DDR2VDD B08B (4 ×) DGND B03 (32 ×) DIF_N B02B (1 ×) DIF_N B03 (1 ×) DIF_P B02B (1 ×) DIF_P B03 (1 ×) DVI_AUL_IN B06C (1 ×) DVI_AUR_IN B06C (1 ×) EDID_WC B04D (1 ×) EDID_WC B06A (1 ×) EDID_WC B07 (1 ×) FE_SCL B02B (1 ×) FE_SCL B03 (1 ×) FE_SDA B02B (1 ×) FE_SDA B0 3 (1 ×) GCK B08B (1 ×) GN B06C (1 ×) GN B07 (1 ×) GND_CVBS B06C (1 ×) GND_CVBS B06D (1 ×) GND-AUDIO B02A (4 ×) GND-AUDIO B04A (13 ×) GOE B08B (1 ×) GP B06C (1 ×) GP B07 (1 ×) GSLOP B08B (1 ×) GSLOP B08C (2 ×) GSP1 B08B (1 ×) GSP2 B08B (1 ×) HDMI_CEC B04D (1 ×) HDMI_CEC B06A (1 ×) HDMI_PLUGPWR1 B06A (4 ×) HDMI_PLUGPWR2 B06A (4 ×) HP_DET B04D (1 ×) HP_DET B06B (1 ×) HP_DETECT B04D (1 ×) HP_LOUT B04A (1 ×) HP_LOUT B06B (1 ×) HP_ROUT B04A (1 ×)
HP_ROUT B06B (1 ×) HPOUTL B06B (1 ×) HPOUTL B06C (1 ×) HPOUTR B06B (1 ×) HPOUTR B06C (1 ×) HSYNC B06C (1 ×) HSYNC B07 (1 ×) IF_AGC B02B (1 ×) IF_AGC B03 (1 ×) IF_AGC B04D (1 ×) IF_ATV B02B (2 ×) INNCOM B08D (2 ×) JTCK B04D (2 ×) JTDI B04D (2 ×) JTDO B04D (2 ×) JTMS B04D (2 ×) JTRST B04D (2 ×) KEYBOARD B04D (2 ×) LAMP-ON B02A (1 ×) LAMP-ON B04D (1 ×) LCD-PWR-ONn B04D (1 ×) LCD-PWR-ONn B05 (1 ×) LED-1 B04D (2 ×) LED-2 B04D (1 ×) LEFT_SPEAKER B04A (2 ×) LIGHT-SENSOR B04D (2 ×) LS B08B (1 ×) MUTE B04A (1 ×) MUTE B04D (1 ×) NAND_PALE B04D (1 ×) NAND_PARB B04D (1 ×) NAND_PCLE B04D (1 ×) NAND_PDD(0) B04D (1 ×) NAND_PDD(1) B04D (1 ×) NAND_PDD(2) B04D (1 ×) NAND_PDD(3) B04D (1 ×) NAND_PDD(4) B04D (1 ×) NAND_PDD(5) B04D (1 ×) NAND_PDD(6) B04D (1 ×) NAND_PDD(7) B04D (1 ×) NAND_POCE B04D (1 ×) NAND_POOE B04D (1 ×) NAND_POWE B04D (1 ×) OUTCOM B08D (2 ×) PB0P B06C (1 ×) PBS_HPL B06B (1 ×) PBS_HPL B08A (1 ×) PBS_HPR B06B (1 ×) PBS_HPR B08A (1 ×) PBS_SPI_CLK B04D (1 ×) PBS_SPI_CLK B08A (1 ×) PBS_SPI_DI B04D (1 ×) PBS_SPI_DI B08A (1 ×) POWER_DOWN B04D (1 ×) POWER-OK B02A (1 ×) POWER-OK B04D (1 ×) PR0P B06C (1 ×) PREAMPL B06C (1 ×) PREAMPR B06C (1 ×) PWR5V_1 B06A (1 ×) PWR5V_2 B06A (1 ×) PX1A- B05 (1 ×) PX1A- B06A (1 ×) PX1A- B08B (1 ×) PX1A+ B05 (1 ×) PX1A+ B06A (1 ×) PX1A+ B08B (1 ×) PX1B- B05 (1 ×) PX1B- B06A (1 ×) PX1B- B08B (1 ×) PX1B+ B05 (1 ×) PX1B+ B06A (1 ×) PX1B+ B08B (1 ×) PX1C- B05 (1 ×) PX1C- B06A (1 ×) PX1C- B08B (1 ×) PX1C+ B05 (1 ×) PX1C+ B06A (1 ×) PX1C+ B08B (1 ×) PX1CLK- B05 (1 ×)
PX1CLK- B06A (1 ×) PX1CLK- B08B (1 ×) PX1CLK+ B05 (1 ×) PX1CLK+ B06A (1 ×) PX1CLK+ B08B (1 ×) PX1D- B05 (1 ×) PX1D- B06A (2 ×) PX1D- B08B (1 ×) PX1D+ B05 (1 ×) PX1D+ B06A (1 ×) PX1D+ B08B (1 ×) PX1E- B05 (1 ×) PX1E- B06A (1 ×) PX1E- B08B (1 ×) PX1E+ B05 (1 ×) PX1E+ B06A (1 ×) PX1E+ B08B (1 ×) PX2A- B05 (1 ×) PX2A- B06A (1 ×) PX2A- B08B (1 ×) PX2A+ B05 (1 ×) PX2A+ B06A (1 ×) PX2A+ B08B (1 ×) PX2B- B05 (1 ×) PX2B- B06A (1 ×) PX2B- B08B (1 ×) PX2B+ B05 (1 ×) PX2B+ B06A (1 ×) PX2B+ B08B (1 ×) PX2C- B05 (1 ×) PX2C- B06A (1 ×) PX2C- B08B (1 ×) PX2C+ B05 (1 ×) PX2C+ B06A (1 ×) PX2C+ B08B (1 ×) PX2CLK- B05 (1 ×) PX2CLK- B06A (1 ×) PX2CLK- B08B (1 ×) PX2CLK+ B05 (1 ×) PX2CLK+ B06A (1 ×) PX2CLK+ B08B (1 ×) PX2D- B05 (1 ×) PX2D- B06A (2 ×) PX2D- B08B (1 ×) PX2D+ B05 (1 ×) PX2D+ B06A (1 ×) PX2D+ B08B (1 ×) PX2E- B05 (1 ×) PX2E- B06A (1 ×) PX2E- B08B (1 ×) PX2E+ B05 (1 ×) PX2E+ B06A (1 ×) PX2E+ B08B (1 ×) R_L B08B (1 ×) R_L B08D (1 ×) RC B04D (1 ×) RC1 B04D (1 ×) RC1 B06B (1 ×) RC1 B08A (1 ×) RC2 B04D (1 ×) RC2 B06B (1 ×) RC2 B08A (1 ×) RESET_DEMOD B03 (1 ×) RESET_DEMOD B04D (1 ×) REV B08B (1 ×) RF_AGC B02B (2 ×) RF_AGC B04D (1 ×) RF_AGC_SW B02B (1 ×) RF_AGC_SW B04D (1 ×) RIGHT_SPEAKER B04A (2 ×) ROM_S
CL B08B (1 ×) ROM_SCL B08D (1 ×) ROM_SDA B08B (1 ×) ROM_SDA B08D (1 ×) RP B06C (1 ×) RP B07 (1 ×)
SAV_L_IN B06C (1 ×) SAV_L_IN B06D (1 ×) SAV_R_IN B06C (1 ×) SAV_R_IN B06D (1 ×)
SCL_VGA B07 (1 ×) SCL_VGA B08D (1 ×) SCL-DISP B04D (1 ×) SCL-LCD B04D (1 ×) SCL-LCD B08A (1 ×) SCL-MAIN B04D (4 ×) SCL-MAIN1 B04D (1 ×) SCL-MAIN1 B08A (1 ×) SCL-TCON B08B (1 ×) SCL-TCON B08D (4 ×) SDA_VGA B07 (1 ×) SDA_VGA B08D (1 ×) SDA-DISP B04D (1 ×) SDA-LCD B04D (1 ×) SDA-LCD B08A (1 ×) SDA-MAIN B04D (4 ×) SDA-MAIN1 B04D (1 ×) SDA-MAIN1 B08A (1 ×) SDA-TCON B08B (1 ×) SDA-TCON B08D (4 ×) SELLVDS B08B (1 ×) SELLVDS
B08D (1 ×) SENSE+1V0_MT5363 B02A (1 ×) SENSE+1V0_MT5363 B04B (1 ×) SGND1 B08C (15 ×) SIF_OUT B02B (1 ×) SIF_OUT B06C (1 ×) SIF_OUT_GND B02B (1 ×) SIF_OUT_GND B06C (1 ×) SOG B06C (1 ×) SOG B07 (1 ×) SOY0 B06C (1 ×) SPB0P B06C (1 ×) SPB0P B06D (1 ×) SPB1P B06C (1 ×) SPB1P B06D (1 ×) SPR0P B06C (1 ×) SPR0P B06D (1 ×) SPR1P B06C (1 ×) SPR1P B06D (1 ×) STANDBY B02A (1 ×) STANDBY B04D (1 ×) STANDBYn B04D (1 ×) SW_MUTE B04A (1 ×) SW_MUTE B04D (1 ×) SY0N B06C (1 ×) SY0N B06D (1 ×) SY0P B06C (1 ×) SY0P B06D (1 ×) SY1N B06C (1 ×) SY1N B06D (1 ×) SY1P B06C (1 ×) SY1P B06D (1 ×)
TSO_CLK B03 (1 ×) TSO_CLK B04D (1 ×) TSO_DATA0 B03 (1 ×) TSO_DATA0 B04D (1 ×) TSO_SYNC B03
(1 ×) TSO_SYNC B04D (1 ×) TSO_VALID B03 (1 ×) TSO_VALID B04D (1 ×) TUNER_SCL B02B (1 ×) TUNER_SCL B03 (1 ×) TUNER_SCL B04D (1 ×) TUNER_SDA B02B (1 ×) TUNER_SDA B03 (1 ×) TUNER_SDA B04D (1 ×) U_D B08B (1 ×) U_D B08D (1 ×) U_D_INV B08B (1 ×) UART_RX B04D (2 ×) UART_TX B04D (2 ×) USB_DM B04D (1 ×) USB_DM B06E (1 ×) USB_DP B04D (1 ×) USB_DP B06E (1 ×) USB_OCP B04D (1 ×) USB_OCP B06E (1 ×) USB_PWR_EN B04D (1 ×) USB_PWR_EN B06E (1 ×)
VCC_3V3 B08B (4 ×) VCC_3V3 B08C (3 ×) VCC_3V3 B08D (8 ×) VCC1V8 B08B (4 ×) VCC1V8 B08C (1 ×) VCOM B08D (1 ×) VCOM B08E (1 ×) VDD1V8 B08B (2 ×) VDD1V8PLL B08B (2 ×) VDD3V3IO B08B (2 ×) VDD3V3LV RS B08B (2 ×) VGH_35V B08B (1 ×) VGH_35V B08C (1 ×) VGL_-6V B08C (2 ×) VH0 B08D (1 ×) VH127 B08D (3 ×) VH159 B08D (1 ×) VH191 B08D (1 ×) VH247 B08D (1 ×) VH255 B08D (1 ×) VH31 B08D (2 ×) VH63 B08D (2 ×) VH95 B08D (2 ×) VIF1 B02B (2 ×) VIF2 B02B (2 ×) VL0 B08D (1 ×) VL127 B08D (3 ×) VL159 B08D (1 ×) VL191 B08D (1 ×) VL247 B08D (1 ×) VL
31 B08D (2 ×) VL63 B08D (2 ×) VL95 B08D (2 ×) VLS_15V6 B08C (3 ×) VLS_15V6 B08D (4 ×) VLS_15V6_B B08C (2 ×) VREF_15V2 B08D (1 ×) VREF_15V2 B08E (1 ×) VSYNC B06C (1 ×) VSYNC B07 (1 ×) WP_TCON B08D (1 ×) Y0N B06C (1 ×) Y0P B06C (1 ×)
Circuit Diagrams and PWB Layouts
EN 66LC10.1L LA 10.
2010-Apr-06
Page 67

IR/LED Board

18980_530_100329.eps
100329
IR/LED board
J J
2009-12-09
1
YKJ2035
IR/LED
VSS
+3.3V
+3.3V
+5V
LED2
LED2
LED1
R9
10kΩ
IR
IR
R12
47Ω
VSS
R3
100Ω
R4
6.8kΩ
R6
0Ω
VSS
+3.3V
VSS
+3.3V
C1
10μF
LIGHT1
2
3
4
5
6
7
8
J1
2.0- 8pin
1
2
3
J2
2.0- 3pin
RED
R10
10kΩ
D2
B
2
C
1
E
3
Q2*
BC847
GND
1
GND
2
OUT
3
VD D
4
U1
IRM -H636
Keyboard
Keyboard
VSS
Circuit Diagrams and PWB Layouts
EN 67LC10.1L LA 10.
2010-Apr-06
Page 68

Layout IR/LED Board

18970_531_100323.eps
100323
2009-12-09
1
YKJ2035
IR/LED
XXXXXX-X0001 12NC
Layout IR/LED Board (Top Side)
Layout IR/LED Board (Bottom Side)
Circuit Diagrams and PWB Layouts
EN 68LC10.1L LA 10.
2010-Apr-06
Page 69

Keyboard Control Board

18980_540_100329.eps
100329
Keyboard Control Board
E E
2009-09-10
1
SF2035/SF2037
SIDE CONTROL
+3.3V
R6
5.6kΩ
VSS
C2
103
R8
8.2kΩ
R5
3.9kΩ
R4
1.5kΩ
R7
18kΩ
CH+
VSS
CH−
VSS
HOME
VSS
VOL+
VSS
VOL−
VSS
POWER
VSS
VSS
1
2
3
J1
CON3
Circuit Diagrams and PWB Layouts
EN 69LC10.1L LA 10.
2010-Apr-06
Page 70

Layout Keyboard Control Board

18970_541_100323.eps
100323
2009-09-10
1
SF2035/SF2037
SIDE CONTROL
Layout Keyboard Control Board
Circuit Diagrams and PWB Layouts
EN 70LC10.1L LA 10.
2010-Apr-06
Page 71

11. Styling Sheets

18980_800_100329.eps
100329
DALI 32"- 40"
Pos No. Description Remarks
0004 Front Cabinet 0012 Back Cover 0021 I/O Bracket Side 0024 I/O Bracket Bottom 0045 Speaker bracket 0260 Stand 1085 Remote Control Not displayed
FOR ELECTRICAL PARTS/ASSEMBLIES SEE WIRING DIAGRAM CHAPTER 9
0004
0260
0012
0021
0024
0045

Styling Sheet Dali 32" - 40"

Styling Sheets
EN 71LC10.1L LA 11.
2010-Apr-06
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