PassLabs Aleph 0-S Service manual

Aleph 0s Service Manual Version 1.0 - 1.3
PRODUCT DESCRIPTION
The Aleph 0s is a high performance Mosfet single-ended Class A stereo audio power

amplifier, intended for maximum performance in reproduction of music. It is a simple design,
having only three gain stages: input differential pair, cascoded voltage gain stage, and
output followers. All three gain stages are biased by constant current sources from the
negative supply. The output stage will operate as a single ended class A system at lower
power levels and will operate as a push-pull class A system at levels above the bias point of
the constant current source.

SIMPLIFIED SCHEMATIC
To best understand the operation of the amplifier, refer to the simplified schematic Figure 1.

The front end of the amplifier accepts a balanced or unbalanced input signal at two N
channel Mosfets operating as a differential pair. They are provided with bias by a current
source from the negative rail which operates at a constant 8 milliamps. The output of the
differential pair drives a P channel Mosfet which provides voltage and current gain. At the
output of this second stage you will see the full voltage swing of the amplifier.

This second gain stage is provided with a single-ended Class A current bias from another
current source from the negative supply which provides a constant 30 milliamps current.
Between the current source and the drain of the P channel device is a constant voltage
source which is used to provide voltage bias to the output Mosfet transistors.

The amplifier has complementary N and P channel output transistors operated as source
followers, so that they provide only current gain. High current single ended Class A bias is
provided by yet another constant current source from the negative supply. This current
source provides greater than 1 amp of constant current per channel

COMPLETE SCHEMATIC
For purposes of clarity and simplicity, the complete schematic of the Aleph 0s is broken up

into the following sections: Power supply, Front end, and Output Stage.
Figure 2 shows the power supply schematic. An IEC standard AC line connector connects to

the primary of a toroidal power transformer through an inrush suppression thermistor, fast
blow fuse, a power switch, and a thermostat. Fig 2 shows the transformer wired for 120
VAC, and the transformer can be adapted to 240 VAC by connecting the two primary
windings in series. 100 volt operation requires a special transformer.

The secondary system consists of a bridge rectifier and four 31,000 uF capacitors. The
secondary DC voltage is approximately plus and minus 40 volts. The front end circuitry of
the amplifier is decoupled from the main supply by RC filters.

Figure 3 shows one half of the output stage. Both halves run exactly in parallel.

1

2

3

4

RevNumber

DCBA

1.3

.33

G

S

IRF244

221

R203

221

R204

R206

Q204

MPSA42

C201

4.7

ALEPH 0S OUTPUT STAGE (1/2)

Title

SizeADate

D

Q202

47.5K

R205

.33

R207

ofSheet

Drawn by

PL10OS10.S01

10/10/93 PASS

Filename

V+

Q201

R201

IRF244

221

+D

9.1V

Z201

OUT

R208

9.1V

Z202

Q203

IRF9240

R202

-D

221

ISD

V-

A B C D

1

2

3

4

Following are the front end circuits and PC board component placements for Revision
numbers 1.0 through 1.3. All are very similar, and while the following description applies
specifically to Rev 1.0, the comments apply to all versions.

The circuit formed by Q101, Z102, R108 and R107 is a constant current source designed to
bias Z101, the voltage reference for the front end constant current sources, and Q7, the
voltage gain stage cascode transistor. This current source and reference circuit is common
to both channels. Further references are to each channel singly, with both channels having
identical circuits and part references.

Q3 and Q4 are constant current sources which bias the front end. They are driven by Z101
at 9.1 volts, resulting in approximately 4.5 volts across their source resistors, R3 and R10,
giving approximately 8 ma and 30 ma constant current.

The input differential transistors Q1 and Q2 are power Mosfet transistors which have been
matched to .01 volts threshold voltages at 4 milliamps current. The gates of these devices
are connected to differential networks formed by R5, 6, 13-18. These form a true differential
amplifier for balanced input and can be operated unbalanced by simply driving the positive
input (XLR pin 2) with or without shorting the negative input (XLR pin 3) to ground. Shorting
the negative input to ground provides twice the voltage gain over leaving it unterminated,
but either method of operation is acceptable.

Zener diodes Z1 and 2 protect the input transistors from outside transient voltages. Q1
drives Q6 in common source mode which is in cascode (common gate) connection with Q7.
At the same time, Q2 drives the source of Q7 in a folded cascode connection, so that both
input transistors drive the secondary gain stage. The DC offset point of this system is set by
P1.

While the amplifier is primarily biased by the output stage constant current source, the
design provides for "pull" operation beyond the constant current bias point with a set of P
channel source followers. The bias relation between the P and N channel source follower
output devices is set by the constant voltage circuit of Q5 and adjusted by P2. Normally, the
P channel output stage will be biased at about 10% of the value of the constant current
source, or about 100 ma.

C5 provides 10 picofarads of forward compensation in the feedback loop. C6 provides 39 pf
of compensation for Q6.

Z3 provides protection for the gate of Q7 when Q6 is shut down on a negative waveform
clip. Q8 provides current limiting for Q6 during a positive waveform clip.

R1 and C7 provide loading at radio frequencies. If R1 is damaged, it is a sure sign of high
power at high frequencies, such as full power at 100 KHz or Square waves above 20 KHz.
Unless it is on a test bench, the only way the amplifier will experience this will be in system
oscillation, where the output of the amplifier is allowed to bleed back to the input. This is
generally due to wiring fault in the system.

1

2

3

4

RevNumber

+DRIVE

DCBA

OUTPUT

C7

.047

C4

390PF

C3

-DRIVE

R1

2.7

GND

ALEPH 0S FRONT END

390PF

ofSheet

PASS

Drawn by

D

PL10FE.S01

12/13/93

B

Title

Size

Date

Filename

Q5

C8

V-

4.7UF
150

R3

Q4

V+

R2

4.75

Q6

Q7

221

MPSA92

4.75K

R109

9.1V

Z102

2.2K

IRFD9210

R7

Q8

39PF

C6

9.1V

Z3

MPSA92

R108

IRF9510

R8

Q101

4.75K

221

R107

15K

CCW

7.5K

R12

Q2

IRFD210

P2

W

IRFD210

5K

GND

C

C5

W

9.1V

Z2

10PF

R18

100K

Q3

R4

R9

IRF610

221

9.1V

Z101

221

680

IRF610

R10

CCW

R11

5K

P1

W

50K

T1

C

W

THERMISTOR

R13

4.75KR5

Q1

IRFD210

4.75K

9.1V

Z1

4.75K

R16

100K

R17

+

R14

4.75K

R15

390PF

C2

390PF

C1

B C

A

R6

221

- INPUT

1

2

221

+ INPUT

3

4