For standard GSM Fl(n)=890+0.2*n 1 ≤n≤ 124 Fu(n)=Fl(n)+45
890 MHz ~915 MHz : Mobile Transmit,Base receive
935 MHz ~960 MHz : Base Transmit, Mobile receive
For Extended GSM Fl(n)=890+0.2*n 1 ≤n≤ 124 Fu(n)=Fl(n)+45
Fl(n)=890+0.2*(n-1024) 975 ≤n≤ 1023
880 MHz ~915 MHz : Mobile Transmit,Base receive
925 MHz ~960 MHz : Base Transmit, Mobile receive
For DCS Band Fl(n)=1710.2+0.2*(n-512) 512 ≤n≤ 885 Fu(n)=Fl(n)+95
1710 MHz ~1785 MHz : Mobile Transmit,Base receive
1805 MHz ~1880 MHz : Base Transmit, Mobile receive
SECTION 1. Introduction
1.1 An Introduction of GSM Digital Cellular Mobile Communication System
GSM (Global System for Mobile communication) concluded that digital technology working in
the Time Division Multiple Access (TDMA) mode would provide the optimum solution for the
future system. Specifically , a TDMA system has the following advantage
► Offers a possibility of channel splitting and advanced speech coding ,resulting in improved
spectrum efficiency.
► Offers much greater variety of service than the analog
► Allows considerable improvements to be made with regards to the protection of information.
The GSM system is basically designed as a combination of three major subsystem;
The network subsystem, the radio subsystem, and the operation support system.
The functional architecture of a GSM system can be divided into the Mobile Station (MS), the Base
Station (BS), and the Network Subsystem (NS). The MS is carried by the subscriber, the BS
subsystem controls the radio link with the MS and the NS performs the switching of calls between
the mobile and other fixed or mobile network users as well as mobility management. The MS and
the BS subsystem communicate across the Um interface also known as radio link
The specifications relating to MS are as follows:
TS 100 607-1 : Digital cellular telecommunication system(Phase2+)Mobile Station (MS)
Transmit frequency band : 880 MHz ~ 915 MHz(For EGSM) , 1710 MHz ~ 1785 MHz(For DCS)
Receive frequency band: 925 MHz ~ 960 MHz(For EGSM) , 1805 MHz ~ 1880 MHz(For DCS)
Channel spacing : 200 KHz
ARFCN(Absolute Radio Frequency Channel Number) : 1~124 and 975~1023 (For EGSM),
512~885 (For DCS)
Transmit·receive frequency spacing: 45 MHz
Frequency band and Channel Arrangement
PANTECH R&D CONFIDENTIAL
Zeron Service Manual
4
** Fl(n)= frequency value of the carrier , Fu(n)= corresponding frequency value in upper band
1.3 Item Name and Usage
Zeron, GSM digital cell phone, is supercompact, superlight mobile communication terminal for
personal use. It has a 900MHz and 1800MHz frequency band and adopts GSM and DCS mode
having excellent spectrum efficiency, economy, and portability.
This product is GSM Cellular type portable phone, adopting 1-cell Li-ion battery and power saving
circuit to maximize its operation time. Also, it is equipped with a fixed antenna and its color LCD with
font built in enables both Chinese and English text service. And power control(basic feature of GSM),
security feature, voice symbol feature, and variable data rate feature are used appropriately to
ensure its best performance. This product consists of a handset, battery pack, and Travel charger.
1.4 Characteristics
1) All the active devices of Zeron are made of semiconductors to ensure excellent performance and
semi-permanent use.
2) Surface mounting device (SMD) is used to ensure high reliability, compactness and lightness.
3) The Zeron’s RF Cirsuit consists of SPR module(SKY74073) which Transceiver is fully intergrated
transceiver ,PA ,PA control circuitry,anttena switch,diplexer,transmit harmonic filter, and SAW
filters, external crystal oscillator and Rf switch connector.
4) Zeron is designed to perform excellently even in the worst environment
PANTECH R&D CONFIDENTIAL
Zeron Service Manual
5
Mobile Transmit Frequency
880 MHz ~ 915 MHz/1710MHz ~ 1785MHz
Mobile Receive Frequency
925 MHz ~ 960 MHz/1805MHz ~ 1880MHz
The Number of Time Slot
8
The Number of Channels
174/375
Channel Spacing
200 kHz
Power Supply
Rechargeable Li-Ion Battery 3.7V/680mAh
Operating Temperature
-10℃∼ +55℃
Dimension
Weight
Maximum Output Power
33±2 / 30±2 dBm
Frequency Error
±90Hz/±180Hz
Phase Error
RMS < 5°, PEAK < 20°
Minimum Output Power
5±5 / 0±5 dBm
Power Control
5~19(2 dB Step)/0~15(2 dB Step)
Output RF Spectrum
TS 100 910V6.2.0
Switching Transient
TS 100 910V6.2.0
Intermodulation attenuation
Conducted Spurious Emissions
Idle Mode
-57dBm 9KHz~880M/915MHz~1GHz
-59dBm 880MHz~915MHz
-53dBm 1.7~1.785GHz
-47dBm 1~1.715GHz/1.785GHz~12.75GHz
Allocated Channel
-36dBm 9KHz~ 1GHz
-30dBm 1GHz~ 12.75GHz
Reference Sensitivity
For GSM900 small MS :-102dBm
For DCS1800 class3 MS : -102dBm
For Adjacent interference
For Adjacent(200KHz) interference
For Adjacent(400KHz) interference
For Adjacent(600KHz) interference
C/Ic
9 dB
C/Ia1
-9 dB
C/Ia2
-41 dB
C/Ia3
-49 dB
Section 2. Electrical Specifications
2.1 General E-GSM / DCS Band
2.2 Transmitter E-GSM / DCS Band
2.3 Receiver
PANTECH R&D CONFIDENTIAL
Zeron Service Manual
6
Antenna
Two-mode
Speaker
Display
Screen
MIC
Section 3 Operation
3.1 Name of each part
PANTECH R&D CONFIDENTIAL
Zeron Service Manual
7
Parameter
Projected Actual (MAIN LCD)
Display
Color TFT LCD with white LED back lighting
262,144 colors
European Character : (font size : 1616) 6 lines x 16
characters
Chinese Character : (font size : 1616) 6 lines 7
characters
Driver
PD161928P (NEC)
Module Dimen.
33.2(H) x 52.9(V) x 5.3(D)
Effective display
area
24.58(H) x 27.46(V) (Diagonal:1.5inch)
Number of dots
128(H) x RGB(H) x 143(V)
Dot pitch
64um(H) x 192um(V)
Parameter
Projected Actual (SUB LCD)
Display
Color TFT LCD with white LED back lighting
262,144 colors
European Character : (font size : 715) 1 lines x 12
characters
Chinese Character : (font size : 1616) 1 lines 6
characters
Driver
S1D10605D03E000 (EPSON)
Module Dimen.
33.2(H) x 52.9(V) x 5.3(D)
Effective display
area
14.21(H) x 21.31(V) (Diagonal:1.0inch)
Number of dots
96(H) x RGB(H) x 64(V)
Dot pitch
74um(H) x 222um(V)
Market Goal
Projected Actual
Comments
English
Keypad
0-9, *,#
Send (Color)
End/Pwr (Color)
Up (Melody), Down
(Phonebook), Left
(Organizer), Right
(SMS),CENTER(WA
P),
MENU, OK, CLR
Accessary, Camera
* Key: Vib. Mode
# Key: Auto Lock
0/+Key: International
0-9, *,#
Send (Color)
End/Pwr (Color)
Up (Melody), Down
(Phonebook), Left
(Organizer), Right
(SMS),CENTER(WA
P),
MENU, OK, CLR
Accessary, Camera
* Key: Vib. Mode
# Key: Auto Lock
0/+Key: International
Applying battery voltage and pressing “END” key on the key pad short-circuits “Ground” and “_
PowerON”. ADP6535(U102) control that power manage regarding power on/off in handset
Pressing POWERKEY on the key pad is active on the handset.
This will turn on all the LDOs, when POWERKEY is held low. The power of RF Tx power amplifier is
supplied directly by the battery.
4.1.2 Logic part
4.1.2.1 Summary
The logic part consists of AD6526 ARM7 microprocessor-combined GSM-ASIC, COMBO(flash
ROM & SRAM), AD6535 VBC Chip. AD6526 is GSM-ASIC chipset implemented for GSM terminal’s
system control and baseband digital signal processing.
Major parts used in the logic part are as follows:
AD6526 is a GSM core device containing ARM7 CPU core. AD6526 is 160 pin LFBGA (mini-BGA)
package, consisting of terminal chips. The function and characteristics of clock are as follows:
1) Complete single chip GSM Processor
2) Channel codec sub-system
• Channel coder and decoder
• Interleaver and Deinterleaver
• Encryption and Decryption
3) Control Processor Subsystem including
• Parallel and serial Display interface
• Keypad Interface
• SIM Interface
• Control of RADIO subsystem
• Real Time Clock with Alarm
PANTECH R&D CONFIDENTIAL
Zeron Service Manual
10
☞ Configuration by Function of AD6526
1 Microprocessor Core
AD6526 has a built-in ARM7 microprocessor core, including microprocessor interrupt controller,
timer/counter, and DMA controller. And besides, 32bit data path is included, and up to 8Mbyte
addressing is enabled and can be extended up to 16Mbyte. Although external clock should be
provided to operate the microprocessor, this core uses 13MHz VCTCXO to provide clock.
2 Input Clock
1) Main Clock(13 MHz):
This is the clock needed for the microprocessor built in AD6526 to operate.
2) VC-TCXO(13 MHz) , 32.768KHz Clock:
This is the system reference clock to control SLEEP mode.
This is the clock derived from 13MHz VC-TCXO clock, provided by RF part. It is the timing
reference clock for GSM signal processing.
3 DSP Subsystem
This is a GSM signal processing part in GSM mode, consisting of speech transcoding and
Channel equalization as follows:
1) Speech transcoding
In full rate, the DSP receives the speech data stream from VBC and encodes data from 104kbps to
13kbps. Using algorithm is Regular Pulse Excitation with Long Term Prediction (RPE-LTP).
2) Equalization
The Equalizer recovers and demodulates the received signal
The Equalizer establishes local timing and frequency references for mobile terminal as well as
RSSI calculation.
The equlization algorithm is a version of Maximum Likelihood Sequency Estimation(MLSI)
using Viterbi Algorithm.
☞ GSM Core and RF Interface
1) Transmitter:
AD6535 VBC receive data at 270kbps and use an on chip lock-up table to perform GMSK
modulation. A pair of 10bit matched differential DACs convert the modulated data and pass
I and Q analog data to the transmit section of the radio system.
2) Receiver:
The receiver I and Q signals are sampled by a pair of ADCs at 270kbps.
The I and Q samples are transferred to the EGSMP through a dedicated receive path serial port.
4 RF Interface
This interfaces the RF part to control power amplifier, Tx LO buffer amplifier, VC-TCXO, and
AGC-end on transmit/receive paths in the RF part.
PANTECH R&D CONFIDENTIAL
Zeron Service Manual
11
1) Transmitter Interface:
This transmits TX_AGC signal to Tx AGC amplifier to adjust transmit power level and sends
Ramp_DAC signal to the RF part to control power amplifier.
2) Receiver Interface:
This transmits RX_AGC signal to Rx AGC amp. to adjust receive path gain.
5 General Purpose ADC Support
The AD6535 includes a general purpose 16bit auxiliary ADC with four multiplexed input channel
These are used for measurment of battery voltage ID , temperature and accessory ID.
6 USC(Universal System Connector) Interface
A Typical GSM handset requires serial connections to provide data during normal phone operation
manufacturing,testing and debugging.
7 General Purpose Interface
The AD6526 provides 32 interface pin for control of peripheral devices.
All GPIO pins start up as inputs. Additional purpose inputs and outputs are available under SW
control.
8 Speech Transcoding
In full rate mode, the DSP receive the speech data stream from the VBC and encodes data from
104kbps to 13kbps.Using algorithm is Regular Pulse Exitation with Long Term Prediction as
specified GSM Recommandation
9 Power Down Control Section
1) Idle Mode Control:
If IDLE/ signal turns ‘Low’, transmitter section becomes disabled.
2) Sleep Mode Control:
If IDLE/ and SLEEP/ signals turn ‘Low’, all the sections except for VC-TCXO circuit become
disabled.
3) Receiver & Transmitter Mode Control:
If IDLE/ and SLEEP/ signals turn ‘High’, all the sections become enabled to perform
transmit/receive operation.
4.1.3 Memory Part
Memory consists of COMBO (flash ROM & SRAM).
1 Flash ROM
Flash ROM has a capacity of 128Mbit(16MByte). The main programs of the terminal(call processing,
user interface, and diagnostic task) and supplemental programs (NAM program and test program)
are stored in the flash ROM. Even if the program version may be changed in the future, customers
can download the program.
2 Static RAM
SRAM has a capacity of 32Mbit(4MByte) and stores system parameters, data buffer, and stack of
each task in it.
PANTECH R&D CONFIDENTIAL
Zeron Service Manual
12
3 Key Tone Generation
All alert signals are generated by the DSP and output to the EVBC.
These alert can be used for the earpiece.
4.1.4 Notification Part
The notification of incoming call is given by melody, vibrator, and 7-color LED.
1) Melody:
This is a device sounding alert/melody tones.
The melody datas are stored in flash memory (U103) And generated by Melody IC(U104).
2) Vibrator:
This is a device enabling vibration. And generated by GPO23 of AD6526(U101).
3) 7-color LED :
This is a device to indicate a notification mode using the lamp.
U102 Nos. M15, M16 and L16 signal drives the lamp to flash
4.1.5 Key Pad Part
To enable key operation to input information, the key matrix is configured using strobe signal of
KEYPADROW(0-4) and 5 input ports of KEYPADCOL(0-4). Also, to use the key even at light, the
backlight circuit is provided for LED 17s.
4.1.6 LCD Module(Display Part)
LCD module consists of LCD, controller, LED-Backlight, and LCD reflector.using dual LCD
Main LCD: 1S/W Icon x 1 lines[(128x3)x160] can be displayed on the LCD panel. 6 icons could be
provided by S/W. Controller with English font built in has been used.
Sub LCD: 1S/W Icon x 1 lines(96x64) can be displayed on the LCD panel. 6 icons are provided.
Controller with English font built in has been used.
LED-backlight Using illuminates the LCD panel, and LCD reflector enhances LCD display effect.
4.1.7 Camera Sensor Module
Camera Sensor module is color CMOS VGA camera module.
Also, Camera Sensor module consist of Sensor, Lens, Flex cable, and Housing.
Module size is 8mm x 8mm x 5.73mm, and number of pixel is 326,688 pixels
PANTECH R&D CONFIDENTIAL
Zeron Service Manual
13
4.2 Radio Transceiver Section
The Zeron’s RF Cirsuit consists of SPR module(CX74073) which Transceiver is fully intergrated
transceiver ,PA ,PA control circuitry,anttena switch,diplexer,transmit harmonic filter, and SAW
filters, external crystal oscillator and Rf switch connector.
Fig.4-1. RF Transceiver block diagram
The receive path consists of a diplexer(which realizes a low-pass filter in the EGSM band and a
high-pass filter in the DCS band), transmit/receive (T/R) switch , saw filter,intergrated
LNA,quadrature demodulator section that performs direct down conersion and baseband
amplifer/filter circuitry
The trandmit path consists of the same diplexer and T/R switches as in the receive path, two low
pass filters for harmoics suppression(one for each band), a dual-band directional detector for the
PA control loop, and a dual-band PA. the transmit path also consists of a vectot modulator within a
translation loop architectur with intergrated high-power transmit oscillators for frequency
up-conversion The synthesizer section contains a fully intergrated on-chip oscillator locked in an
intergrated fractional-N synthesizer loop, The synthesizer is driven by the intergrated reference
crystal oscillator circuitry that uses an external crystal resonator
PANTECH R&D CONFIDENTIAL
Zeron Service Manual
14
Fig.4-2. Bottom view of RF Transceiver PCB Layout
4.2.1 DC Distribution and Regulation Part
The battery voltage, in return, is applied to the logic part and RF part via LDO(Low Drop-Out)
regulator. As several LDO regulators are used, power can be supplied for each necessary part
efficiently. Logic parts use +2.8V, 1.8V. Audio parts use +2.5V. RF parts such as) also use +2.8V
DC voltage. but PA circuitry use vbatt (battery volatage)
PANTECH R&D CONFIDENTIAL
Zeron Service Manual
15
4.2.2 Transciever pin description
Fig.4-3. Top View of SKY74073
Table 4.1 Pin Description of SKY74073
PANTECH R&D CONFIDENTIAL
Zeron Service Manual
16
4.2.3 Receiver Section
4.2.3.1 An Overview of Receive section
Fig.4-4. Receiver block diagram
The front-end section of the receive path consists of the diplexer, one T/R switch,and one band
–select RF SAW filter for each band. The front-end section is followed by the receive section in the
RF transceiver comprised of a programmable gain LNA, a quadrature demodulator for each band
and the baseband I/Q path with casacaded amplifiers and channel-selected filters.
The channel-select filters reduce the adjacent and second adjacent interferers to typically less than
the desired signal at the Rx outputs. The cascade amplifiers include one with a gain step of
12db,followed by another woth 2dB steps that cover a 40dB range, followed by a final stage eith
6dB steps that cover a 30 dB range
In the high gain state of the baseband amplifiers, all DC offsets amplified and , if uncorrected, the
I/Q outputs(pins 7 to 10)can suffer from significant unwanted DC offset voltages. To cancel
Correction (DCOC) circuits. The on-chip DC offset timing sequencer performs DCOC
The DCOC sequence may be set up to occure automatically using the three –wire interface bus
every time the RXENA input(pin11) goes high. The duration of the tracking time for each of the
three DCOC loops may be programmed using the three-wire interface and each loops may also be
bypassed independently in case they are not required. The LNA is enabled through automatic
timing from the sequencer
Three calibration loops are required to ensure that DC offests do not overload the baseband chain
at any point. After compensation, the correction voltage are held in on-chip capacitors for the
duration of the receive slot. Internal timing is proviede to generate the track and hold signals for
these signals can be selected relative to the RXENA signal
PANTECH R&D CONFIDENTIAL
Loading...
+ 39 hidden pages
You need points to download manuals.
1 point = 1 manual.
You can buy points or you can get point for every manual you upload.