Panasonic OneNAND128 User Manual

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OneNAND128 FLASH MEMORY

OneNAND SPECIFICATION

Product Part No. VCC(core & IO) Temperature PKG

KFG2816Q1M-DEB 1.8V(1.7V~1.95V) Extended 67FBGA(LF)/48TSOP1

OneNAND128

KFG2816D1M-DEB 2.65V(2.4V~2.9V) Extended

KFG2816U1M-DIB 3.3V(2.7V~3.6V) Industrial 67FBGA(LF)/48TSOP1

67FBGA(LF)/48TSOP1

Version: Ver. 1.0

Date: June 15th, 2005

OneNAND128 FLASH MEMORY

INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.

1. For updates or additional information about Samsung products, contact your nearest Samsung office.

2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply.

OneNAND rightful owners.

™‚ is a trademark of Samsung Electronics Company, Ltd. Other names and brands may be claimed as the property of their

OneNAND128 FLASH MEMORY

Document Title

OneNAND

Revision History

Revision No.

0.0

0.1

1.0

History

1. Initial Issue.

1. Corrected the errata

2. Revised Cold Reset

3. Added TSOP1 Package Information

4. Revised FBGA package type

5. Added 67FBGA Package Information

6. Revised typical tOTP, tLOCK from 300us to 600us

7. Revised max tOTP, tLOCK from 600us to 1000us

8. Deleted Lock All Block, Lock-Tight All Block Operation

9. Added Endurance and Data Retention

10. Revised Load Data into Buffer Operation Sequence

11. Revised Warm Reset

12. Revised Programmable Burst Read Latency Timing Diagram

13. Revised Multi Block Erase Flow Chart

14. Revised Extended Operating Temperature

1. Added Copyright Notice in the beginning

2. Corrected Errata

3. Updated Icc2, Icc4, Icc5, Icc6 and I

4. Revised INT pin description

5. Added OTP erase case NOTE

6. Revised case definitions of Interrupt Status Register

7. Added a NOTE to Command register

8. Added ECClogSector Information table

9. Removed ’data unit based data handling’ from description of Device Operation

10. Revised description on Warm/Hot/NAND Flash Core Reset

11. Revised Warm Reset Timing

12. Revised description for 4-, 8-, 16-, 32-Word Linear Burst Mode

13. Revised OTP operation description

14. Added note for OTP

15. Removed all block lock default case after cold or warm reset

16. Added explanation for each prohibited case in protect mode

17. Revised the case of writing other commands during Multi Block Erase routine

18. Added note for Erase Suspend/Resume

19. Added supplemental explanation for ECC Operation

20. Removed classification of ECC error from ECC Operation

21. Removed redundant sentance from ECC Bypass Operation

22. Added technical note for Boot Sequence

23. Added technical note for INT pin connection guide

24. Excluded tOEH from Asynchronous Read Table

25. Revised Asycnchronous Read timing diagram for CE

26. Revised Asynchronous Write timing diagram for CE

27. Revised Load operation timing diagram for CE

in Internal Register Reset

don’t care mode

Draft Date

Sep. 9, 2004

Oct. 28, 2004

Jun. 15, 2005

Remark

Advance

The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right

to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, please contact the SAMSUNG branch office near you.

OneNAND128 FLASH MEMORY

1. FEATURES

♦ Architecture

• Design Technology: 0.12µm

• Voltage Supply

- 1.8V device(KFG2816Q1M) : 1.7V~1.95V

- 2.65V device(KFG2816D1M) : 2.4V~2.9V

- 3.3V device(KFG2816U1M) : 2.7V~3.6V

• Organization

- Host Interface:16bit

• Internal BufferRAM(3K Bytes)

- 1KB for BootRAM, 2KB for DataRAM

• NAND Array

- Page Size : (1K+32)bytes

- Block Size : (64K+2K)bytes

♦ Performance

• Host Interface type

- Synchronous Burst Read : Clock Frequency: up to 54MHz : Linear Burst - 4 , 8 , 16 , 32 words with wrap-around : Continuous Sequential Burst(512 words)

- Asynchronous Random Read : Access time of 76ns

- Asynchronous Random Write

• Programmable Read latency

• Multiple Sector Read

- Read multiple sectors by Sector Count Register(up to 2 sectors)

• Multiple Reset

- Cold Reset / Warm Reset / Hot Reset / NAND Flash Reset

• Power dissipation (typical values, C

- Standby current : 10uA@1.8V device, 15uA@2.65V/3.3V device

- Synchronous Burst Read current(54MHz) : 12mA@1.8V device, 20mA@2.65V/3.3V device

- Load current : 20mA@1.8V device, 20mA@2.65V/3.3V device

- Program current: 20mA@1.8V device, 20mA@2.65V/3.3V device

- Erase current: 15mA@1.8V device, 18mA@2.65V/3.3V device

• Reliable CMOS Floating-Gate Technology

- Endurance : 100K Program/Erase Cycles

- Data Retention : 10 Years

L=30pF)

♦ Hardware Features

• Voltage detector generating internal reset signal from Vcc

• Hardware reset input (RP

• Data Protection

- Write Protection mode for BootRAM

- Write Protection mode for NAND Flash Array

- Write protection during power-up

- Write protection during power-down

• User-controlled One Time Programmable(OTP) area

• Internal 2bit EDC / 1bit ECC

• Internal Bootloader supports Booting Solution in system

)

♦ Software Features

• Handshaking Feature

- INT pin: Indicates Ready / Busy of OneNAND

- Polling method: Provides a software method of detecting the Ready / Busy status of OneNAND

• Detailed chip information by ID register

♦ Packaging

• Package

- 67ball, 7mm x 9mm x max 1.0mmt , 0.8mm ball pitch FBGA

- 48 TSOP 1, 12mm x 20mm, 0.5mm pitch

OneNAND128 FLASH MEMORY

2. GENERAL DESCRIPTION

OneNAND is a single-die chip with standard NOR Flash interface using NAND Flash Array. This device is comprised of logic and NAND Flash Array and 3KB internal BufferRAM. 1KB BootRAM is used for reserving bootcode, and 2KB DataRAM is used for buffering data. The operating clock frequency is up to 54MHz. This device is X16 interface with Host, and has the speed of ~76ns random access time. Actually, it is accessible with minimum 4clock latency(host-driven clock for synchronous read), but this device adopts the appropriate wait cycles by programmable read latency. OneNAND provides the multiple sector read operation by assigning the number of sectors to be read in the sector counter register. The device includes one block sized OTP(One Time Programmable), which can be used to increase system security or to provide identification capabilities.

OneNAND128 FLASH MEMORY

3. PIN DESCRIPTION

Pin Name Ty pe Nameand Description

Host Interface

Address Inputs

A15~A0 I

DQ15~DQ0 I/O

INT O

RDY O

CLK I

AVD I

Power Supply

CC-Core/Vcc

CC-IO/Vccq

SS Ground for OneNAND

etc.

DNU

- Inputs for addresses during operation, which are for addressing BufferRAM & Register.

Data Inputs/Outputs

- Inputs data during program and commands during all operations, outputs data during memory array/ register read cycles. Data pins float to high-impedance when the chip is deselected or outputs are disabled.

Interrupt

Notifying Host when a command has completed. It is open drain output with internal resistor(~50kohms). After power-up, it is at hi-z condition. Once IOBE is set to 1, it does not float to hi-z condition even when the chip is deselected or when outputs are disabled.

Ready

Indicates data valid in synchronous read modes and is activated while CE

Clock

CLK synchronizes the device to the system bus frequency in synchronous read mode. The first rising edge of CLK in conjunction with AVD

Write Enable

controls writes to the bufferRAM and registers. Datas are latched on the WE pulse’s rising edge

Address Valid Detect

Indicates valid address presence on address inputs. During asynchronous read operation, all addresses

are latched on AVD

CLK’s rising edge while AVD

> Low : for asynchronous mode, indicates valid address ;for burst mode,

causes starting address to be latched on rising edge on CLK

> High : device ignores address inputs

Reset Pin

When low, RP resets internal operation of OneNAND. RP status is don’t care during power-up and bootloading.

Chip Enable

CE-low activates internal control logic, and CE-high deselects the device, places it in standby state, and places ADD and DQ in Hi-Z

Output Enable

-low enables the device’s output data buffers during a read cycle.

Power for OneNAND Core

This is the power supply for OneNAND Core.

Power for OneNAND I/O

This is the power supply for OneNAND I/O Vcc-IO is internally connected to Vcc-Core, thus should be connected to the same power supply.

Do Not Use

Leave it disconnected. These pins are used for testing.

No Connection

Lead is not internally connected.

’s rising edge, and during synchronous read operation, all addresses are latched on

is held low for one clock cycle.

low latches address input.

is low

NOTE:

Do not leave power supply(V

CC, VSS) disconnected.

OneNAND128 FLASH MEMORY

4. PIN CONFIGURATION

4.1 TSOP1

N.C A15 A14 A13 A12 A11 A10

A9 A8

INT

AVD

A7 A6 A5 A4 A3 A2 A1 A0

N.C

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

48-pin TSOP1

Standard Type 12mm x 20mm

0.5mm pitch

(TOP VIEW, Facing Down)

TSOP1 OneNAND Chip

48pin, 12mm x 20mm, 0.5mm pitch TSOP1

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25

OE DQ15 DQ7 DQ14 DQ6 V

DQ13 DQ5 DQ12 DQ4 DQ11 DQ3 DQ10 DQ2 V

DQ9 DQ1 DQ8 DQ0 RDY CLK CE V

OneNAND128 FLASH MEMORY

4.2 67FBGA

WE RP DQ14

DQ12 DQ8 DQ1 OE DQ9

DQ7 DQ4 DQ11 DQ10 DQ3

DQ15 A12 DQ0 DQ5 DQ6

CLK

CE DQ2 NC NC A9

A14

A13

INT A0 A1 NC A10 A6

A4 A5 A2 A3 NC

RDY

NC NC

VSS VSS

A15

AVD A7 A11 A8

NC NC

DQ13

VCC

Core

VCC

NC NC

(TOP VIEW, Balls Facing Down)

67ball FBGA OneNAND Chip

67ball, 7.0mm x 9.0mm x max 1.0mmt , 0.8mm ball pitch FBGA

OneNAND128 FLASH MEMORY

TERMS, ABBREVIATIONS AND DEFINITIONS

B (capital letter) Byte, 8bits

W (capital letter) Word, 16bits

b (lower-case letter) Bit

ECC Error Correction Code

Calculated ECC ECC which has been calculated during load or program access

Written ECC ECC which has been stored as data in the NAND Flash Array or in the BufferRAM

BufferRAM On-chip Internal Buffer consisting of BootRAM and DataRAM

BootRAM A 1KB portion of the BufferRAM reserved for Bootcode buffering

DataRAM A 2KB portion of the BufferRAM reserved for Data buffering

Memory NAND Flash array which is embedded on OneNAND

Partial unit of page, of which size is 512B for main area and 16B for spare area data.

Sector

Data unit

It is the minimum Load/Program/Copy-Back program unit while one~two sector operation is

available

Possible data unit to be read from memory to BufferRAM or to be programmed to memory.

- 528B of which 512B is in main area and 16B in spare area

- 1056B of which 1024B is in main area and 32B in spare area

OneNAND128 FLASH MEMORY

5. BLOCK DIAGRAM

DQ15~DQ0

A15~A0

CLK

Host Interface

AVD

INT

RDY

- Host Interface

- BufferRAM(BootRAM, DataRAM)

- Command and status registers

- State Machine (Bootloader is included)

- Error Correction Logic

- Memory(NAND Flash Array, OTP)

BufferRAM

BootRAM

DataRAM

Internal Registers

(Address/Command/Configuration

/Status Registers)

Bootloader

StateMachine

NAND Flash

Array

Error

Correction

Logic

OTP

(One Block)

NOTE:

1) At cold reset, bootloader copies boot code(1K byte size) from NAND Flash Array to BootRAM.

Figure 1. Internal Block Diagram

OneNAND128 FLASH MEMORY

BootRAM

DataRAM 0

DataRAM 1

Main area data

(512B)

{

BootRAM 0

BootRAM 1

DataRAM 0_0

DataRAM 0_1

Main area data

(512B)

{

DataRAM 1_0

DataRAM 1_1

(BufferRAM)

Figure 2. BufferRAM and NAND array structure

Spare area data

(16B)

{

Spare area data

(16B)

{

Sector

Block:

64pages

64KB+2KB

Page:1KB+32B

Sector(main area):512B

Sector(spare area):16B

(NAND array)

Spare

Main area

256W

Note1 Note1 Note2 Note2 Note2 Note3 Note3 Note3 Note4 Note4

LSB MSB

1st W

NOTE:

1) The 1st word of spare area in 1st and 2nd page of every invalid block is reserved for the invalid block information by manufacturer.

Please refer to page 59 about the details.

2) These words are managed by internal ECC logic. So it is recommended that the important data like LSN(Logical Sector Number) are written.

3) These words are reserved for the future purpose by manufacturer. These words will be dedicated to internal logic.

4) These words are for free usage.

5) The 5th, 6th and 7th words are dedicated to internal ECC logic. So these words are only readable. The other words are program-

mable by command.

6) ECCm 1st, ECCm 2nd, ECCm 3rd: ECC code for Main area data

7) ECCs 1st, ECCs 2nd: ECC code for 2nd and 3rd word of spare area.

LSB MSB

{

Figure 3. Spare area of NAND array assignment

LSB MSB

{

Main area

LSB MSB

{

256W

{

area

ECCm

1st

2nd

LSB MSB

{

Spare

area

ECCm

ECCs

3rd

1st

LSB MSB

ECCs

2nd

LSB MSB

{

(Note3)

FFh

{

LSB MSB

{

OneNAND128 FLASH MEMORY

6. ADDRESS MAP For OneNAND NAND Array (word order)

Block Block Address

Block0 0000h 0000h~00FDh 64KB Block32 0020h 0000h~00FDh 64KB

Block1 0001h 0000h~00FDh 64KB Block33 0021h 0000h~00FDh 64KB

Block2 0002h 0000h~00FDh 64KB Block34 0022h 0000h~00FDh 64KB

Block3 0003h 0000h~00FDh 64KB Block35 0023h 0000h~00FDh 64KB

Block4 0004h 0000h~00FDh 64KB Block36 0024h 0000h~00FDh 64KB

Block5 0005h 0000h~00FDh 64KB Block37 0025h 0000h~00FDh 64KB

Block6 0006h 0000h~00FDh 64KB Block38 0026h 0000h~00FDh 64KB

Block7 0007h 0000h~00FDh 64KB Block39 0027h 0000h~00FDh 64KB

Block8 0008h 0000h~00FDh 64KB Block40 0028h 0000h~00FDh 64KB

Block9 0009h 0000h~00FDh 64KB Block41 0029h 0000h~00FDh 64KB

Block10 000Ah 0000h~00FDh 64KB Block42 002Ah 0000h~00FDh 64KB

Block11 000Bh 0000h~00FDh 64KB Block43 002Bh 0000h~00FDh 64KB

Block12 000Ch 0000h~00FDh 64KB Block44 002Ch 0000h~00FDh 64KB

Block13 000Dh 0000h~00FDh 64KB Block45 002Dh 0000h~00FDh 64KB

Block14 000Eh 0000h~00FDh 64KB Block46 002Eh 0000h~00FDh 64KB

Block15 000Fh 0000h~00FDh 64KB Block47 002Fh 0000h~00FDh 64KB

Block16 0010h 0000h~00FDh 64KB Block48 0030h 0000h~00FDh 64KB

Block17 0011h 0000h~00FDh 64KB Block49 0031h 0000h~00FDh 64KB

Block18 0012h 0000h~00FDh 64KB Block50 0032h 0000h~00FDh 64KB

Block19 0013h 0000h~00FDh 64KB Block51 0033h 0000h~00FDh 64KB

Block20 0014h 0000h~00FDh 64KB Block52 0034h 0000h~00FDh 64KB

Block21 0015h 0000h~00FDh 64KB Block53 0035h 0000h~00FDh 64KB

Block22 0016h 0000h~00FDh 64KB Block54 0036h 0000h~00FDh 64KB

Block23 0017h 0000h~00FDh 64KB Block55 0037h 0000h~00FDh 64KB

Block24 0018h 0000h~00FDh 64KB Block56 0038h 0000h~00FDh 64KB

Block25 0019h 0000h~00FDh 64KB Block57 0039h 0000h~00FDh 64KB

Block26 001Ah 0000h~00FDh 64KB Block58 003Ah 0000h~00FDh 64KB

Block27 001Bh 0000h~00FDh 64KB Block59 003Bh 0000h~00FDh 64KB

Block28 001Ch 0000h~00FDh 64KB Block60 003Ch 0000h~00FDh 64KB

Block29 001Dh 0000h~00FDh 64KB Block61 003Dh 0000h~00FDh 64KB

Block30 001Eh 0000h~00FDh 64KB Block62 003Eh 0000h~00FDh 64KB

Block31 001Fh 0000h~00FDh 64KB Block63 003Fh 0000h~00FDh 64KB

NOTE 1) The 2nd bit of Page and Sector address register is Don’t care. So the address range is bigger than the real range. Even though 2nd bit is set to "1", this bit is always considered "0". Please refer to Start Address 8 register.

Page and Sector

Address

(1)

Size Block Block Address

Page and Sector

Address

(1)

Size

OneNAND128 FLASH MEMORY

Block Block Address

Page and Sector

Address

(1)

Size Block Block Address

Page and Sector

Address

(1)

Block64 0040h 0000h~00FDh 64KB Block96 0060h 0000h~00FDh 64KB

Block65 0041h 0000h~00FDh 64KB Block97 0061h 0000h~00FDh 64KB

Block66 0042h 0000h~00FDh 64KB Block98 0062h 0000h~00FDh 64KB

Block67 0043h 0000h~00FDh 64KB Block99 0063h 0000h~00FDh 64KB

Block68 0044h 0000h~00FDh 64KB Block100 0064h 0000h~00FDh 64KB

Block69 0045h 0000h~00FDh 64KB Block101 0065h 0000h~00FDh 64KB

Block70 0046h 0000h~00FDh 64KB Block102 0066h 0000h~00FDh 64KB

Block71 0047h 0000h~00FDh 64KB Block103 0067h 0000h~00FDh 64KB

Block72 0048h 0000h~00FDh 64KB Block104 0068h 0000h~00FDh 64KB

Block73 0049h 0000h~00FDh 64KB Block105 0069h 0000h~00FDh 64KB

Block74 004Ah 0000h~00FDh 64KB Block106 006Ah 0000h~00FDh 64KB

Block75 004Bh 0000h~00FDh 64KB Block107 006Bh 0000h~00FDh 64KB

Block76 004Ch 0000h~00FDh 64KB Block108 006Ch 0000h~00FDh 64KB

Block77 004Dh 0000h~00FDh 64KB Block109 006Dh 0000h~00FDh 64KB

Block78 004Eh 0000h~00FDh 64KB Block110 006Eh 0000h~00FDh 64KB

Block79 004Fh 0000h~00FDh 64KB Block111 006Fh 0000h~00FDh 64KB

Block80 0050h 0000h~00FDh 64KB Block112 0070h 0000h~00FDh 64KB

Block81 0051h 0000h~00FDh 64KB Block113 0071h 0000h~00FDh 64KB

Block82 0052h 0000h~00FDh 64KB Block114 0072h 0000h~00FDh 64KB

Block83 0053h 0000h~00FDh 64KB Block115 0073h 0000h~00FDh 64KB

Block84 0054h 0000h~00FDh 64KB Block116 0074h 0000h~00FDh 64KB

Block85 0055h 0000h~00FDh 64KB Block117 0075h 0000h~00FDh 64KB

Block86 0056h 0000h~00FDh 64KB Block118 0076h 0000h~00FDh 64KB

Block87 0057h 0000h~00FDh 64KB Block119 0077h 0000h~00FDh 64KB

Block88 0058h 0000h~00FDh 64KB Block120 0078h 0000h~00FDh 64KB

Block89 0059h 0000h~00FDh 64KB Block121 0079h 0000h~00FDh 64KB

Block90 005Ah 0000h~00FDh 64KB Block122 007Ah 0000h~00FDh 64KB

Block91 005Bh 0000h~00FDh 64KB Block123 007Bh 0000h~00FDh 64KB

Block92 005Ch 0000h~00FDh 64KB Block124 007Ch 0000h~00FDh 64KB

Block93 005Dh 0000h~00FDh 64KB Block125 007Dh 0000h~00FDh 64KB

Block94 005Eh 0000h~00FDh 64KB Block126 007Eh 0000h~00FDh 64KB

Block95 005Fh 0000h~00FDh 64KB Block127 007Fh 0000h~00FDh 64KB

NOTE 1) 2nd bit of Page and Sector address is Don’t care. So the address range is bigger than the real range. Even though 2nd bit is set to "1", this bit is always considered "0". Please refer to Start Address 8 register.

Size

OneNAND128 FLASH MEMORY

Block Block Address

Page and Sector

Address

(1)

Size Block Block Address

Page and Sector

Address

(1)

Block128 0080h 0000h~00FDh 64KB Block160 00A0h 0000h~00FDh 64KB

Block129 0081h 0000h~00FDh 64KB Block161 00A1h 0000h~00FDh 64KB

Block130 0082h 0000h~00FDh 64KB Block162 00A2h 0000h~00FDh 64KB

Block131 0083h 0000h~00FDh 64KB Block163 00A3h 0000h~00FDh 64KB

Block132 0084h 0000h~00FDh 64KB Block164 00A4h 0000h~00FDh 64KB

Block133 0085h 0000h~00FDh 64KB Block165 00A5h 0000h~00FDh 64KB

Block134 0086h 0000h~00FDh 64KB Block166 00A6h 0000h~00FDh 64KB

Block135 0087h 0000h~00FDh 64KB Block167 00A7h 0000h~00FDh 64KB

Block136 0088h 0000h~00FDh 64KB Block168 00A8h 0000h~00FDh 64KB

Block137 0089h 0000h~00FDh 64KB Block169 00A9h 0000h~00FDh 64KB

Block138 008Ah 0000h~00FDh 64KB Block170 00AAh 0000h~00FDh 64KB

Block139 008Bh 0000h~00FDh 64KB Block171 00ABh 0000h~00FDh 64KB

Block140 008Ch 0000h~00FDh 64KB Block172 00ACh 0000h~00FDh 64KB

Block141 008Dh 0000h~00FDh 64KB Block173 00ADh 0000h~00FDh 64KB

Block142 008Eh 0000h~00FDh 64KB Block174 00AEh 0000h~00FDh 64KB

Block143 008Fh 0000h~00FDh 64KB Block175 00AFh 0000h~00FDh 64KB

Block144 0090h 0000h~00FDh 64KB Block176 00B0h 0000h~00FDh 64KB

Block145 0091h 0000h~00FDh 64KB Block177 00B1h 0000h~00FDh 64KB

Block146 0092h 0000h~00FDh 64KB Block178 00B2h 0000h~00FDh 64KB

Block147 0093h 0000h~00FDh 64KB Block179 00B3h 0000h~00FDh 64KB

Block148 0094h 0000h~00FDh 64KB Block180 00B4h 0000h~00FDh 64KB

Block149 0095h 0000h~00FDh 64KB Block181 00B5h 0000h~00FDh 64KB

Block150 0096h 0000h~00FDh 64KB Block182 00B6h 0000h~00FDh 64KB

Block151 0097h 0000h~00FDh 64KB Block183 00B7h 0000h~00FDh 64KB

Block152 0098h 0000h~00FDh 64KB Block184 00B8h 0000h~00FDh 64KB

Block153 0099h 0000h~00FDh 64KB Block185 00B9h 0000h~00FDh 64KB

Block154 009Ah 0000h~00FDh 64KB Block186 00BAh 0000h~00FDh 64KB

Block155 009Bh 0000h~00FDh 64KB Block187 00BBh 0000h~00FDh 64KB

Block156 009Ch 0000h~00FDh 64KB Block188 00BCh 0000h~00FDh 64KB

Block157 009Dh 0000h~00FDh 64KB Block189 00BDh 0000h~00FDh 64KB

Block158 009Eh 0000h~00FDh 64KB Block190 00BEh 0000h~00FDh 64KB

Block159 009Fh 0000h~00FDh 64KB Block191 00BFh 0000h~00FDh 64KB

Size

OneNAND128 FLASH MEMORY

Block Block Address

Page and Sector

Address

(1)

Size Block Block Address

Page and Sector

Address

(1)

Block192 00C0h 0000h~00FDh 64KB Block224 00E0h 0000h~00FDh 64KB

Block193 00C1h 0000h~00FDh 64KB Block225 00E1h 0000h~00FDh 64KB

Block194 00C2h 0000h~00FDh 64KB Block226 00E2h 0000h~00FDh 64KB

Block195 00C3h 0000h~00FDh 64KB Block227 00E3h 0000h~00FDh 64KB

Block196 00C4h 0000h~00FDh 64KB Block228 00E4h 0000h~00FDh 64KB

Block197 00C5h 0000h~00FDh 64KB Block229 00E5h 0000h~00FDh 64KB

Block198 00C6h 0000h~00FDh 64KB Block230 00E6h 0000h~00FDh 64KB

Block199 00C7h 0000h~00FDh 64KB Block231 00E7h 0000h~00FDh 64KB

Block200 00C8h 0000h~00FDh 64KB Block232 00E8h 0000h~00FDh 64KB

Block201 00C9h 0000h~00FDh 64KB Block233 00E9h 0000h~00FDh 64KB

Block202 00CAh 0000h~00FDh 64KB Block234 00EAh 0000h~00FDh 64KB

Block203 00CBh 0000h~00FDh 64KB Block235 00EBh 0000h~00FDh 64KB

Block204 00CCh 0000h~00FDh 64KB Block236 00ECh 0000h~00FDh 64KB

Block205 00CDh 0000h~00FDh 64KB Block237 00EDh 0000h~00FDh 64KB

Block206 00CEh 0000h~00FDh 64KB Block238 00EEh 0000h~00FDh 64KB

Block207 00CFh 0000h~00FDh 64KB Block239 00EFh 0000h~00FDh 64KB

Block208 00D0h 0000h~00FDh 64KB Block240 00F0h 0000h~00FDh 64KB

Block209 00D1h 0000h~00FDh 64KB Block241 00F1h 0000h~00FDh 64KB

Block210 00D2h 0000h~00FDh 64KB Block242 00F2h 0000h~00FDh 64KB

Block211 00D3h 0000h~00FDh 64KB Block243 00F3h 0000h~00FDh 64KB

Block212 00D4h 0000h~00FDh 64KB Block244 00F4h 0000h~00FDh 64KB

Block213 00D5h 0000h~00FDh 64KB Block245 00F5h 0000h~00FDh 64KB

Block214 00D6h 0000h~00FDh 64KB Block246 00F6h 0000h~00FDh 64KB

Block215 00D7h 0000h~00FDh 64KB Block247 00F7h 0000h~00FDh 64KB

Block216 00D8h 0000h~00FDh 64KB Block248 00F8h 0000h~00FDh 64KB

Block217 00D9h 0000h~00FDh 64KB Block249 00F9h 0000h~00FDh 64KB

Block218 00DAh 0000h~00FDh 64KB Block250 00FAh 0000h~00FDh 64KB

Block219 00DBh 0000h~00FDh 64KB Block251 00FBh 0000h~00FDh 64KB

Block220 00DCh 0000h~00FDh 64KB Block252 00FCh 0000h~00FDh 64KB

Block221 00DDh 0000h~00FDh 64KB Block253 00FDh 0000h~00FDh 64KB

Block222 00DEh 0000h~00FDh 64KB Block254 00FEh 0000h~00FDh 64KB

Block223 00DFh 0000h~00FDh 64KB Block255 00FFh 0000h~00FDh 64KB

Size

OneNAND128 FLASH MEMORY

Detailed information of Address Map (word order)

• BootRAM(Main area)

-0000h~01FFh: 2(sector) x 512byte(NAND main area) = 1KB

0000h~00FFh(512B)

BootM 0

(sector 0 of page 0)

• DataRAM(Main area)

-0200h~05FFh: 4(sector) x 512byte(NAND main area) = 2KB

0200h~02FFh(512B)

DataM 0_0

(sector 0 of page 0)

• BootRAM(Spare area)

-8000h~800Fh: 2(sector) x 16byte(NAND spare area) = 32B

8000h~8007h(16B)

BootS 0

(sector 0 of page 0)

• DataRAM(Spare area)

-8010h~802Fh: 4(sector) x 16byte(NAND spare area) = 64B

8010h~8017h(16B)

DataS 0_0

(sector 0 of page 0)

0300h~03FFh(512B)

DataM 0_1

(sector 1 of page 0)

8018h~801Fh(16B)

DataS 0_1

(sector 1 of page 0)

0400h~04FFh(512B)

DataM 1_0

(sector 0 of page 1)

8020h~8027h(16B)

DataS 1_0

(sector 0 of page 1)

0100h~01FFh(512B)

BootM 1

(sector 1 of page 0)

0500h~05FFh(512B)

DataM 1_1

(sector 1 of page 1)

8008h~800Fh(16B)

BootS 1

(sector 1 of page 0)

8028h~802Fh(16B)

DataS 1_1

(sector 1 of page 1)

*NAND Flash array consists of 1KB page size and 64KB block size.

OneNAND128 FLASH MEMORY

Spare area assignment

Equivalent to 1word of NAND Flash

Buf.

Word

Address

Byte

Address

F E D C B A 9 8 7 6 5 4 3 2 1 0

BootS 0 8000h 10000h BI

8001h 10002h Managed by Internal ECC logic

8002h 10004h Reserved for the future use Managed by Internal ECC logic

8003h 10006h Reserved for the current and future use

8004h 10008h

8005h 1000Ah

ECC Code for Main area data (2

ECC Code for Spare area data (1

) ECC Code for Main area data (1st)

) ECC Code for Main area data (3rd)

8006h 1000Ch FFh(Reserved for the future use)

8007h 1000Eh Free Usage

BootS 1 8008h 10010h BI

8009h 10012h Managed by Internal ECC logic

800Ah 10014h Reserved for the future use Managed by Internal ECC logic

800Bh 10016h Reserved for the current and future use

800Ch 10018h

800Dh 1001Ah

ECC Code for Main area data (2

ECC Code for Spare area data (1

) ECC Code for Main area data (1st)

) ECC Code for Main area data (3rd)

800Eh 1001Ch FFh(Reserved for the future use)

800Fh 1001Eh Free Usage

DataS

0_0

8010h 10020h BI

8011h 10022h Managed by Internal ECC logic

8012h 10024h Reserved for the future use Managed by Internal ECC logic

8013h 10026h Reserved for the current and future use

8014h 10028h

8015h 1002Ah

ECC Code for Main area data (2

ECC Code for Spare area data (1

) ECC Code for Main area data (1st)

) ECC Code for Main area data (3rd)

8016h 1002Ch FFh(Reserved for the future use)

8017h 1002Eh Free Usage

DataS

0_1

8018h 10030h BI

8019h 10032h Managed by Internal ECC logic

801Ah 10034h Reserved for the future use Managed by Internal ECC logic

801Bh 10036h Reserved for the current and future use

801Ch 10038h

801Dh 1003Ah

ECC Code for Main area data (2

ECC Code for Spare area data (1

) ECC Code for Main area data (1st)

) ECC Code for Main area data (3rd)

801Eh 1003Ch FFh(Reserved for the future use)

801Fh 1003Eh Free Usage

ECC Code for Spare area data (2

)

OneNAND128 FLASH MEMORY

Equivalent to 1word of NAND Flash

Buf.

Word

Address

Byte

Address

F E D C B A 9 8 7 6 5 4 3 2 1 0

DataS 1_0 8020h 10040h BI

8021h 10042h Managed by Internal ECC logic

8022h 10044h Reserved for the future use Managed by Internal ECC logic

8023h 10046h Reserved for the current and future use

8024h 10048h

8025h 1004Ah

ECC Code for Main area data (2

ECC Code for Spare area data (1

) ECC Code for Main area data (1st)

) ECC Code for Main area data (3rd)

8026h 1004Ch FFh(Reserved for the future use)

8027h 1004Eh Free Usage

DataS 1_1 8028h 10050h BI

8029h 10052h Managed by Internal ECC logic

802Ah 10054h Reserved for the future use Managed by Internal ECC logic

802Bh 10056h Reserved for the current and future use

802Ch 10058h

802Dh 1005Ah

ECC Code for Main area data (2

ECC Code for Spare area data (1

) ECC Code for Main area data (1st)

) ECC Code for Main area data (3rd)

802Eh 1005Ch FFh(Reserved for the future use)

802Fh 1005Eh Free Usage

NOTE:

- BI: Invalid block Information

ECC Code for Spare area data (2

)

>Host can use complete spare area except BI and ECC code area. For example, Host can write data to Spare area buffer except for the area controlled by ECC logic at program operation. >OneNAND automatically generates ECC code for both main and spare data of memory during program operation in case of ’with ECC’ mode , but does not update ECC code to spare bufferRAM. >When loading/programming spare area, spare area BufferRAM address(BSA) and BufferRAM sector count(BSC) is chosen via Start buffer register

as it is.

OneNAND128 FLASH MEMORY

7. Detailed address map for registers

Address

(word order)

F000h 1E000h Manufacturer ID R Manufacturer identification

F001h 1E002h Device ID R Device identification

F002h 1E004h Version ID R Version identification

F003h 1E006h Data Buffer size R Data buffer size

F004h 1E008h Boot Buffer size R Boot buffer size

F005h 1E00Ah

F006h 1E00Ch Technology R Info about technology

F007h~F0FFh 1E00Eh~1E1FEh Reserved - Reserved for User

F100h 1E200h Start address 1 R/W NAND Flash Block address

F101h 1E202h Start address 2 R/W Reserved

F102h 1E204h Start address 3 R/W Destination Block address for Copy back program

F103h 1E206h Start address 4 R/W

F104h 1E208h Start address 5 - N/A

F105h 1E20Ah Start address 6 - N/A

F106h 1E20Ch Start address 7 - N/A

F107h 1E20Eh Start address 8 R/W NAND Flash Page & Sector address

F108h~F1FFh 1E210h~1E3FEh Reserved - Reserved for User

F200h 1E400h Start Buffer R/W

F201h~F207h 1E402h~1E40Eh Reserved - Reserved for User

F208h~F21Fh 1E410h~1E43Eh Reserved - Reserved for vendor specific purposes

F220h 1E440h Command R/W Host control and memory operation commands

F221h 1E442h

F222h 1E444h

F223h~F22Fh 1E446h~1E45Eh Reserved - Reserved for User

F230h~F23Fh 1E460h~1E47Eh Reserved - Reserved for vendor specific purposes

F240h 1E480h Controller Status R Controller Status and result of memory operation

F241h 1E482h Interrupt R/W Memory Command Completion Interrupt Status

F242h~F24Bh 1E484h~1E496h Reserved - Reserved for User

F24Ch 1E498h

F24Dh 1E49Ah

F24Eh 1E49Ch

F24Fh~FEFFh 1E49Eh~1FDFEh Reserved - Reserved for User

Address

(byte order)

Name

Amount of

buffers

System

Configuration 1

System

Configuration 2

Unlock Start

Block Address

Unlock End

Block Address

Write Protection

Status

Host

Access

R Amount of data/boot buffers

Destination Page & Sector address for Copy back program

Number Buffer of for the page data transfer to/from the memory and the start Buffer Address The meaning is with which buffer to start and how many buffers to use for the data transfer

R, R/W Memory and Host Interface Configuration

-N/A

Start memory block address to unlock in Write

R/W

Protection mode

End memory block address to unlock in Write

R/W

Protection mode

Current memory Write Protection status

(unlocked/locked/tight-locked)

Description

OneNAND128 FLASH MEMORY

Address

(word order)

FF00h 1FE00h

FF01h 1FE02h

FF02h 1FE04h

FF03h 1FE06h

FF04h 1FE08h

FF05h~FFFFh 1FE12h~1FF0Ah Reserved - Reserved for vendor specific purposes

Address

(byte order)

Name

ECC Status

ECC Result of

main area data

ECC Result of

spare area data

ECC Result of

main area data

ECC Result of

spare area data

Host

Access

R ECC status of sector

ECC error position of Main area data error for first

selected Sector

ECC error position of Spare area data error for first

selected Sector

ECC error position of Main area data error for second

selected Sector

ECC error position of Spare area data error for second

selected Sector

Description

OneNAND128 FLASH MEMORY

7. Address Register (word order)

7.1 Manufacturer ID Register (R): F000h, default=00ECh

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ManufID

ManufID (Manufacturer ID): manufacturer identification, 00ECh for Samsung Electronics Corp.

7.2 Device ID Register (R): F001h, default=refer to Table1

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DeviceID

DeviceID (Device ID): Device Identification,

Table 1.

Device DeviceID[15:0]

KFG2816Q1M 0004h

KFG2816D1M 0005h

KFG2816U1M 0005h

7.3 Version ID Register (R): F002h

: N/A

OneNAND128 FLASH MEMORY

7.4 Data Buffer size Register(R): F003h, default=0400h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DataBufSize

DataBufSize: total data buffer size in words in the memory interface used for shrinks Equals two buffers of 512 words each(2x512=2

7.5 Boot Buffer size Register (R): F004h, default=0200h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BootBufSize: total boot buffer size in words in the memory interface (512 words=2

, N=9)

7.6 Amount of Buffers Register (R): F005h, default=0201h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DataBufAmount BootBufAmount

DataBufAmount: the amount of data buffer=2(2N, N=1) BootBufAmount: the amount of boot buffer=1(2

7.7 Technology Register (R): F006h, default=0000h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Tech: technology information, what technology is used for the memory

, N=0)

, N=10)

BootBufSize

Te ch

Tech Technology

0000h NAND SLC

0001h NAND MLC

0002h-FFFFh Reserved

OneNAND128 FLASH MEMORY

7.8 Start Address1 Register (R/W): F100h, default=0000h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved(00000000) FBA

FBA (NAND Flash Block Address): NAND Flash block address which will be read or programmed or erased.

Device Number of Block FBA

128Mb 256 FBA[7:0]

7.9 Start Address2 Register (R/W): F101h, default=0000h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved(0000000000000000)

7.10 Start Address3 Register (R/W): F102h, default=0000h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved(00000000) FCBA

FCBA (NAND Flash Copy Back Block Address): NAND Flash destination block address which will be copy back programmed.

Device Number of Block FBA

128Mb 256 FBA[7:0]

7.11 Start Address4 Register (R/W): F103h, default=0000h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved(00000000) FCPA Reserved FCSA

FCPA (NAND Flash Copy Back Page Address): NAND Flash destination page address in a block for copy back program operation. FCPA(default value) = 000000 FCPA range : 000000~111111, 6bits for 64 pages

FCSA (NAND Flash Copy Back Sector Address): NAND Flash destination sector address in a page for copy back program operation. FCSA(default value) = 0

FCSA range : 0~1, 1bits for 2 sectors

OneNAND128 FLASH MEMORY

7.12 Start Address5 Register: F104h

: N/A

7.13 Start Address6 Register: F105h

: N/A

7.14 Start Address7 Register: F106h

: N/A

7.15 Start Address8 Register (R/W): F107h, default=0000h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved (00000000) FPA Reserved FSA

FPA (NAND Flash Page Address): NAND Flash start page address in a block for page read or copy back program or program operation. FPA(default value)=000000 FPA range: 000000~111111 , 6bits for 64 pages

FSA (Flash Sector Address): NAND Flash start sector address in a page for read or copy back program or program operation. FSA(default value) = 0

FSA range : 0~1, 1bits for 2 sectors

7.16 Start Buffer Register (R/W): F200h, default=0000h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved(0000) BSA Reserved(0000000) BSC

BSC (BufferRAM Sector Count): this field specifies the number of sectors to be read or programmed or copy back programmed. Its maximum count is 2 sectors at 0(default value)value. For a single sector access, it should be programmed as value 1 and it should be programmed as value 0 for two sectors. However internal RAM buffer reached to 1 value(max. value), it counts up to 0 value to satisfy BSC value. for example) if BSA=1101, BSC=0, then selected BufferRAM are ’1101->1100’.

BSA (BufferRAM Sector Address): It is the place where data is placed and specifies the sector 0~1 in the internal BootRAM and DataRAM. BSA[3] is the selection bit between BootRAM and DataRAM. BSA[2] is the selection bit between DataRAM0 and DataRAM1. BSA[0] is the selection bit between Sector0 and Sector1 in the internal BootRAM and DataRAM. While one of BootRAM or DataRAM0 interfaces with memory, the other RAM is inaccessible.

BootRAM

DataRAM0

DataRAM1

Main area data

{

BootRAM 0

BootRAM 1

DataRAM 0_0

DataRAM 0_1

DataRAM 1_0

DataRAM 1_1

Spare area data

{

BSA

0000

0001

1000

1001

1100

1101

Sector: (512 + 16)byte

BSC Number of Sectors

1 1 sector

0 2 sectors

OneNAND128 FLASH MEMORY

7.17 Command Register (R/W): F220h, default=0000h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Command

Command: operation of the memory interface

Acceptable

CMD Operation

0000h Load single/multiple sector data unit into buffer 00F0h, 00F3h

0013h Load single/multiple spare sector into buffer 00F0h, 00F3h

0080h Program single/multiple sector data unit from buffer 00F0h, 00F3h

001Ah Program single/multiple spare area sector from buffer 00F0h, 00F3h

001Bh Copy back program 00F0h, 00F3h

0023h Unlock NAND array block(s) from start block address to end block address -

002Ah Lock NAND array block(s) from start block address to end block address -

002Ch Lock-tight NAND array block(s) from start block address to end block address -

0071h Erase Verify Read 00F0h, 00F3h

0094h Block Erase 00F0h, 00F3h

0095h Multi-Block Erase 00F0h, 00F3h

00B0h Erase Suspend 00F3h

0030h Erase Resume 00F0h, 00F3h

00F0h Reset NAND Flash Core -

00F3h Reset OneNAND 1) -

0065h OTP Access 00F0h, 00F3h

NOTE:

1)’Reset OneNAND’(=Hot reset) command makes the registers(except RDYpol, INTpol, IOBE, and OTP the warm reset(=reset by RP

pin).

L bits) and NAND Flash core into default state as

command

during busy

This R/W register describes the operation of the OneNAND interface. Note that all commands should be issued right after INT is turned from ready state to busy state. (i.e. right after 0 is written to INT register.) After any

command is issued and the corresponding operation is completed, INT goes back to ready state. (00F0h and 00F3h may be accepted during busy state of some operations. Refer to the rightmost column of the command register table above.)

OneNAND128 FLASH MEMORY

7.18 System Configuration 1 Register (R, R/W): F221h, default=40C0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R/W R/W R/W R/W R/W R/W R/W R R

RM BRL BL ECC

RM (Read Mode): this field specifies the selection between asynchronous read mode and synchronous read mode

RDY

pol

INT

pol

IOB

RM Read Mode

0 Asynchronous read(default)

1 Synchronous read

BRL (Burst Read Latency): this field specifies the initial access latency in the burst read transfer.

BRL Latency Cycles

000 8(N/A)

001 9(N/A)

010 10(N/A)

011 3(up to 40MHz)

100 4(default, min.)

101 5

110 6

111 7

Reserved(0000)

BL (Burst Length): this field specifies the size of burst length during Sync. burst read. Wrap around and linear burst.

BL Burst Length(Main) Burst Length(Spare)

000 Continuous(default)

001 4 words

010 8 words

011 16 words

100 32 words N/A

101~111 Reserved

ECC: Error Correction Operation, 0=with correction(default), 1=without correction(by-passed)

RDYpol: RDY signal polarity 0=low for ready, 1=high for ready((default)

INTpol: INT Pin polarity 0=low for Interrupt pending , 1=high for Interrupt pending (default)

INTpol INT bit of Interrupt Status Register INT Pin output

00 1

10 0

IOBE: I/O buffer enable for INT and RDY signals, INT and RDY outputs are HighZ at power-up, bit 7 and 6 become valid after IOBE is set to1. IOBE can be reset only by Cold reset or by writing 0 to bit 5 of System Configuration 1 register. 0=disable(default), 1=enable

BWPS: boot buffer write protect status, 0=locked(fixed)

OneNAND128 FLASH MEMORY

7.19 System Configuration 2 Register : F222h

: N/A

7.22 Controller Status Register (R): F240h, default=0000h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OnGo Lock Load Prog Erase Error Sus PRp RSTB OTP

OnGo: this bit shows the overall internal status of OneNAND 0=ready, 1=busy

Lock: this bit shows whether host loads data from NAND Flash array into locked BootRAM or programs/erases locked block of NAND Flash array.

L Reserved(000000)

Lock Locked/Unlocked Check Result

0 Unlocked

1 Locked

Error (Current Sector/Page Write Result): this bit shows current sector/page Load/Program/Copy Back Program/Erase result of flash memory or whether host puts invalid command into the device.

(0)

Error

Current Sector/Page Load/Program/CopyBack. Program/Erase Result

and Invalid Command Input

0Pass

1Fail

Sus (Erase Suspend/Resume):this bit shows the Erase Suspend Status.

Sus Erase Suspend Status

0 Erase Resume(Default)

1 Erase Suspend

OTPL (OTP Lock Status):this bit shows OTP block is locked or unlocked. OTPL bit is automatically updated at power-on.

OTPL OTP Locked/Unlocked Status

0 OTP Block Unlock Status(Default)

1 OTP Block Lock Status(Disable OTP Program/Erase)

TO (Time Out): time out for read/program/copy back program/erase 0=no time out(fixed)

Load : this bit shows the Load operation status 0=ready(default), 1=busy or error case, refer to the table 3

Prog (Program Busy) : this bit shows the Program operation status 0=ready(default), 1=busy or error case, refer to the table 3

Erase (Erase Busy) : this bit shows the Erase operation status 0=ready(default), 1=busy or error case, refer to the table 3

RSTB (Reset Busy) : this bit shows the Reset operation status 0=ready(default), 1=busy or error case, refer to the table 3

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