Panasonic MTM86628 User Manual

This product complies with the RoHS Directive (EU 2002/95/EC).

1

(G)2(S)3(A)

(K)

4

(D)

5

(D)

6

Multi Chip Discrete

MTM86628

Silicon P-channel MOS FET (FET)
Silicon epitaxial planar type (SBD)

For DC-DC converter
For switching circuits

 Overview

MTM86628 is the composite MOS FET (P-channel MOS FET and Schottky

Barrier Diode) that is highly suitable for DC-DC converter and other switching

circuits.

 Features

 Built-in schottky barrier diode: VR = 15 V, IF = 700 mA
 Low on-resistance: Ron = 300 mW (VGS = –4.0 V)
 Low short-circuit input capacitance (Common source): C
 Small surface mounting halogen-free package: WSSMini6-F1 (1.6 mm × 1.6

mm × 0.5 mm)

= 80 pF

iss

 Package

Code

WSSMini6-F1
Pin Name

1: Gate 4: Cathode

2: Source 5: Drain

3: Anode 6: Drain

 Marking Symbol: PL

 Internal Connection

 Absolute Maximum Ratings Ta = 25°C

Parameter Symbol Rating Unit

Drain-source surrender voltage V

Gate-source surrender voltage V

Drain current I

1

*

FET

Peak drain current

Channel temperature

Storage temperature T

Total power dissipation

Reverse voltage V

Forward current (Average) I

SBD

Junction temperature T

Storage temperature T

Note) *1: t = 10 µs, Duty Cycle < 1%

2: Glass epoxy board: 25.4 mm × 25.4 mm × 0.8 mm

*

Copper foil of the drain portion should have a area of 300 mm2 or more

3: Stand-alone (without the board)

*

P

P

F(AV)

I

T

D1

D2

DSS

GSS

D

DP

ch

stg

stg

2

*

3

*

R

j

–20 V
±12

–1.0 A

–4.0 A

150

–55 to +150

540 mW

150 mW

15 V

700 mA

125

–55 to +125

V

°C
°C

°C
°C

Publication date: November 2008 SJF00111AED 1

This product complies with the RoHS Directive (EU 2002/95/EC).

VDD = −15 V

PW = 10 µs
Duty Cycle ≤ 1%

ID = − 0.5 A
RL = 30 Ω

V

OUT

V

IN

D

G

S

V

IN

50 Ω

t

d(on)

t

d(off)

0 V

−4 V

V

IN

V

OUT

10%

90%

90%

10%

t

r

t

f

MTM86628

 Electrical Characteristics Ta = 25°C±3°C

 FET

Parameter Symbol Conditions Min Typ Max Unit

Drain-source surrender voltage V

Drain-source cutoff current

Gate-source cutoff current

Gate threshold voltage V

Drain-source ON resistance R

Forward transfer admittance

Short-circuit input capacitance (Common source)

Short-circuit output capacitance (Common source)

Reverse transfer capacitance (Common source)

Turn-on delay time

Rise time

*

Turn-off delay time

Fall time

Note) 1. Measuring methods are based on JAPANESE INDUSTRIAL STANDARD JIS C 7030 measuring methods for transistors.

2. *: ton , t

*

*

*

measurement circuit

off

DSSID

I

DSS

I

GSS

THID

DS(on)

Yfs

C

iss

C

oss

C

rss

t

d(on)

t

r

t

d(off)

t

f

= –1.0 mA, VGS = 0 –20 V

VDS = –20 V, VGS = 0 –1.0

VGS = ±10 V, VDS = 0

= –1.0 mA, VDS = –10 V – 0.45 –1.0 –1.5 V

ID = – 0.5 A, VGS = –4.0 V 300 420

ID = – 0.5 A, VGS = –2.5 V 420 560

ID = – 0.5 A, VDS = –10 V 1.0 2.0 S

80 pF

VDS = –10 V, VGS = 0, f = 1 MHz

12 pF

12 pF

12 ns

VDD = –15 V, VGS = –4.0 V, ID = – 0.5 A

6 ns

17 ns

10 ns

µA

±10 µA

mW

 SBD

Parameter Symbol Conditions Min Typ Max Unit

Forward voltage V

Reverse current I

Note) Measuring methods are based on JAPANESE INDUSTRIAL STANDARD JIS C 7031 measuring methods for diodes.

2 SJF00111AED

IF = 500 mA 0.42 V

F

IF = 700 mA 0.45 V

VR = 6 V 90

R

VR = 15 V 250

µA
µA