Panasonic MN6155 Datasheet
For Communications Equipment
MN6155
PLL LSI with Built-In Prescaler
Overview
The MN6155 is a CMOS LSI for a phase-locked loop
(PLL) frequency synthesizer with serial data parameter
input.
It consists of a two-coefficient prescaler, variable
frequency divider, phase comparator, and charge pump.
It offers high-speed operation on a low power supply
voltage (1.0 to 1.4 V) and low power consumption (1.65
mW for V
=1.1 V, FIN= RIN=90 MHz).
DD
Other features include intermittent operation by the
power save (PS) control signal and high-speed pull-in that
rapidly corrects the phase differences occurring at the start
of operation.
It also offers two choices for the reference signal: selfÂexcited operation using the built-in inverter amplifier or
use of an external, separately excited oscillator.
Features
Low power supply voltage:VDD=1.0 to 1.4V
Low power consumption: 1.65mW(VDD=1.10V,
F
=90MHz, RIN=90MHz)
IN
High-speed operation: FIN=90MHz, RIN=90MHz
(V
=1.1V)
DD
Frequency dividing ratios in reference frequency
dividing stage
6 to 131,070 for RSL at "H" level
(even number setting is available)
272 to 131,071 for RSL at "L" level
Frequency dividing ratios for comparator stage: 272
to 262,143
Power supply pin for built-in charge pump
V
=2.5 to 3.2V
CP
Output monitor pins for both comparator and reference
frequency dividing stages
Pin Assignment
X
X
OUT
FV
V
D
V
V
F
DD
1
IN
2
3
4
5
OP
6
SS
7
CP
8
IN
SSOP016-P-0225
(TOP VIEW)
R
16
15
14
13
12
11
10
9
IN
RSL
LC
FR
PS
LE
DATA
CLK
MN6155 For Communications Equipment
Block Diagram
DDVSS
V
4
FR
6
13
13-bit programmable counter
Switching
circuit
OP
VCPD
7
5
Phase comparator
17-bit latch
18-bit shift register
LC
14
Control
18-bit latch
FV
3
14-bit programmable counter
15
RSL
Swallow
counter
Prescaler and
phase adjustment
16
IN
R
3-bit counter
Phase
adjustment
Prescaler
1
2
IN
X
OUT
X
Data control
9
CLK
10
DATA
11
LE
12
PS
Swallow
counter
Prescaler and
phase adjustment
8
IN
F
For Communications Equipment MN6155
Pin Descriptions
Pin No. Symbol Function Description
1X
2X
IN
OUT
3 FV Frequency divider output signal in comparator stage.
4VDDPower supply
5DOPLow-pass filter connection pin. Use a passive filter.
6VSSGround
7VCPPower supply pin for built-in charge pump
8FINFrequency divider input pin in comparator stage.
9 CLK Shift register clock input pin.
10 DATA Shift register data input pin.
11 LE Load enable signal input pin.
12 PS Power save control signal input pin.
13 FR Reference frequency divider output signal.
14 LC Charge pump control signal output pin.
15 RSL Reference signal selection pin.
16 R
IN
Crystal oscillator connection pins:
XIN =Oscillator circuit input pin;
is attached to a pull-up resistor when the PS or RSL pin is at "L" level.)
(X
IN
X
=Oscillator circuit output pin.
OUT
Phase comparator input monitor.
The chip latches data at the rising edge of the CLK signal.
The final two bits in the data select the write latch:
"11" for R-latch; "01" for N-latch.
This is the latch-write-enable signal. It is at "H" level for write.
"H" level input starts the frequency divider and places the chip in operational
mode. "L" level input places the chip in standby mode, which saves power.
The chip switches the internal charge pump output to the H-z state and the loop
is opened.
Phase comparator input monitor.
When frequency divider operation is stopped, this pin is at "L" level, the
internal charge pump output is in the high-impedance state, and the loop is opened.
"H" level selects self-excited oscillator (X
and X
IN
OUT
).
"L" level selects external oscillator (RIN).
External reference oscillation input pin.
This pin is attached to a pull-up resistor when the PS pin is at "L" level or the
RSL pin is at "H" level.
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