Panasonic MN3890S Datasheet
CCD Delay Line Series
MN3890S
NTSC-Compatible CCD 1 H Video Signal Delay Element
Overview
The MN3890S is a 1 H image delay element of a 4 f
CMOS CCD and suitable for video signal processing applications.
It contains such components as a frequency-doubler
circuit, a shift register clock driver, a 906-stage CCD analog shift register, and a resampling output amplifier.
The MN3885S drives and samples the 906-stage analog shift register using a redoubled version of the supplied clock signal with a frequency 7.16 MHz of twice
the NTSC color signal subcarrier frequency , and after adding in the attached filter delay, produces a delay of 1 H
(the horizontal scan period).
Features
Single 5.0 V power supply
Energy-saving design based on CMOS process
Low EMI levels from clock during driving
Applications
VCRs, Video cameras
Structure and Operation
The MN3890S consists of the operational blocks shown
in the block diagram.
Frequency-doubler circuit
When the 7.16 MHz of the doubled NTSC color signal
subcarrier frequency is inputted from the clock input pin
XI, 14.32 MHz clock of fourfold frequency of color signal subcarrier is generated by this circuit.
Clock driver
This block generates two transfer clock signals, ø1 and
ø2, synchronized with the 14.32 MHz clock signal from
the frequency-doubler circuit.
It also generates the sampling clock signals øS and øS',
resampling clock signal øSH, and reset clock signal øR
that have adjusted timing relations with ø1 and ø2.
CCD analog shift register
This block first converts the analog signal fr om the V
input signal pin into a voltage signal, and inputs it into
906-stage analog shift register.
Pin Assignment
SC
BB
DD
1
IN
2
3
4
SS
8
7
6
5
( TOP VIEW )
SOP008-P-0225A
output pin at the point
O
V
V
V
V
The shift register samples the shift register input with
the sampling clock øS, and converts the results to char ges,
and uses transfer clocks ø1 and ø2 to transfer the results
to the following block, the charge detection block, where
the charges is converted into a voltage signal.
Resampling output amplifier
In the output amplifier, this voltage signal is done
Sample-and-Hold by resampling, and Y-signal as it is
outputted at Vo.
Operation
The following is an explanation of delay line operation.
The waveforms driving the shift registers are as shown
in the timing chart on page 622.
The input signal voltage sampled during the interval
between t=0 and t=τc (where τc is one-half the sampling
interval) appears at the V
t=1813τc.
IN
V
O
V
GC
PCOUT
&
VCOIN
XI
1
MN3890S CCD Delay Line Series
Block Diagram
DD
V
3
GC
V
7
Booster
Bias circuit
1
V
IN
Charge
input
CCD 906 stages
block
circuit
Charge
detection
block
Resampling
output amplifier
8
V
O
øS driver
Waveform
adjustment
block
ø1 driver
øR driver
øSH driver
Timing
adjustment
ø2 driver
øSH driver
XI
5
amplifier
adjustment
block
Phase
comparator
6
PCOUT
1/2nd frequency
doubler
VCO
&
VCOIN
Substrate bias
generator
4
SS
V
2
BB
V
Waveform
2
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