Panasonic MN3880S Datasheet
CCD Delay Line Series
MN3880S
NTSC CCD Video Signal Delay Element
Overview
The MN3880S is a CCD signal delay element for video
signal processing applications.
It contains such components as a shift register clock
driver, charge I/O blocks, two CCD delay elements, a
clamp bias circuit, resampling output amplifiers, and
booster circuits.
The MN3880S samples the input using the supplied
clock signal with a frequency of 7.15909 MHz, twice the
NTSC color signal subcarrier frequency, and after adding in the attached filter delay, produces independent delays of 1 H (the horizontal scan period) each for the two
lines.
Features
Single 4.9 V power supply
Single chip combining luminance signal delay
element and delay element for chrominance signal
after passing through a low pass filter
Applications
VCRs
Pin Assignment
VBIASC
VOC
N.C.
V
DD
–V
BB
N.C.
VOY
VBIASY
1
2
3
4
5
6
7
8
SOP016-P-0225
(TOP VIEW)
VINC
16
N.C.
15
N.C.
14
X1
13
V
12
11
10
9
SS
N.C.
N.C.
VINY
1
MN3880S CCD Delay Line Series
Block Diagram
VINC
XI
SS
V
12
Bias circuit
16
Charge
input block
øS driver ø1 driver ø2 driver øR driver
Timing adjustment
13
Waveform amplitude
adjustment block
Timing adjustment
CCD 454 stages
DD
V
4
Charge
detection block
VBIASC
1
Resampling
output amplifier
øSH driver
øSH driver
2
VOC
øSH driver
øSH driver
Resampling
output amplifier
8
VBIASY
7
VOY
VINY
øS driver ø1 driver ø2 driver øR driver
Clamp circuit
9
Charge
input block
5
BB
–V
CCD 454 stages
Charge
detection block
2
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