Panasonic MN3867S Datasheet

CCD Delay Line Series
MN3867S
PAL-Compatible CCD Video Signal Delay Element
Overview
The MN3867S is a CCD signal delay element for video
signal processing applications.
It contains such components as a threefold-frequency circuit, a shift register clock driver, charge I/O blocks, two CCD analog shift registers switchable between 1700 and 617 stages and between 848.5 and 617 stages, a clamp bias circuit, resampling output amplifiers, and booster circuits.
When the switch input is "L" level, the MN38667S samples the input using the supplied clock signal with a frequency three times the PAL color signal subcarrier fre­quency (4.43361875 MHz) and, after adding in the at­tached filter delay, produces independent delays of 1 H (the horizontal scan period) and 2 H for the two lines. When the switch input is "H" level, the MN38667S dis­ables the threefold-frequency circuit and samples the in­put with the image sensor drive frequency (9.65625 MHz) for the camera's 510 horizontal pixels and, after adding in the attached filter delay, produces independent delays of 1 H (the horizontal scan period) each for the two lines.
Features
Single 5.0 V power supply Choice of camera and VCR modes, so that both the
camera and VCR portions of a video camera with 510 horizontal pixels can use the same MN38667S for sig­nal processing
Pin Assignment
XIC
V
SS3
V
DD3
VINC1
N.C.
VINVC
VGC1 VO1C
V
DD1
V
SS1
1 2 3 4 5 6 7 8 9 10
SOP020-P-0300C
( TOP VIEW )
20 19 18 17 16 15 14 13 12 11
XIV
PCOUT
&
VCOIN
–V
BB
V
SS2
V
DD2
VINVY SW VINC2 VGC2 VO2Y
Applications
Video cameras
1
MN3867S CCD Delay Line Series
Block Diagram
DD1VSS1VDD2VSS2VDD3VSS3
VINVC
VINC1
VINVY
VINC2
XIV
XIC
6
4
15
13
20
1
V
9
Bias circuit
L
H
Waveform amplifier adjustment block
L
Phase comparator
3
10
16
17
2
Clamp circuit
Charge input block
Charge input block
Charge input block
Charge input block
1086-stage analog shift register
3-stage analog shift register
234.5-stage analog shift register
3-stage analog shift register
L
H H
L
L
H H
L
H
1/3rd frequency divider
H
VCO
L
Timing adjustment
19
Mode switch
L
H
L
H
L
H
L
H
Waveform adjustment block
L
H
SW
14
614-stage analog shift register
614-stage analog shift register
Booster circuit
ø1 driver
ø2 driver
Charge detector
Charge detector
VGC1
7
Voltage generator
Voltage generator
Resampling output amplifier
Resampling output amplifier
øS driver
øR driver
øSH driver øSH driver
Substrate bias generator
18
BB
–V
VGC2
12
11
8
VO1C
VO2Y
PCOUT & VCOIN
2
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