Panasonic AN8725FH Datasheet

ICs for Optical Disk Drive

AN8725FH

Semiconductor laser power control IC

■ Overview

The AN8725FH is a laser driver IC that can set a laser
emitting level to a maximum precision in recording and
playback of an optical recording equipment such as PD,
and can modulate a laser light in tune with the external
signal.

■ Features

• Digital setting of playback current, peak current, bias

current and abnormal light emitting level

• Peak current and bias current can be modulated by the

external signal.

• Driving current set-up (digital set-up)
For playback: 8-bit + 4-bit (0 mA to 80 mA)

5-bit + 4-bit (0 mA to 150 mA)
For peak: 4-bit + 8-bit (0 mA to 150 mA)
For bias: 4-bit + 8-bit (0 mA to 150 mA)

• Laser output light monitoring circuit built-in

• Abnormal light emitting detecting function built-in:

Possible to set up excessive and insufficient light emit­ting levels with 4-bit DAC for playback and recording,
respectively.

• Supply voltage abnormality detection:

Voltage down (3.9 V or less), voltage up (6.1 V or more)

14.00±0.20

12.00±0.20

60 41

61

80

120

(1.25)

0.50

+0.10

0.18

–0.05

Seating plane

QFP080-P-1212

40

(1.25)

21

0.90±0.10

0.90±0.10

14.00±0.20

12.00±0.20

1.95±0.20

0.50±0.20

0.10±0.10

Unit: mm

(1.00)

–0.05

+0.10

0.15

0° to 10°

■ Applications

• Optical disk drive

1

AN8725FH ICs for Optical Disk Drive

■ Block Diagram

IGND

AGND

PKMD

BIMD

RPHOLD

XWR

XRD

AD0
AD1
AD2
AD3

DT0
DT1
DT2
DT3
DT4
DT5
DT6
DT7

XLDEN

XCLR

XLDERR

XHFON

logic

CC

PKGND

PKV

72

BIV

71

77

4

Playback

current

5

DAC9

4

Playback

current

8

DAC1

8

Peak bias

4

current

DAC4

8

X1/SX2 changeover
AAF off
AAF RST
CTL SW6

DAC1

DAC9 DAC4

Current source for DAC

PS over

Supply voltage

PS down
WPW over

WPW down
RPW over
RPW down
Sleep

4

4

monitoring

Insufficient
light emission
DAC5

Excessive
light emission
DAC6

CC

LPF off

LPF off

DAC56SW

BIGND

RGND

76

62

Playback

current

DAC7

LPF9

Playback

current

DAC8

LPF1

Peak

current

DAC2

Bias

current

DAC3

Shunt circuit

SW5

Abnormal

light

emitting

detection

CC

RV

68

SW1

SW1

SW2

SW3

I/V

conversion

AAF

Sleep circuit

voltage source

BIDCP

78

Reference

(1.25 V)

PKDCP

73

64

Current

amplification

Current

amplification

Current

amplification

X1, X10

SW6

RDCP2

DAC7DAC8DAC2DAC3

Buffer

RDCP1

63

44
43

65

39
38

70
69

75
74

51
50

49
48

47
46

56
36

53
52
34

9

33
28
19
10

3
2

LPF92
LPF91

LDRP

LPF12
LPF11

XLDPK
LDPK

XLDBI
LDBI

IPD
IVIN
IVOUT
AAF
PWRMONI
DETMONI
VNR
VC
CV

CC

CGND

DV

CC

DGND

CC

AV

45

58

40

35
54

4
5
6
8
9

11
12
13
14

Control

15
16
17
18
22
23
24
25

26
27
29
32

30

31

PWMSK

ERFIL

55

ERREF

57

37

RREF

1

202141425960617980

SGND

DACMONI

2

ICs for Optical Disk Drive AN8725FH

■ Pin Descriptions

Note) Description on notations of "Category" in the following list:

IN : Input pin I/O : Input/output pin (pull-down with 100 k Ω)
IND : Input pin (pull-down with 100 kΩ) PS : Power supply/GND pin
INU : Input pin (pull-up with 100 kΩ) MSC: Parts connecting pin, etc.
OUT: Output pin

A: Analog function D: Digital function

Pin No. Symbol Category Description

1 SGND PS D Pin connected to the chip substrate.

Must be used in the same potential as other GND pins.

2 DGND PS D GND pin exclusive for a logic circuit.
3 DGND PS D Must be used in the same potential as other GND pins.

4 PKMD IND D Peak current modulation signal input pin.

In high-level, the current set up with DAC2 is superimposed on LD.

5 BIMD IND D Bias current modulation signal input pin.

In high-level, the current set up with DAC3 is superimposed on LD.

6 RPHOLD IND D Record gate signal input pin.

Inputs a low-level in playback and a high-level in recording.
Switches an amp. of light monitoring signal, abnormally emitted light
detection level and on/off of HF module.

7 XWR INU D Register writing signal pin.

Selects a register specified by address in a fall edge and writes a bus data
on the register of the address specified in the rise edge.

8 XRD INU D Register read-out signal pin.

Register data of the address specified in low appears on the bus.

9DVCCPS D Power supply pin exclusive for a logic circuit.

Must be used in the same potential as other power supply pins.

10 DGND PS D GND pin exclusive for a logic circuit.

Must be used in the same potential as other GND pins.

11 AD0 IND D 4-bit address pin for registers.
12 AD1 IND D Selects the register to be accessed.
13 AD2 IND D
14 AD3 IND D
15 DT0 I/O D Data I/O 8-bit bus pin.
16 DT1 I/O D The bus to set the data to be written on a register and to read out the data
17 DT2 I/O D of a register.
18 DT3 I/O D

19 DGND PS D GND pin exclusive for a logic circuit.

Must be used in the same potential as other GND pins.

3

AN8725FH ICs for Optical Disk Drive

■ Pin Descriptions (continued)

Pin No. Symbol Category Description

20 SGND PS D Pin connected to the chip substrate.
21 SGND PS D Must be used in the same potential as other GND pins.
22 DT 4 I/O D Data I/O 8-bit bus pin.
23 DT 5 I/O D The bus to set the data to be written on a register and to read out the data
24 DT 6 I/O D of a register.
25 DT 7 I/O D

26 XLDEN INU D LD enable input pin.

In a high-level or open mode, LD becomes off and open. This state is suited
to check the LD characteristics in keeping a connection to the IC. At the
time power off, both ends of LD are short-circuited by the IC for protection.
In the low-level, it returns to a normal operation.

27 XCLR IND D Clear signal input pin.

Sets an LDDENB register to "0" in the low-level and presets the status of
each DAC and each switch to an initial state as defined separately.
But six registers for an abnormal detection are not cleared. In this state,
each output of a current amplification 1, 2, 3 are in the off state and a
shunt circuit becomes on to continue to protect LD.
Setting this pin to the high-level and the LDDENB register to "1", it returns
to a normal operation.

28 DGND PS D GND pin exclusive for a logic circuit.

Must be used in the same potential as other GND pins.

29 XLDERR OUT D Laser abnormality detection output pin.

When a supply voltage or a laser light emission exceeds a fixed range, it
goes to low-level. A supply voltage abnormality is detected for the volt­age drop (3.9 V or less) or voltage rise (6.1 V or more). And an abnormal
light emission is detected for an excessive or weaker light emission set up
by 4-bit DAC5 and DAC6. This abnormality detection is latched so as to
prevent it from being reset until ERRCLR register is set to "1".
Further, each DAC output of a playback current, a peak current and a bias
current can be set to off, a shunt circuit be set to on and LD between anode
and GND be short-circuited by 100 Ω so that LD can be protected. This
protection function is latched to keep it from being reset until ERRCLR is
set to "1". Selection of either operation or non-operation for this opera­tion can be made by an STPMSK register.

30 PWMSK MSC D The pin to set up the mask time for a transitional response output that

comes out at switching a detection level of excessive or insufficient light
emission by RPHOLD. Set a mask time by an external capacitor between
PWMSK and DGND and the resistor (10 kΩ) inside the IC. This pin is for
a schmitt-trigger input.

4

ICs for Optical Disk Drive AN8725FH

■ Pin Descriptions (continued)

Pin No. Symbol Category Description

31 ERFIL MSC D Filter setting pin to avoid a detection error of laser abnormality caused

by noise.
Connect an external capacitor between ERFIL and DGND, and set a filter
together with a resistor (10 kΩ) inside the IC. This pin is for schmitt-trigger
input.

32 XHFON OUT D HF module on/off control signal output pin.

High corresponds to off and low to on.

33 DGND PS D GND pin exclusive to a logic circuit.

Must be used in the same potential as other GND pins.

34 DV

CC

PS D Power supply pin exclusive to a logic circuit.

Must be used in the same potential as other power supply pins.

35 AGND PS A GND pin exclusive to a analog circuit.

Must be used in the same potential as other GND pins.

36 VC MSC A Output pin for reference voltage (1.25 V).

Connects a capacitor C between this pin and AGND for de-coupling.

37 RREF MSC A

Reference resistor connecting pin to determine an output current for each DAC.
Connect a resistor of 10 kΩ between RREF and AGND.

38 LPF11 MSC A LPF characteristic setting pin for DAC1 and DAC8.
39 LPF12 MSC A Connect an external resistor between LPF11 and LPF12, and then

capacitor between LPF12 and IGND to set up a cutoff frequency.

40 IGND PS A GND pin for playback power supply setting DAC1, DAC9 and distur-

bance reduction LPF.
Must be used in the same potential as other GND pins.

41 SGND PS D Pin connected to the chip substrate.
42 SGND PS D Must be used in the same potential as other GND pins.
43 LPF91 MSC A LPF characteristic setting pin for DAC9 and DAC7.
44 LPF92 MSC A Connect an external resistor between LPF91 and LPF92 and then

capacitor between LPF92 and IGND to set a cutoff frequency.

45 AV

CC

PS A Power supply pin for an analog circuit, a reference supply voltage circuit, etc.

Must be used in the same potential as other power supply pins.

46 DETMONI OUT A Pin to monitor a signal for detecting abnormally emitted light.

In a playback mode, the signal output is five times that in recording
(ten times is posisible by a register setting). Has offset to VNR due to
being outputted through a buffer of transistors.

47 PWRMONI OUT A Laser emitting light monitor signal.

In a low-level of RPHOLD, the amplifier output has 10 times gain
compared with recording, and is equipped with AFF.

5

AN8725FH ICs for Optical Disk Drive

■ Pin Descriptions (continued)

Pin No. Symbol Category Description

48 AAF MSC A AAF characteristic setting pin for optical monitor circuit.

Connect an external resistor, capacitor between AAF and IVOUT and set
up a cutoff frequency.

49 IVOUT OUT A I to V conversion signal output pin.

Connect an external variable resistor between IVIN and IVOUT.

50 IVIN MSC A I to V conversion resistor connection pin.

Connect an external variable resistor between IVIN and IVOUT.

51 IPD MSC A Pin photo diode (PD) connection pin.

Connect a pin photo diode for detecting a semiconductor laser emitting
light. Connect anode to this pin.
Applicable to a source-type PD which has a typical value of 40 µA to
160 µA output in object lens output power of 1 mW.

52 CGND PS A GND pin in an optical monitor circuit.

Must be used in the same potential as other GND pins.

53 CV

CC

PS A Power supply pin in an optical monitor circuit.

Must be used in the same potential as other power supply pins.

54 AGND PS A GND pin exclusive to a analog circuit.

Must be used in the same potential as other GND pins.

55 ERREF IN A Abnormally emitting light detecting range setting pin.

Sets a full scale voltage of DAC5 and DAC6.
A setting range is VNR or more and input range of an external ADC
or less.

56 VNR IN A Reference level input pin for PWRMONI output.

Input a reference voltage of 1.25 V of an external ADC.

57 DACMONI OUT A DAC5, DAC6 monitor pin.

DAC5 voltage is outputted when DAC56 SW register is low, DAC6
voltage is outputted when DAC6 voltage is high.

58 AV

CC

PS A Power supply pin for an analog circuit, a reference supply voltage circuit, etc.

Must be used in the same potential as other power supply pins.

59 SGND PS D Pin connected to the chip substrate.
60 SGND PS D Must be used in the same potential as other GND pins.
61 SGND PS D

62 RGND PS A GND pin for the lead current setting DAC7 and DAC8.

Must be used in the same potential as other GND pins.

63 RDCP1 MSC A Pin to connect a de-coupling capacitor to protect the output current of

DAC7, the read current setting circuit, from disturbance by a switching
noise such as peak current.
(Connects a capacitor between RDCP1 and RGND.)

6

ICs for Optical Disk Drive AN8725FH

■ Pin Descriptions (continued)

Pin No. Symbol Category Description

64 RDCP2 MSC A Pin to connect a de-coupling capacitor to protect the output current of

DAC7, the read current setting circuit, from disturbance by a switching
noise such as peak current.
(Connects a capacitor between RDCP2 and RGND.)

65 LDRP OUT A Source type read current (DAC1, DAC7, DAC8, DAC9) output pin.

Possible to set up the range of 0 mA to 150 mA in the precision of 8-bit
+ 4-bit + 5-bit + 4-bit.
Output voltage range is 1.0 V to 3.5 V.

66 N.C. N.C. pin.
67 N.C. Open the pin or connect to GND.

68 RV

CC

PS A Power supply pin for read current setting DAC7, DAC8.

Consumes approximately a quarter of the necessary read current.
Must be used in the same potential as other power supply pins.

69 LDPK OUT A Source-type peak current (DAC2) output pin.

Possible to set the range of 0 mA to 150 mA in the accuracy of 8-bit.
The output voltage range is 1.0 V to 3.2 V.

70 XLDPK IN A Sink-type peak current output pin.

Approximately three fourths of LDRK output current are outputted from
this pin.

71 PKGND PS A GND pin of DAC2 in the peak current setting circuit.

Must be used in the same potential as other GND pins.

72 PKV

PS A DAC2 power supply pin in the peak current setting circuit.

CC

Consumes approximately a quarter of the setting current.
Must be used in the same potential as other power supply pins.

73 PKDCP MSC A Pin to connect a de-coupling capacitor to avoid the output current disturbance,

which is caused by a switching noise such as peak current, in peak current
setting circuit DAC2.
(Connects a capacitor between PKDCP and PKGND.)

74 LDBI OUT A Source-type bias current (DAC3) output pin.

Possible to set the range of 0 mA to 150 mA in the accuracy of 8-bit.
Output voltage range is 1.0 V to 3.2 V.

75 XLDBI IN A Sink-type peak current output pin.

Approximately three fourths of LDBI output current are outputted from
this pin.

76 BIGND PS A GND pin of a bias current setting circuit DAC3.

Must be used in the same potential as other GND pins.

77 BIV

CC

PS A Power supply pin of a bias current setting circuit DAC3.

Consumes approximately one fourth of a setting current.
Must be used in the same potential as other power supply pins.

7

AN8725FH ICs for Optical Disk Drive

■ Pin Descriptions (continued)

Pin No. Symbol Category Description

78 BIDCP MSC A Pin to connect a de-coupling capacitor to avoid the output current disturbance,

which is caused by a switching noise such as bias current, of a bias current
setting circuit DAC3.
(Connects a capacitor between BIDCP and BIGND.)

79 SGND PS D Pin connected to the chip substrate.
80 SGND PS D Must be used in the same potential as other GND pins.

■ Absolute Maximum Ratings

Parameter Symbol Rating Unit

Supply voltage V
Input voltage V
Outoput voltage V
Parts connecting pin voltage V
Supply current I
Pin current I

2

Power dissipation
Operating ambient temperature
Storage temperature

Note)*1: Except for the operating ambient temperature and storage temperature, all ratings are for Ta = 25°C.

2: The power dissipation shown is for the IC package in single unit at Ta = 75°C.

*

Refer to "■ Application Notes, 1. PD  Ta curves of QFP080-P-1212".

*

1

*

1

*

T
T

CC

OUT

MSC

CC

PIN

P

opr

stg

IN

D

7.0 V

− 0.4 to VCC +0.4 V

− 0.4 to VCC +0.4 V

− 0.4 to VCC +0.4 V

80 mA

−100 to +100 mA

600 mW

−20 to +75 °C

−55 to +150 °C

■ Recommended Operating Range

Parameter Symbol Range Unit

Supply voltage V

CC

■ Electrical Characteristics at VCC = 5.0 V, Ta = 25°C

Parameter Symbol Conditions Min Typ Max Unit

Supply current

Supply current I

Sleep mode supply current I

Reference voltage block

Reference voltage output V
Reference voltage variation ∆V

Maximum output current ∆V

8

XCLR = low, digital I/O pin = open,  20 30 mA

CC

IPD = 0 µA
Sleep = 1, IPD = 0 µA  34mA

SLP

REF

REFVCC

OMIREF

= 4.5 V to 5.5 V, I
= 4.5 V to 5.5 V ± 20

V

CC

I

= −1 mA to + 1 mA

REF

= −1.5 mA, ± 50 mV

difference from I

REF

4.50 to 5.50 V

1.20 1.25 1.30 V

= 0 mA ± 15 mV

REF

= 0 mA

ICs for Optical Disk Drive AN8725FH

■ Electrical Characteristics at VCC = 5.0 V, Ta = 25°C (continued)

Parameter Symbol Conditions Min Typ Max Unit

Digital block

High-level input voltage V

Low-level input voltage V

High-level input voltage V
(Schmitt-trigger input) V

Low-level input voltage V
(Schmitt-trigger input) V

High-level output voltage V

Low-level output voltage V

V

Input pull-up, pull-down R
resistance Pull-down: VIH = 5.0 V

Input leak I

Entire optical monitor

Offset voltage at playback V

Offset voltage at recording V

PMOFW

Gain ratio GR G

Maximum output voltage V

Minimum output voltage V

f characteristics at playback f

PMR AAF

f characteristics at recording f

Settling time at playback t

Settling time at recording t

PMSETR

PMSETW

To be applied to a digital input pin 0.8 ×  V

IH

V

CC

To be applied to a digital input pin 0.2 × V

IL

To be applied to PWMSK, ERFIL pin 0.8 ×  V

IHSHC

CC

To be applied to PWMSK, ERFIL pin 0.2 × V

ILSHC

OHIOH

OL1IOL

OL2IOL

PD

LKH

= −2 mA 0.8 ×  V

V

CC

= +2 mA 0.2 × V

= +0.5 mA 0.4

Pull-up: VIL = 0 V 75 100 125 kΩ

To be applied to a digital input pin, 80 µA
VOH = 5.25 V

To be applied to a digital input pin, 10

I

LKL

VOL = 0 V

VR1 = 1 kΩ, IPD = 0 mA −15  15 mV

PMOFR

VR1 = 1 kΩ, difference from an ideal −40 0 40
value at IPD = 100 µA to 200 µA

VR1 = 1 kΩ, IPD = 0 mA −15  15 mV
VR1 = 1 kΩ, difference from an ideal −20 0 20

value at IPD = 100 µA to 2 000 µA

PMR /GPMW

, 9.0 10.0 11.0 times

output = VNR +0.6 V to 2.0 V

PM max

VCC × VCC × V

0.73 0.78

PM min

VNR− V

AAF-off VR1 = 1 kΩ,46 MHz

−3 dB, IPD = 100 µA to 200 µA

OFF

VR1 = 1 kΩ, 6 7.5  MHz

PMW

−3 dB, IPD = 100 µA to 2 000 µA
VR1 = 1 kΩ, error ±0.5%,  200 400 ns

output variation: Range of 0 V to 2 V
VR1 = 1 kΩ, error ±0.5%,  200 400 ns

output variation: Range of 0 V to 2 V

V

CC

CC

V

CC

0.015

9

AN8725FH ICs for Optical Disk Drive

■ Electrical Characteristics at VCC = 5.0 V, Ta = 25°C (continued)

Parameter Symbol Conditions Min Typ Max Unit

Current amplification changeover

Gain at playback G
Gain at recording G
Gain ratio GR

I to V conversion block

Offset voltage V

DAC1 block

Resolution RES1  8  bit
Integral linearity error EL1 −1.0  10.0 LSB
Differential linearity error ED1 −1.0  1.5 LSB
Maximum output current I

Offset current I

I

LPF on/off gain ratio GR

Settling time t

DAC7 block

Resolution RES7  4  bit
Integral linearity error EL7 −1.0  1.0 LSB
Differential linearity error ED7 − 0.5  0.5 LSB
Maximum output current I

Minimum output current I

Settling time t

DAC8 block

Resolution RES8  4  bit
Integral linearity error EL8 −1.0  1.0 LSB
Differential linearity error ED8 − 0.5  0.5 LSB

Reg7 = "80h", IPD = 40 µA to 240 µA 9.0 10.0 11.0 times

IPDR

Reg7 = "C0h", IPD = 200 µA to 3 200 µA

IPDW

IPDGIPDR /GIPDW

VR1 = 0 Ω, IPD = 0 mA −15  15 mV

IVOF

DAC1 = "FFh", DAC8 [Fh], 70 80 90 mA

1max

0.9 1.0 1 . 1 times

9.0 10.0 11.0 times

DAC7 [0h], DAC9 [00h]
"00h" LPF-on, DAC8 [Fh], −1  1mA

1OF1

DAC7 [0h], DAC9 [00h],
DAC7, DAC8 characteristics included

"00h" LPF-off, DAC8 [Fh], −250  250 µA

1OF2

DAC7 [0h], DAC9 [00h]

DALGLPFON

/G

, 0.95 1 1.05 times

LPFOFF

input amplitude 0 V to 2 V
XWR ↑ to DAC1 [10h to 8Fh],  400 800 ns

SDA1

±2 LSB range, DAC7 [0h], DAC8 [Fh],
DAC9 [00h] LPF-off,
LPF11 pin open,

RDCP2 pin open

Set to DAC7 = "Fh", 133 150 170 mA

7max

DAC9 [1Fh], DAC1 [00h], DAC8 [0h]
Set to DAC7 = "0h", − 0.1 0 0.1 mA

7min

DAC9 [1Fh], DAC1 [00h], DAC8 [0h]
XWR ↑ to DAC7 [0h to Fh],  50 500 ns

SDA7

DAC9 [1Fh], ±0.5 LSB,
DAC1 [00h], DAC8 [0h]

10

ICs for Optical Disk Drive AN8725FH

■ Electrical Characteristics at VCC = 5.0 V, Ta = 25°C (continued)

Parameter Symbol Conditions Min Typ Max Unit

DAC8 block (continued)

Maximum output current I

Minimum output current I

Settling time t

DAC2 block

Resolution RES2  8  bit
Integral linearity error EL2 −1.0  5.0 LSB
Differential linearity error ED2 −1.0  1.0 LSB
Maximum output current I
Offset current I
Settling time t

DAC3 block

Resolution RES3  8  bit
Integral linearity error EL3 −1.0  5.0 LSB
Differential linearity error ED3 −1.0  1.0 LSB
Maximum output current I
Offset current I
Settling time t

DAC4 block

Resolution RES4  4  bit
Integral linearity error EL4 −1.0  1.0 LSB
Differential linearity error ED4 −1.0  1.0 LSB
Maximum output current I
Offset current I
Settling time t

DAC9 block

Resolution RES9  5  bit
Integral linearity error EL9 −1.0  1.0 LSB
Differential linearity error ED9 −1.0  1.0 LSB
Maximum output current I

Set to DAC8 = "Fh", 70 80 90 mA

8max

DAC1 [FFh], DAC9 [1Fh], DAC7 [0h]
Set to DAC8 = "0h", 4 5 6 mA

8min

DAC1 [FFh], DAC9 [1Fh], DAC7 [0h]
XWR ↑ to DAC8 [0h to Fh],  50 250 ns

SDA8

DAC1 [80h], ±0.5 LSB,
DAC9 [00h], DAC7 [0h]

DAC2 = "FFh", DAC4 [Fh] 133 150 170 mA

2max

DAC2 = "00h", DAC4 [Fh] − 0.1  0.1 mA

2OF

XWR ↑ to DAC2 [10h to FFh],  100 250 ns

SDA2

±2.0 LSB, DAC4 [Fh]

DAC3 = "FFh", DAC4 [Fh] 133 150 170 mA

3max

DAC3 = "00h", DAC4 [Fh] − 0.1  0.1 mA

3OF

XWR ↑ to DAC3 [10h to FFh],  200 450 ns

SDA3

±2.0 LSB, DAC4 [Fh]

DAC2 = "FFh", DAC4 [Fh] 133 150 170 mA

4max

DAC2 = "00h", DAC4 [Fh] − 0.1  0.1 mA

4OF

XWR ↑ to DAC4 [0h to Fh],  300 600 ns

SDA4

±0.5 LSB, DAC2 [FFh]

DAC9 = "1Fh", DAC7 [Fh], 133 150 170 mA

9max

DAC1 [00h], DAC8 [0h]

11