Orban 2200 User Manual

OPTIMOD-FM 2200 TECHNICAL DATA

Section 6

Technical Data

page contents

6-2 Specifications 6-5 Circuit Description

6-5 Overview 6-5 16.384MHz Oscillator and System Clocking 6-7 Control Circuits 6-9 User Control Interface and LED Display Circuits 6-10 L/R Input Circuits 6-13 L/R Output Circuits 6-17 Composite Output Circuits 6-18 DSP Circuits 6-20 Power Supply

6-1

6-22 Parts List

6-23 Obtaining Spare Parts 6-40 Vendor Codes

6-41 Schematics, Assembly Drawings 6-57 Abbreviations

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TECHNICAL DATA OPTIMOD-FM 2200

page

Specifications

It is impossible to characterize the listening quality of even the simplest limiter or compressor on the basis of the us ual sp ecific ations, b ecause su ch spec ificatio ns canno t adequate ly describe the crucial dynamic processes that occur under program conditions. Therefore, the only way to meaningfully evaluate the sound of an audio processor is by subjective listening tests.

Certain spec ific atio ns are presented here to ass ur e the eng ine er that they are reason able, to help plan the installation, and to help make certain comparisons with other processing equipment. Some specifications are for features that are only available on the 2200-D.

Installation

Analog Audio Input

Configuration: Left and r ight. Impedance: Electronically balanced 600 Ω or >10kΩ load imped an ce, jumper-sel ec table. Dynamic Range: >90dB. Common Mode Rejection: ≥70dB at 50-60Hz. ≥45dB at 60Hz-15kHz. Sensitivity: −20dBu to +20dBu to p roduce 10d B gain redu ction at 1kHz, software- a nd jumper-

adjustable.

Maximum Input Level: +27dBu. Connector: XLR-type, female, EMI-suppressed. Pin 1 Chassis Ground, Pins 2 (+) and 3

electro ni cally balanced, floating and symme t rical.

A/D Conversion: 18-bit. Filtering: RFI-filtered, with hig h-pass filter at 0.1 5Hz .

Analog Audio Output

Configuration: Left and right. Fla t or pre -emph as iz ed (at 50 µs or 75 µs), software-selectable. Source Impedance: 30Ω, ±5%, electronically balanced and floating. Load Impe dance: 600Ω or greater , ba la nc ed or unb al an ce d. Termination not req ui red. Output Level: Adjustable from −20dBu to +20dBu into 600Ω or greater load, software-adjust-

able.

Output Noise Level: ≤−90.0dB (Bypass mode, de-emphasized, 20Hz-15kHz bandwidth, ref-

erenced to 100% modulation).

Crosstalk: ≤−70dB, 20Hz-15kHz. Distortion: ≤0.05% THD (Bypass mode, de-emph as ized , 2 0Hz-15kHz bandwid th ). Connector: XLR-type, male, EMI-suppressed. Pin 1 Chassis Ground, Pins 2 (+) and 3 elec-

tronicall y balanced, fl oating and sy m metrical.

Filtering: RFI-filtered.

OPTIMOD-FM 2200 TECHNICAL DATA

Digital Audio Input (2200-D Only)

Configuration: Two-c hann el per AES/EBU-s tand ard. 20 -bit re solu tion . Sampling rate: 25-55kHz, automatically-selected. Connector: XLR-type, female, EMI-suppressed. Pin 1 Chassis Ground, Pins 2 and 3 trans-

former balanced and floating.

Input Reference Level: Adjustable from 0dBFS to −20dBFS, software-controlled.

Digital Audio Output (2200-D Only)

Configuration: Two-channel AES/EBU-standard. 18-bit resolution. Software-controllable for

flat, pre-emphasized to the selected processing pre-emphasis, J.17 pre-emphasized, or pre-emphasized to th e se le ct ed proc es sing pre-e mp ha si s pl us J.1 7 pre -emph as is .

Sampling rate: 32kHz, 44.1kHz, or 48kHz, software-selected. Connector: XLR-type, male, EMI-su ppressed. Pin 1 Cha ssis Ground, Pins 2 an d 3 transfor mer

balanced and floating.

Status Bits: AES/EBU status bits are implemented to con trol pre-emph asis in the Orb an 8208

digital Stereo Enco de r.

Output Level Adjus tment Output at 100% modulation , adjustab le from 0dBFS to −22.8dBFS,

software-controlled.

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Composite Baseband Outputs

Configuration: Two (2) ou tputs, eac h with an indep endent outp ut level c ontrol, ou tput amplif ier

and connec tor.

Source Impedance: 0Ω voltage sourc e or 75Ω (jumper-se lectable), single end ed, floa ting over

chassis gr o und.

Load Impe dance: 37Ω or greater. Term ination not required. Level (0Ω Source Impedance, 75Ω or higher Load Imp edance): Adjustable 0.4Vp-p to

8.8Vp-p with front panel multi-turn output level controls, one per output.

Pilot Level: Adjustable from 8% to 10%, softwa re-c ontrolled. Pilot Stability: 19kHz, ±0.5Hz (10 ° to 40° C). D/A Conversi on : 18-bit. Signal-to-Noise Ratio: ≥85dB (Bypass mode, demodulataed, de-emphasized, 20Hz-80kHz

bandwidth , ref erenced to 100% mod ulation, unwe ighted).

Distortion: ≤0.05% THD (Bypass mode, demodulated, de-emphasized, 20Hz-15kHz band-

width, refere nc ed t o 10 0% mod ul at ion, unweight ed ).

Stereo Separation: At 100% modulation = 3.5Vp-p, >60dB, 30Hz-15kHz, >65dB typical at

1kHz; at 100% modul ation = 1.0Vp-p, >50d B, 30 Hz-15kHz.

Crosstalk (Linear): ≤−80dB, main channel to sub-ch annel or su b-channel to main ch annel)

referenced to 100% modulation).

Crosstalk (Non-Linear): ≤−80dB, main channe l to sub -ch anne l or su b-cha nnel to ma in ch an-

nel) referenc ed to 100% modulat io n).

38kHz Suppression: ≥70dB; 75dB typical (referenc ed to 10 0% modul at io n).

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TECHNICAL DATA OPTIMOD-FM 2200

76kHz and Sideband Suppression: ≥70dB; 80dB typical (referenced to 100% modulatio n). Connector: BNC, floating over chassis ground. EMI-sup pre ssed . Maximum Load Capacitance : 0.047µF (0Ω source impedanc e). Maximum Recommended Cabl e Le ngth (0Ω Source Impedance): 100ft/30m RG-58A/U. Filtering: RFI-filtered.

Remote Control Interf ace

Configuration: Eight opto-isolated inputs, user-programmable to select any eight of: User

Presets, Factory Presets, Bypass, Tone, Exit Test (returns from Bypass or Tone), Stereo, Mono from Left, Mono from Right, Mon o f rom Sum, I np ut Ana log, In pu t Di gita l.

Control: Momentary or continuous low side contact closure. 10mA minimum sink current;

9VDC, 50mA rating.

Power Supply: Current-Limited 9VDC provided to facilitate use with contact closure. Connector: DB-25, EMI-suppressed. Filtering: RFI-Filtered.

Power

Voltage: 90-120VAC, 100-132VAC or 200-264VAC, 50-60Hz; 40VA. Connector: IEC; detachable 3-wire po wer cord supplied. AC is EMI-suppressed. Ground: Circuit ground is independent of chassis ground; can be isolated or connected with a

rear panel switch.

Safety Standards: UL, CE, CSA.

Environmental

Operating Temperature Range: 32° to 122°F/0° to 50°C at nominal operating voltages. Humidity: 0-95% RH, non-condensing. Dimensions (W x D x H ): 19“ x 14.25” x 1.75“/4 8. 3c m x 36 .2 cm x 4.5 cm. 1 rack unit high. Weight: 12 lbs/5.4k g. Shipping W ei ght: 15 lbs/6.8kg.

Warranty

One Yea r, Parts an d L ab or: Subject to the limitations set forth in Orban’s Standard Warranty

Agreement.

Specifications are subject to change without notice.

OPTIMOD-FM 2200 TECHNICAL DATA

Circuit Description

This section provides a detailed description of circuits used in the 2200/2200-D. It starts with an overview of th e 2200/2200-D system, iden tifying circuit sections and des cribing their purpose. Then each s ection is treated in deta il by first giving an overv iew of the circuits followed by a component-by-component description. Keywords are highlighted throughout the circuit descriptions to help you quickly locate the information you need.

Overview

The block dia gram on page 6-35 illustrates the following overview of 2200/2200-D circuit sections.

The 16.384MHz Oscillator and System Clocking section provides the various clocks needed by the control, I/O and DSP circuits to carry out their functio ns.

The Control Circuits administrate control of the 2200/2200-D system.

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The User Control Interface and LED Display Circuits section includes the connector, RF-filtering, and circuitry for the remote control inputs. It also includes circuitry for the front panel pushbutton switches, LED control status indicators, and LED Meters. The LED Meters measure various 2200/2200-D signal levels and display the results on six front panel 10-segment LED meters.

The L/R Input C ircuits include the conn ector s and R F-f ilter ing for th e le ft and rig ht aud io inputs and the dig ital audio input, and the circuitry to interface thes e inputs to the digital processing.

The L/R Output Circuits in clude the connec tors and RF-filter ing for the le ft and right audio outputs and the digita l audio ou tput, a nd the circu itry to interfa ce the digital pr ocessin g to these outputs.

The Composite Output Ci rcuits include the conn ectors and RF-filtering for the two co mposite outputs, and th e circuitry to inte rface the digita lly processed, s tereo encoded s ignal to these outputs.

The DSP Circuits implement the bypass, test tone, audio processing, and stereo encoding functions using digital signal processing.

The Power Supply provides power for all 2200 /2200 -D circu it section s.

16.384MHz Oscillator and System Clocking

A synchronous clocking scheme is used on the 2200/2200-D to eliminate any asynchronous clocks operating in the sensitive regions of the L/R input A/D converter. A single

16.384MHz crystal oscillator provides the timing reference for all system digital clock signals. The only clocks that run asynchronous to this clock are the AES/EBU digital audio input related clocks and the 11.2896MHz free running crystal clock oscillator providing the

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TECHNICAL DATA OPTIMOD-FM 2200

44.1kHz AES/EBU output sample rate (this does not fall within a sensitive region of the A/D). Synchronous counters are used to divide the 16.384MHz clock to produce the various clock signals for the sys tem. A PLL cir cuit is u sed to synth esize an 18.432MH z clock fo r operating the host microprocessor and a 6.144MHz clock for providing the 48kHz AES/EBU output sample rate clock in addition to providing the AES/EBU input receiver with the ability to measure the input sample rate.

Component-Level Description:

The 16.384MHz digital output from crystal oscillator Y602 feeds the master clock (MCLK) inputs of both the input and the output SRC chips IC603 and IC615. The 16.384MHz clock also feeds flip-flop IC604, which divides by two to produce an 8.192MHz clock. The 8.192MHz clock feeds digital multiplexer chip IC610, which routes the 8.192MHz to AES/EBU digital audio transmitter chip IC616 when an internally generated 32kHz output sample rate is selected. The 8.192MHz clock is also sent to an 8-bit synchronous counter implemented in programmable logic array (PLA) IC61 3.

This counter divides down to obtain the lower frequency system clocks. All outputs of the PLA have their transitions coincident with the rising edge of the

8.192MHz clock. The 8.192MHz clock is inverted by buffers IC605-A, -B to provide clocks 8.192MHZA* and 8.192MHZB* that have falling edges coincident with the transitions of the lower frequency clocks. 8.192MHZA* feeds the bit clock of the inter-DSP communication links following buffers IC710-B, -D.

8.192MHZB* feeds th e A/D input c lock (2 56 x sample rate ), the L/R outp ut D/A master clock, and the input bit clock on both the L/R output D/A and the composite D/A.

The 2.048MHz clock output from IC613 feeds the PLL circuit made up of PLA IC618, 74HC4046 phase detector/VCO IC619 and associated components. The PLA f irst buffers the 2.048MHz signal, providing a clean 2. 048MHz output at pin 12 used as the reference input to the PLL phase detector (IC619 pin 14). Of the three detecto rs inclu de d in the 7 4HC40 46, the p hase fre quen cy dete cto r (PFD) is used by the 2200/22 00-D. The output of the phase dete ctor (pin 13) feed s the loop filter made up of resistors R607, R608 and capacitor C605 that provide a single pole low-pass filter forming a second order loop. Pin 9 of IC619 is the input control voltage to the VCO. Resistor R614 eliminates subharmonic frequency modulation of the VCO caused by parasitic capacitance. Resistors R605 and R606 set the PLL’s lock-in frequency range. A divide-by-nine counter is placed between the VCO output and th e phase detec tor comparator input. This pla ces the VCO output at 18.432MHz. The divide-by-nine is implemented by the PLA IC618 between pins 2 and 15. A 6.144MHz clock is derived at the counter’s divide-by-three point and is provided at pin 17 of the PLA. The PLA provides a buffered 18 .432 MHz outpu t at pin 14 which fee ds Z-180 microp roce ssor IC100.

IC614-A, -D provide buffered clocks 2.048MHZA and 2.048MHZB for driving the EXTAL inputs (pin 27) of the DSP chips. Ea ch b uffer drives fou r DSP chips.

The 256kHz clock output of IC6 13 (pin 15) is require d for the DSP-to -composite D/A interface. The 128kHz clock (pin 14) is used for the inter-DSP word clock. The 128kHz, 64kHz and 32kHz clocks are all used in the LCD backlight drive

OPTIMOD-FM 2200 TECHNICAL DATA

circuit. The 32kHz clock is also used for the input word clock of both the output sample-rate converter (SRC) and the L/R output D/A. The 32kHz clock is used to generate DSP inter rupt request sign als (IRQBA, IRQBB) required for proce ss timing and interchip synchronization. The circuit consisting of flip-flop IC612 and IC614-B, -C is required to ensure that the first falling edges of all IRQB signals are coincide nt. This synchro nization occurs e very time the u nit is powered up and when there is a proc essing a lgorithm c hange. It is contr olled by the Z -180 via pin 2 of latch IC611. The 32kHz clock is also used, along with IC313, in the A/D clock synchronizing circ uit. This circuit makes th e IRQB and the L/R clo cks, both operating at 32kHz, phase synchronous. This ensures that the process-tooutput buff er tran sfer inter nal to the DSP doesn’ t over lap the output buf fer -to-peripheral tran sf er. The 8.192MHZB* clock that feed s th e A/D in pu t clock (IC312 pin 19) is internally divided down to produce a 32kHz word clock at IC312 pin 13 and a 2.048MHz bit clock at pin 14. These clocks are used to control the A/D-to-DSP seria l in ter fa ce and the input SRC-to-DSP se rial interface.

AC terminations are used on various clocks throughout the board to improve signal integrity for sensitive devices.

Control Circuits

6-7

The control circuits process and execute user-initiated requests to the system. The source of these reque sts is the front panel buttons and the remote contact closures . These changes affect hardware function and/o r DSP processi ng. Th e co ntrol circuits al so send informa tion to the LCD display, LED status, and LED meter circuits. A RAM chip sto res code segments. For quick access, an EEPROM ch ip stores dy namic s ystem st ate inform ation. A ROM c hip contains the exec ut a ble form of 22 00 /22 00 -D DSP and Cont rol so ftwa re .

1. Microprocessor and Power Monitoring Circui t

A Z-180 microprocessor executes software code required to control the functionality of the 2200/2200-D. The EXTAL po rt of the Z-180 receives an 18.432MHz clock sign al from the clock divider/PLL circuit and is internally divided down to 9.216MHz to provide the Z-180 system clock frequency. ROM contains control software for the Z-180. User system setup and other dynamic system state information that must survive power down is stored in non-volatile EEPROM. Power monitoring circuitry prevents data co rruption by placi ng and holding the Z-180 in reset if AC mains power is insufficient.

The Z-180 communicates to the DSP through the synchronous serial data host port. When the DSP requires executable code, the Z -180 reads it from the ROM and sends it to the DSP. The Z-180 sends parameter contr ol dat a to the DSP and receive s stat u s data fr om the DSP. If status from DSP is irregular, the Z-180 will place the 2200 /2200-D h ardware and DSP in a reset state and execute initialization procedures.

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TECHNICAL DATA OPTIMOD-FM 2200

Component-Level Description:

The Z-180 is IC10 0. Watchdog timer/voltage monitor IC122 provides th e system reset function. IC122 pin 7 monitors pulses generated every 1 second by the Z-180. If the Z-180 is not operating correctly to provide the pulses, IC122 will reset the Z-180. IC12 2 also mo nitors the voltag e o n the +5V source that supplies power to the 2200/2200-D digital electronics. When the +5V line is above the minimum operating voltage of +4.75V, R103 will pull RESET* high which allows the Z-180 to exit the reset condition. When the +5V line is below the minimum operating voltage, the open-collector output of IC122 pulls Z-180’s RESET* low which puts the Z-180 into the reset condition, thereby preventing the Z-180 and the 2200/2 200-D electron ics from executin g incorrectly d ue to low +5V line voltage.

Z-180 IC100 pins 55, 56, and 57 comprise the host serial data communication port. The Z-180 uses this port to communicate with the DSP IC700-IC707 via host port interface pins 26, 35, and 41; and with EEPROM IC107 via pins 2, 5, and 6. Communication is SPI type with Z-180 as master and DSP as slave.

2. RAM, ROM and EEPROM

A RAM chip provides temporary storage for Z-180 data and program code segments. A ROM chip provides permane nt storage of the executable control software and the executable DSP software. System state information that mus t be maint ained while the 22 00 /2200 -D is powered down is stored in a EEPROM. The EEPROM does not lose data when the 2200/2200-D is po wer ed down .

Component-Level Description:

IC104 decodes Z-180 memory addresses to access instructions to execute from ROM IC105 and to read or write data from 32KB RAM IC10 6. EEPROM I C107 is selected by latch IC611 pin 6.

3. Data Latches, Tri-State Data Buffers and Address Decoders

Digital logic decodes Z-180 I/O addresses, allowing the Z-180 to access RAM, ROM and EEPROM. The logic provides Z-180 data bus allocation by using latches and tri-state data buffers to allow other 2200/2200-D hardware to communicate to the Z-180. To control other hardware, the Z-180’s data bus state is latched at the appropriate time, and the latched control signals are provided to other hardware. For the Z-180 to read information from other hardware, the Z-180’s data bus is connected at appropriate times to other hardware’s source signals throug h tri-state data buffers (e.g. IC120).

Component-Level Description:

Decoder IC104 allows the Z-180 to access ROM IC105 and RAM IC106. Decoders IC101, IC102, and IC103 allow the Z-180 to access all other

OPTIMOD-FM 2200 TECHNICAL DATA

2200/2200-D h ard ware . T he deco de d outpu t s fr om I C1 01, IC10 2, a nd IC1 03 a re used to latch the state o f the Z -180 data bus at a ppropriate tim es with d ata latch es IC202, IC205, IC207, IC303, IC305, IC609, IC611, IC708, and IC709, and to allocate the Z-180 data bus at appropriate times to various pe ripherals via tr i-state data buffers IC120, IC204, and IC601. IC120 buf fers or tri-states status in formation from the remote contact closure circuitry onto the Z-180 data bus. IC204 buffers or tri-states information from the user control interface onto the Z-180 data bus. IC601 buffers or tri- sta tes sta tus information from AES/EBU Receiver IC600 onto the Z-180 data bus.

User Control Interface and LED Display Circuits

The user contro l inter face enable s the use r to contr ol the fun ctiona lity of the 22 00/22 00-D unit. A rear pane l remote interf ace connecto r enables remo te control of cer tain functions. Front panel pu shbutton switches s elect between various op erationa l modes and f unctions. Data latches detect and store the commands entered with these switches. Front panel status LEDs indicate the c ontrol status of the unit, and mete r LEDs indicate signal levels and processing activity within the unit.

6-9

1. Remote Interface

A remote interface connector and circuitry enables remote control of certain operating modes; the 2200 has eight remote contact closure inputs.

A valid remote signal is a momentary pulse of current flowing through the particular remote signal pins. Cur rent must flow con sistently for 50 msec for the signa l to be interpreted a s valid. Generally, the 2200/2200-D will respond to the most recent control operation whether it came from the front panel, or remote interface.

Component-Level Description:

J101 is a 25-pin D-connector that c on ne cts the re mo te c on tro l inp ut signals. The connector incorporates a ferrite block to filter out RFI from the signals. The associated opto-isolato rs (e.g. IC1 10) isolate the inputs f rom the detector circuitry on the 2200/2200-D. The associated diodes (e.g. CR10 2) pr event the opto-iso lators from breaking down under a reverse bias. The outputs of the opto-isolators are inverted and buffered (e.g. by IC118-A) and latched by tri-state data buffer IC120. When RE MOTE* sign al p rovid ed to IC120 pin 19 i s broug ht low, IC120 places r emote sign als on the Z- 180 data bu s.

2. Switch Matrix and LED Indicators

Ten front pane l pushbu tton switche s are ar ranged in a matrix, co nfigure d as two column s and six rows (the FUNCTION and CONTRAST keys ha ve dedicated rows). These switches are the primary element of the physical user interface to the 2200/2200-D control software. The host microprocessor controls the system setup an d function of the DSP a ccording to the switch/rotary encoder ente red commands, the AES Status b its from the Di gital Inpu t signal,

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TECHNICAL DATA OPTIMOD-FM 2200

and the remote control interface status; and updates the LED control status indicators accordingly.

Component-Level Description:

S200-S208 and S210 a re the front panel pushbutto n switches. CR200 -CR204 and CR206 are the front pa ne l LED control status in dicators. Via decoder I C1 02 , the host microprocessor Z-180 periodically selects data latch IC202 (on the display board) to drive o ne of the two c olu mns in the switc h matr ix low, then commands tri-state data buffer IC204 (also on the display board) to read its inputs to determine if any new information is being received from one or more of the switches in that column. If no switches are closed, pull-up resistors R202, R210-R213 pull the buffer inputs to +5V. Th e buffer, in turn, de-boun ces the signals and place s the appro priate word on th e data bus f or the Z-1 80 to rea d. The Z-180 transmits the update d information to data latch IC202 which directly drives the LED Control Status Indicators.

3. LED Meter Circuits

The meter LEDs are arranged in an 8x8 matrix, in rows and columns. Each row of LEDs in the matrix has a 1/8 duty cycle ON time. The rows are multiplexed at a fast ra te so that the meters appear continuously illuminated. Via the serial port, the DSP sends meter data values to the Z-180, which a lterna tely sends pairs o f mapped 8-bit wo rds to the data bus . One of the words, latched by a “row selector” latch, has a single rotating active bit to select one of the 8 rows. The other word, latched by a “column selector” latch, has active bits corresponding to those of the 8 LED s in the s electe d row th at are to be lit. Th e latch ed words co ntrol high-current Darlington transistor arrays which drive the LED matrix.

Component-Level Description:

The meter LED matrix consists of six 10-segment LED bargraph assemblies (CR208-CR213) and thr ee discre te LEDs (CR214 -CR216). IC20 8 contains e ight Darlington transistors, each of which is connected to the cathodes of a “row” of the LEDs. Row selector latch IC207, controlled by the Z-180, alternately turns one of the eight transistors on, such that it will sink current through the LEDs selected by column selector latch IC205, also controlled by the Z-180. IC205 turns on the appropriate transistors inside current driver IC206 to drive the selected row of LEDs. IC206 ge ts its current from a storage cap acitor fed dire ctly by the power transformer’s lower voltage secondary winding. Resistors RP200 function as current limiting resistors.

L/R Input Circuits

This circuitry interfaces the analog and digital audio to the DSP. The analog input stages scale and buff er the input au dio level to match it to the ana log-to-d igital (A/D) co nverter. The A/D converts the analog input audio to digital audio. The digital input receiver accepts AES/EBU-format digital audio signals from the digital input connector, an d transmits them

OPTIMOD-FM 2200 TECHNICAL DATA

to the input sample rate converter (SRC). The digital audio from the A/D and SRC is transmitted to the DSP.

1. Analog Input Stages

The RF-filtered left an d righ t an alog input sig nals ar e each applied to a resisto r load and a resistor pad. The pad and lo ad are enabled or disabled by jumpers that are positioned b y hand. The loaded and padded signal is applied to a floating-balanced amplifier that has an adjustable (digitally-controlled) gain. The gain is set by FET transistors and analog switches. The state of the FETs and switches is set by the outputs of a latch. The control circuits control the gain according to what the user specifies from the front panel controls by writing data to the latch. The g ain amplif ier output fe eds a cir cuit that sc ales, balan ces, and remo ves DC from the signal. This circu it feed s an RC low-p ass filte r which ap plies the balanc ed sign al to the analog-to-digital (A/D) converter.

Component-Level Description:

The left channel balanced audio input signal is applied to the filter/load/pad network made up of L300, L301, L302, L303 , R300-R305, C323 and C324. J301 is a jumper that re moves or inse rts the optional 600Ω ter minatio n load (R30 0) on the input signal. J302 and J303 are the jum pers tha t remove or insert the resistive divider (R301-R303) that pads the input signal before it is applied to IC300, a differential amplifier. R306, R307, R310-R313, FETs Q300-Q301, and quad analog switch IC307 make up the circuit that sets the gain of IC300. The FETs, along with IC307, are used as switches to chan ge the resistive paths in the circ uit. The state of the FET switches is set by the outputs of digital latches IC304 and IC305. The latch outputs feed IC306, a quad comparator, which outputs 0V to turn on a F ET and −15V to turn off a FET. The control circuit writes directly to IC307 to control the state of the switches on IC307. IC300 feeds IC302 and associated components. This stage balanc es the signal and attenua tes by 3.5dB to scale the signal to the proper level for the analog-to-digital (A/D) converter. IC301-B and associated components comprise a servo amp to prevent DC from passing to the DSP. R334, R337, C302, and C303 make a simple RC filter necessary to filter high frequency energy that would otherwise cause aliasing distortion in the A/D converter. The corresponding right channel circuitry is functionally identical to that just described.

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2. Stereo Analog-to-Digital (A/D) Conve rter

The A/D is a ste reo, 18-bit sigma- delta converte r, implemented on a dual-chip integr ated circuit. The A/D oversamples the audio at 2.048MHz. It applies noise shaping, then it filters and decimates to a 32kHz sample rate. The samples are output in two’s complement, 32-bit word, two-word frame serial format, with SPI compatible timing, MSbit first, and transmitted to the DSP. The 32kHz frame clock and 2.048MHz bit clock from the A/D function as master clocks for the 2200/2200-D inp ut to the DSP. For more information on 2200/2200-D input clocking, please refer to “16.384MHz Oscillator and System Clocking.”

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TECHNICAL DATA OPTIMOD-FM 2200

Component-Level Description:

The balanced left analog input is applied to pins 3(+) and 4(-), and the balanced right analog input is applied to pins 26(+) and 25(-) of the A/D (IC312). The maximum differential signal that the A/D can accept is ±7.36Vpeak. The A/D samples the left and right inputs simultaneously at 64 times the 2200/2200-D sample rate of 32kHz . ICL KD, th e m aster clock input of the A/D (p in 19), is f ed an 8.192MHz clo ck providing the 2.048MHz input sample r ate required . The A/D sends the digitized stereo audio to the f irst DSP chip (IC700) via its syn chro nous serial port formed by the data SDATA (pin 15), the bit clock SCLK (pin 14) and the word clock L/R* (pin 13). The SPI communication standard is used for this audio interface, with A/D as master and DSP IC700 as slave. The SPI format is: 32-bits/word, multiplexed stereo, word clock low represents left data present, MSB first, data transitions occur on rising edge of the bit clock, first 18 bits are valid, trailing bits ar e set low , MSB de layed one bit p eriod from word clock edge. IC314 provides buf ferin g to re duce the drive requ ireme nt of the on-bo ard dr ivers on the A/D and to ensure that there are no overshoots or undershoots as a result of transmission line reflections that may degrade the performance of the A/D. IC109-D is required to invert the word cloc k to suppor t the SPI inte rf ac e.

3. Digital Input Receiver and Sample Rate Converte r (SRC)

The digital input receiver accepts digital audio signals using the AES/EBU interface format (AES3-1992). The rec eiv er a nd in pu t s amp le ra te conv er ter (SRC) tog eth er wi ll ac ce pt a nd sample-rate con ve rt any of the “s tan da rd ” 32kHz, 44 .1kHz, 4 8kHz r ate s in ad dition to an y digital audio sa mple rate within the r an ge o f 25 kHz a nd 5 5kH z. The au dio sig na l re ce ive d is decoded by the AES receiver and sent to the SRC. The SRC converts the input sample rate to the 32kHz 2 200- D sy ste m sample rate. Via a sy nc hr on ou s s er ial in terface, the SRC sends the 32kHz sample rate audi o to the DSP for proc essin g.

Component-Level Description:

The differential digital input signal is received through a shielded 1:1 pulse transformer (T600). T600 has very low inter-winding capacitance, providing a high level of isolatio n for hig h fre quency com mon mo de in ter fere nc e. I C600 is a dedicated AES/EBU digital audio receiver integrated circuit. It contains a phase locked loop that recovers the clock and the synchronization information present in the AES/EBU signal. A Schmitt trigger at the input provides 50mV of hysteresis for added noise immunity. R600 provides a 110Ω input impedance per the AES/EBU specification.

The Z-180 provides the active high reset signal (AES_RST) to IC600 mode control pins 17, 18, an d 2 3, via latch IC609 pin 6. Thi s is used when the 2200-D is asked to respond to analog audio input. When in the reset state, the receiver holds all outputs inactive (except MCK pin 19).

IC600 pins 2 through 6 and pin 27 are an output latch that provides AES/EBU status information, selected by the STATSEL line. The information on this latch is provided to the Z- 180 data bus via tr i-state data buf fer I C601. STA TSEL signal

OPTIMOD-FM 2200 TECHNICAL DATA

from IC611 pin 12 is applied to IC600 pin 16. When STATSEL is high, pins 2 through 6 and pin 27 contain information about the channel status bits. When STATSEL is low , pins 2 through 6 and pin 27 c ontain in put sam ple r ate a nd e rror information. The Z-180 reads these to determine if a valid AES/EBU signal and sample rate is present. CHSEL is used to select whether channel A or channel B status bits are present on IC600’s output latch. When STATSEL is low, left channel status is made available , and when STAT SEL is high , right channel sta tus is made available.

Received AES audio is tr ansmitted from the AES r eceiver to the in put sample rate converter (SRC IC603), in the sync hr onou s seria l SPI f or ma t. T he AES r ec eiver is master and the SRC is slave. The AES receiver outputs data on pin 26, the bit clock on pin 12, and the frame clock on pin 11. The frame clock is inverted by IC605-F for compatibility with the SRC’s input port. These signals ar e sent to the SRC serial input interface pin s 3, 4, and 6 respectively.

The MCK clock output at pin 19 of the AES receiver chip has a frequency 256 times the input sample rate of th e receiv ed sig nal. This is use d to drive the outpu t AES/EBU transmitter when an output sa mple rate that is synchro nous to the input sample rate (extern al sync ) i s requ ire d.

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The crystal oscillator (Y602) provide s the SRC a maste r clock of 16.384MHz on pin 2. This MCLK frequency allo ws th e in pu t S RC to ope ra te with in pu t sam ple rates in the range of 8.192kHz (MCLK/20 00) to 57kHz (MCLK/286). S RC_RST is an active low reset sign al tied to pin 13 of the SR C. This signal is con trolled by the Z-180 via pin 2 of latch IC609.

The MSDLY _I, BKPOL_I, and TRGLR_I pins of the SRC chip configure the chip for SPI format. Pin 1 of the SRC (GPDLYS) is tied high to minimize the chip’s group delay to approximately 700µs as opposed to approximately 3ms, giving up some tole rance to variations in sample rates. Pin 28 (SETLSLW) is tied high to cause the SRC to settle slowly to cha nges in sample rates, resultin g in the best rejection of sample rate jitter.

The sample rate converted output of the input SRC feeds the first DSP chip (IC700). The SRC output port and the DSP input port ar e both slaves, with clocks supplied by the L/R input A/D converter (IC312). The SRC generates DIG_IN (data) on pin 23, and receive s the bit cloc k and the word clock on pins 26 and 24 respectively. An inverted version of this word clock is used by the DSP chip to conform with the SPI format it requires.

L/R Output Circuits

This circuitry interfaces the DSP to the analog and digital audio outputs. The digital audio from the DSP is transmitted to the digital-to-analog converter (D/A) and output sample rate converter (SRC). The digital-to-analog (D/A) converter converts the digital audio words generated by the DSP to analog output audio. The MDAC stages scale and buffer the D/A output signal to drive the analog output stages to the correct level. The analog output stages drive the analog output XLR con nectors with a low impedance , floating balance d output. The digital output transmitte r accepts th e digital audio words from th e output sample ra te

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TECHNICAL DATA OPTIMOD-FM 2200

converter (SRC) and transmits them in AES/EBU-format digital audio signals on the digital output connector.

1. Stereo Digital-to-Analog (D/A) Converter

The D/A is a single chip, stereo, 18-bit delta-sigma converter. For informatio n on 2200 /2200-D s ystem clockin g, please r efer to “ 16.384MHz O scillator

and System Clocking.”

Component-Level Description:

IC400 is the digital-to- analog (D/A) converte r for the left a nd right output signals. The synchronous serial input interface consists of the bit clock, data and latch enable pins that are configured for the SPI format via DIF0 and DIF1 pins (for details on SPI, see page 6-11). The processed digital output (ANLG_OUT) is provided by DSP I C706 on its SAI outpu t port SDO0 (pin 4 7), and is rece ived by the D/A on pin 18.

An 8.192MHz bit clock is provided from the system clock circuitry to both the DSP and the D/A c hips. The DSP output d ata format is SPI (32 bits pe r word, two words p er frame) . DSP chip IC70 6 receives a 128kHz fr ame clock at its WST input (pin 50) that sets the word transfer rate to eight words per 32kHz period. The D/A receiv es a 32kHz clo ck at its LRCK in put (pin 20). LRCK delinea tes the left and right samples used by the D/A; therefore the D/A uses the first sample received for the left output and the fifth sample for the right output. The DSP output samples are formatted to ensure that the D/A uses a left and right output pair that represent the simultan eo usly sa mp led ana log input.

2. Analog Output Stages

The left and rig ht analog signals eme rging fro m the digita l-to-analog (D/A) conv erter ar e each RC low-pass filtered and applied to an inverting amplifier having an adjustable (digitally-controlled) gain. The gain is set by an MDAC. The state of the MDAC is set by the outputs of a latch. The control circuits control the gain according to what the user specifies from the front panel controls by writing data to the latch. The gain amplifier feeds a programmable d e-emphasis f ilter stage with its response dig itally-controlled by JFET switches. Th e de -emphasis stage f ee ds a floating-b ala nc ed lin e d riv er , h aving a 30Ω, ±5% output impedance. The line driver outputs are applied to the RF-filtered left and right analog output connectors.

Component-Level Description:

The left channel signal emerging from the digital-to-analog (D/A) converter is RC low-pass filtered by R402 and C407 to remove high frequency images. It is then applied to an adjustable gain amplifier formed by VR400, R404-R406, C409, IC401, and IC402-A. These components form an inverting amplifier

OPTIMOD-FM 2200

circuit. IC401 is an 8-bit MDAC, which is a resistor ladder with a program mable resistance. The control circuit writes an 8-bit word directly to IC401, which has a latch on board to store the wor d. The word sets the re sistance valu e betwee n pin 15 and pin 1 of IC401. IC402-A forces pin 1 of IC401 to virtual ground. The resistance between pin 1 and pin 16 of IC401, and resistors R404-R406 and VR400 are in the feedback loop of IC402-A. C409 stabilizes this stage. VR400 is a factory gain tr im to co rrect fo r toler ances in IC401, IC40 0, an d the rest of the analog output circuits.

IC402-A feeds the stage consisting of IC402-B and associated components, which is a programmable de-emphasis filter. JFETs Q400 and Q401 are used to switch C410 and C411 , respectively, in or out of the circuit. The state of the JFET switches is set by the outputs of IC305, a digital latch. The latch outputs feed IC407, a quad comparator, which outputs 0V to turn on a FET and −15V to turn off a FET. If neither of the JFETs are on, the circuit is a unity-gain inverting amplifier. The circuit becomes a first-order low-pass filter if one of the JFETs is turned on. If Q400 is on, capacitor C410 is in circuit to create a 75µs time constant. If Q41 1 is on, capa citor C401 is in circuit to create a 50 µs time constant.

IC402-B feeds the stage consisting of IC403-A, IC403-B, IC408-A, and associated components, which is a floating-balanced line driver. The floating characteristic is achieved by complex cross-coupled positive and negative feedback between two 5532 opamps, a nd its oper atio n is no t rea dily e xplain able exce pt by a detailed mathema tical analysis. Opamps may be r eplaced; resistors ar e specially matched and should not be replaced. IC408-A, R444, R445, R447, and C419 comprise a servo amplifier which cen ters ar ound groun d the ave rage DC level a t output connector J400.

TECHNICAL DATA

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The balanced audio output signal is applied to the RF filter network made up of L400, L401, L402, an d L403 , an d the n to XLR conne ctor J400.

The corresponding right channel circuitry is functionally identical to that just described.

3. Digital Sample Rate Converter (SRC) and Output Transmitter

An output sample rate converter (SRC) chip is used to convert the 32kHz 2200-D system sample rate to any of the standard 32kHz, 44.1kHz or 48kHz rates. A digital audio interface transmitter chip is used to encode digital audio signals using the AES/EBU interface format (AES3-1992). A synchronous serial interface is used for all inter-chip communication.

Component-Level Description:

The processed dig ital ou tpu t ( DIG_ OUT) provided at the SAI output por t SDO0 (pin 47) of DSP IC70 6 is rec eived by asyn chrono us sample rate con verte r (SRC) IC615 pin 3. An 8.192MHz bit c loc k is provide d from th e system clo ck cir cu itry to both the DSP and the SRC chips. The DSP output data format is SPI (32 bits per word two words per frame). DSP chip IC706 receives a 128kHz frame clock at its WST input (pin 50) tha t sets the word transfer rate to e ight words per 32 kHz period. The SRC receives a 32kHz clock at its L/R*_I input (pin 6). L/R*_I delineates the le ft and rig ht samples u sed by the SR C; there fore th e SRC use s the

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TECHNICAL DATA OPTIMOD-FM 2200

first sample rece ived for the left input a nd the fif th sample fo r the rig ht input. T he DSP output samples are formatted to ensure that the SRC uses a left and right output pair that represen t the sim ulta ne ou sly sample d analog input.

The crystal oscillator (Y602) provide s the SRC a maste r clock of 16.384MHz on pin 2. This MCLK frequency allows the output SRC to operate with an output sample rate in the ran ge between 30kHz a nd 57kHz (opera tion between 8kHz and 30kHz will result in a one sample delay between the left and right channels). SRC_RST is an active low reset signal tied to pin 13 of the SRC. This signal is controlled by the Z-180 via pin 2 of latch IC609 .

The output side of the sample rate converter is tied directly to IC616, an AES/EBU digital audio tra nsmitter in tegra ted circu it. This inte rfac e uses the SPI format with the AES transm itter as master . The transmitter chip encodes the au dio data it receives to the AE S/EBU inte rf ac e stan da rd , a nd tra nsmits it.

The SRC output sample rate and the sample rate that the AES/EBU transmitter transmits with is based on the MCK clock provided to pin 5 of IC616 . This clock is received via digital multip lexer chip IC610 which is used to sele ct o ne of four available clocks. Three free running clocks provide the standard sample rates of 32kHz, 44.1kHz and 48kHz wh en an internal sync is req uested. T hese c locks run at a frequency that is 128 times the sample rate they represent. They have a frequency stability of ±100PPM. The fourth clock is the EXTMCK clock that is recovered from the AES/EBU receiver chip. This clock has a frequency of 256 times the input sample rate of th e receiv ed sig nal. This is use d to drive the outpu t AES/EBU transmitter when an outpu t sample rate i s required tha t is synchronous to the input sample rate (external sync).

The inter-chip serial data format, the input MCK multiplication factor, and the output channel status data are controlled by the Z-180 via internal control registers and data memory a ccessed through the p arallel port mad e up of the 5-bit address bus (pins 9-13), the 8-bit data bus (pins 1-4, 21-24) and the CS* and RD/WR* control pins (pins 14 and 16) of IC616.

The on-chip RS422 lin e driver provide d by IC616 i s a low skew, low impedance, differential output capable of driving a 110Ω transmission line with a 4Vp-p signal. Shielded 1:1 pulse transformer T601 transmits the differential digital output signal to XLR connector J601. T601 has very low inter-winding capacitance, providing a high level of isolation from high frequency common mode interference.

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