The information in this publication is subject to change without notice. Force Computers, GmbH reserves the right to make
changes without notice to this, or any of its products, to improve reliability, performance, or design.
Force Computers, GmbH shall not be liable for technical or editorial errors or omissions contained herein, nor for indirect,
special, incidental, or consequential damages resulting from the furnishing, performance, or use of this material. This
information is provided "as is" and Force Computers, GmbH expressly disclaims any and all warranties, express, implied,
statutory, or otherwise, including without limitation, any express, statutory, or implied warranty of merchantability, fitness for a
particular purpose, or non−infringement.
This publication contains information protected by copyright. This publication shall not be reproduced, transmitted, or stored
in a retrieval system, nor its contents used for any purpose, without the prior written consent of Force Computers, GmbH.
Force Computers, GmbH assumes no responsibility for the use of any circuitry other than circuitry that is part of a product of
Force Computers, GmbH. Force Computers, GmbH does not convey to the purchaser of the product described herein any
license under the patent rights of Force Computers, GmbH nor the rights of others.
CopyrightE 2004 by Force Computers, GmbH. All rights reserved.
The Force logo is a trademark of Force Computers, GmbH.a
IEEER is a registered trademark of the Institute for Electrical and Electronics Engineers, Inc.a
PICMGR, CompactPCIR, and the CompactPCI logo are registered trademarks and the PICMG logo is a trademark of the PCI
Industrial Computer Manufacturer’s Group.
AdvancedTCA and ATCA are trademarks of the PCI Computer Manufacturer’s Group.
MS−DOSR, Windows95R, Windows98R, Windows2000R, Windows NTR, Windows Server 2003R and Windows XPR are
registered trademarks and the logos are a trademark of the Microsoft Corporation.
IntelR and PentiumR are registered trademarks and the Intel logo is a trademark of the Intel Corporation.
SPARCR is a registerd trademark, the SPARC logo is a trademark and Ultra SPARCR is a registered trademark of SPARC
International, Inc.
PowerPCR is a registered trademark and the PowerPC logo is a trademark of International Business Machines Corporation.
AltiVecR is a registered trademark and the AltiVec logo is a trademark of Motorola, Inc.
TM
Solaris
Linux Kernel is a free system kernel developed under the GNU General Public License.
GoAheadR is a registered trademark of GoAhead Software, Inc. and SelfReliant
GoAhead Software, Inc.
LynxOSR and BlueCatR are registered trademarks of LynuxWorks, Inc.
TornadoR, VxWorksR, WindR, WindNavigatorR, Wind River SystemsR, Wind River SystemsR and design, WindViewR,
WinRouterR and XmathR are registered trademarks or service marks of Wind River Systems. Inc.
Envoy
SonyR is a registered trademark of Sony Corporation, Japan.
Ethernet
Service Availability
PowerQUICC
Other product names mentioned herein may be trademarks and/or registered trademarks of their respective companies.
a is a trademark of SUN Microsystems, Inc.
TM
, the Tornado logo, Wind RiverTM, and Zinc
TM
a is a trademark of Xerox Corporation.
TM
is a trademark of the Service Availability Forum.
TM
is a trademark of Motorola, Inc.
a
a
a
TM
a and Self AvailabilityTMa are trademarks of
TM
a are trademarks or service marks of Wind River Systems, Inc.
a
a
2SPARC/CPU−56T
World Wide Web: www.fci.com
24−hour access to on−line manuals, driver updates, and application
notes is provided via SMART, our SolutionsPLUS customer support
program that provides current technical and services information.
This Reference Guide is intended for users qualified in electronics or electrical
engineering. Users must have a working understanding of Peripheral Component
Interconnect (PCI), VMEbus, and telecommunications.
Conventions
NotationDescription
57All numbers are decimal numbers except when used with the
notations described below.
00000000
or 0x00000000
0000
or 0b0000
xGeneric use of a letter
nGeneric use of numbers
0.75Decimal number
BoldUsed to emphasize a word
CourierUsed for on−screen output
Courier+BoldUsed to characterize user input
ItalicsFor references, table, and figure descriptions
File > ExitNotation for selecting a submenu
<text>Notation for variables and keys
[text]Notation for buttons and optional parameters
...Repeated item (example: A1, A2, A3, ..., A12)
.
.
.
16
2
Typical notation for hexadecimal numbers (digits 0 through F),
e.g. used for addresses and offsets
Same for binary numbers (digits are 0 and 1)
Omission of information from example/command that is not
necessary at the time being
..Ranges, e.g.: 0..4 means one of the integers 0, 1, 2, 3, and 4
|Logical OR
14SPARC/CPU−56T
(used in register description tables)
No danger encountered. Pay attention to important
information
NotationDescription
Possibly dangerous situation: slight injuries to people or
Dangerous situation: injuries to people or severe damage to
p
p
Possibly dangerous situation: slight injuries to people or
damage to objects possible
Dangerous situation: injuries to people or severe damage to
objects possible
Start of a procedure
End of a procedure
Abbreviations
AbbreviationDescription
B
BGA
BIBBoard Information Block
BMCBase Board Management Controller
FAE
FIFOFirst In First Out
FPGAField−Programmable Gate Array
I
IBMU
ICMBIntelligent Chassis Management Bus
ICTIn−Circuit Test
IDEIntegrated Drive Electronics
IECInternational Electric Code
IOBPInput Output Back Panel
IOMI/O Memory Management Unit
IPMBIntelligent Platform Management Bus
IPMIIntelligent Platform Management Interface
ISOInternational Organization for Standardization
J
JTAG
L
LCA
LDOLocal Data Output
LEDLight Emitting Diode
LVDLow Voltage Differential
LVTTLLow Voltage Transistor Transistor Logic
M
Field Application Engineers
I
Intelligent Board Management Unit
J
Joint Test Access Group
L
Load Controller Assembly
M
MAC
MCUMemory Control Unit
MIIMedia Independent Interface
N
NEBS
NMINonmaskable Interrupt
NVRAMNonvolatile Random Access Memory
ieee.comIEEE P1386 Standard Mechanics for a Common
Mezzanine Card Family: CMC
national.comPC87307/PC97307 Plug and Play Compatible
Super I/O, Preliminary Specification, March
1998
pcisig.comPCI Local Bus Specification Rev2.1
picmg.org
pcisig.com
PCI Local Bus Specification Rev2.2
documentation
VITAvita.comVME64 Standard ANSI/VITA 1−1994
aaaaVME64 Extensions Draft Standard, Draft 1.8, Jun
13, 1997
Xilinx
SPARC/CPU−56T19
xilinx.comSpartan XC520XL FPGA specifications
Safety Notes
The text in this chapter is a translation of the Sicherheitshinweise" chapter
This section provides safety precautions to follow when installing, operating, and
maintaining the board.
We intend to provide all necessary information to install and handle the board in this
Installation Guide. However, as the product is complex and its usage manifold, we do not
guarantee that the given information is complete. If you need additional information, ask
your Force Computers representative.
The board has been designed to meet the standard industrial safety requirements. It
must not be used except in its specific area of office telecommunication industry and
industrial control.
Only personnel trained by Force Computers or persons qualified in electronics or
electrical engineering are authorized to install, remove or maintain the board. The
information given in this manual is meant to complete the knowledge of a specialist
and must not be taken as replacement for qualified personnel.
EMC
The board has been tested in a Standard Force Computers system and found to comply
with the limits for a Class A digital device in this system, pursuant to part 15 of the
FCC Rules respectively EN 55022 Class A. These limits are designed to provide
reasonable protection against harmful interference when the system is operated in a
commercial environment.
The board generates and uses radio frequency energy and, if not installed properly and
used in accordance with this Installation Guide, may cause harmful interference to
radio communications. Operating the system in a residential area is likely to cause
harmful interference, in which case the user will be required to correct the interference
at his own expense.
To ensure proper EMC shielding, always operate the board with the blind panel or
with PMC module installed. If boards are integrated into open systems, always cover
empty slots.
Switch Settings
Switches marked as ’reserved’ might carry production−related functions and can cause
the board to malfunction if their setting is changed. Therefore, only change settings of
switches not marked as ’reserved’.
20SPARC/CPU−56T
Setting/resetting the switches during operation causes board damage. Therefore, check
and change switch settings before you install the board.
Installation
Electrostatic discharge and incorrect board installation and removal can damage
circuits or shorten their life. Therefore:
STouching the board or electronic components in a non−ESD protected environment
causes component and board damage. Before touching boards or electronic
components, make sure that you are working in an ESD−safe environment.
SWhen plugging the board in or removing it, do not press or pull on the front panel
but use the handles.
SBefore installing or removing an additional device or module, read the respective
documentation.
SMake sure that the board is connected to the VME backplane via all assembled
connectors and that power is available on all power pins.
Power Up
If an unformatted floppy disk resides in a floppy drive connected to the VME board
during power up, the VME board does not boot and the OpenBoot prompt does not
appear. Therefore, never boot the VME board with an unformatted floppy disk
residing in a floppy drive connected to the VME board.
a
Operation
While operating the board ensure that the environmental and power requirements are
met:
STo ensure that the operating conditions are met, forced air cooling is required
within the chassis environment.
SHigh humdity and condensation on the surface cause short circuits. Only operate
the board above 0°C. Make sure the board is completely dry and there is no
moisture on any surface before applying power.
Replacement/Expansion
Only replace or expand components or system parts with those recommended by Force
Computers. Otherwise, you are fully responsible for the impact on EMC or any
possible malfunction of the product.
SPARC/CPU−56T21
Check the total power consumption of all components installed (see the technical
specification of the respective components). Ensure that any individual output current
of any source stays within its acceptable limits (see the technical specification of the
respective source).
RJ−45 Connector
The RJ−45 connector on the front panel must only be used for twisted−pair Ethernet
(TPE) connections. Connecting a telephone to such a connector may destroy your
telephone as well as your board. Therefore:
SClearly mark TPE connectors near your working area as network connectors
SOnly connect TPE bushing of the system to safety extra low voltage (SELV) circuits.
SMake sure that the length of the electric cable connected to a TPE bushing does not
exceed 100 meter.
If you have further questions, ask your system administrator.
Battery
If a lithium battery on the board has to be exchanged (see Appendix Battery Exchange),
observe the following safety notes:
SWrong battery exchange may result in a hazardous explosion and board damage.
Therefore, always use the same type of lithium battery as is installed and make sure
the battery is installed as described.
SExchanging the battery after seven years of actual battery use have elapsed results
in data loss. Therefore, exchange the battery before seven years of actual battery use
have elapsed.
SExchanging the battery always results in data loss of the devices which use the
battery as power backup. Therefore, back up affected data before exchanging the
battery.
Environment
Always dispose of used batteries and/or old boards according to your country’s
legislation, if possible in an environmentally acceptable way.
22SPARC/CPU−56T
Sicherheitshinweise
Dieser Abschnitt enthält Sicherheitshinweise, die bei Einbau, Betrieb und Wartung des
Boards zu beachten sind.
Wir sind darauf bedacht, alle notwendigen Informationen, die für die Installation und den
Betrieb erforderlich sind, in diesem Handbuch bereit zu stellen. Da es sich jedoch bei dem
Board um ein komplexes Produkt mit vielfältigen Einsatzmöglichkeiten handelt, können
wir die Vollständigkeit der im Handbuch enthaltenen Informationen nicht garantieren.
Falls Sie weitere Informationen benötigen sollten, wenden Sie sich bitte an die für Sie
zuständige Geschäftsstelle von Force Computers.
Das Board erfüllt die für die Industrie geforderten Sicherheitsvorschriften und darf
ausschliesslich für Anwendungen in der Telekommunikationsindustrie und im
Zusammenhang mit Industriesteuerungen verwendet werden.
Einbau, Wartung und Betrieb dürfen nur von durch Force Computers ausgebildetem
oder im Bereich Elektronik oder Elektrotechnik qualifiziertem Personal durchgeführt
werden. Die in diesem Handbuch enthaltenen Informationen dienen ausschliesslich
dazu, das Wissen von Fachpersonal zu ergänzen, können es aber in keinem Fall
ersetzen.
EMV
Das Board wurde in einem Force Computers Standardsystem getestet. Es erfüllt die für
digitale Geräte der Klasse A gültigen Grenzwerte in einem solchen System gemäß den
FCC−Richtlinien Abschnitt 15 bzw. EN 55022 Klasse A. Diese Grenzwerte sollen einen
angemessenen Schutz vor Störstrahlung beim Betrieb des Boards in Gewerbe− sowie
Industriegebieten gewährleisten.
Das Board arbeitet im Hochfrequenzbereich und erzeugt Störstrahlung. Bei
unsachgemäßem Einbau und anderem als in diesem Handbuch beschriebenen Betrieb
können Störungen im Hochfrequenzbereich auftreten.
Warnung! Dies ist eine Einrichtung der Klasse A. Diese Einrichtung kann im
Wohnbereich Funkstörungen verursachen. In diesem Fall kann vom Betreiber verlangt
werden, angemessene Maßnahmen durchzuführen.
Wenn Sie das Board ohne PMC Modul verwenden, schirmen Sie freie Steckplätze mit
einer Blende ab, um einen ausreichenden EMV Schutz zu gewährleisten. Wenn Sie
Boards in Systeme einbauen, schirmen Sie freie Steckplätze mit einer Blende ab.
Schaltereinstellungen
Das Ändern der mit ’reserved’ gekennzeichneten Schalter kann zu Störungen im
Betrieb des Boards führen. Ändern Sie die Schaltereinstellungen der mit ’reserved’
SPARC/CPU−56T23
gekennzeichneten Schalter nicht, da diese Schalter mit produktionsrelevanten
Funktionen belegt sein können, die im normalen Betrieb Störungen auslösen könnten.
Das Ändern der Schaltereinstellungen während des laufendes Betriebs kann das Board
beschädigen. Prüfen und ändern Sie die Schaltereinstellungen, bevor Sie das Board
installieren.
Installation
Elektrostatische Entladung und unsachgemäßer Ein− und Ausbau des Boards kann
Schaltkreise beschädigen oder ihre Lebensdauer verkürzen. Beachten Sie deshalb die
folgenden Punkte:
SBerühren Sie das Board oder elektrische Komponenten in einem nicht
ESD−geschützten Bereich, kann dies zu einer Beschädigung des Boards führen.
Bevor Sie Boards oder elektronische Komponenten berühren, vergewissern Sie
sich, dass Sie in einem ESD−geschützten Bereich arbeiten.
SDrücken Sie beim Ein− oder Ausbau des Boards nicht auf die Frontplatte, sondern
benutzen Sie die Griffe.
SLesen Sie vor dem Ein− oder Ausbau von zusätzlichen Geräten oder Modulen das
dazugehörige Benutzerhandbuch.
Booten
Betrieb
SVergewissern Sie sich, dass das Board über alle Stecker an die VME Backplane
angeschlossen ist und alle Spannungskontakte mit Strom versorgt werden.
Befindet sich während des Bootens eine unformatierte Diskette in einem mit dem
VME Board verbundenen Diskettenlaufwerk, bootet das VME Board nicht, und die
OpenBoot−Eingabeaufforderung erscheint nicht. Booten Sie deshalb niemals das VME
Board, wenn sich eine unformatierte Diskette in einem mit dem VME Board
verbundenen Diskettenlaufwerk befindet.
Achten Sie darauf, dass die Umgebungs− und die Leistungsanforderungen während
des Betriebs eingehalten werden:
SUm zu gewährleisten, dass die Anforderungen während des Betriebs eingehalten
werden, ist eine Luftkühlung notwendig
SBetreiben Sie das Board nur innerhalb der angegebenen Grenzwerte für die relative
Luftfeuchtigkeit und Temperatur, da durch hohe Luftfeuchtigkeit Kurzschlüsse
24SPARC/CPU−56T
entstehen können. Stellen Sie vor dem Einschalten des Stroms sicher, dass sich auf
dem Board kein Kondensat befindet und betreiben Sie das Board nicht unter 0°C.
Wenn Sie das Board in Gebieten mit starker elektromagnetischer Strahlung betreiben,
stellen Sie sicher, dass das Board mit dem System verschraubt ist und das System
durch ein Gehäuse abgeschirmt wird.
Stellen Sie sicher, dass Anschlüsse und Kabel des Boards während des Betriebs nicht
versehentlich berührt werden können.
Austausch/Erweiterung
Verwenden Sie bei Austausch oder Erweiterung nur von Force Computers empfohlene
Komponenten und Systemteile. Andernfalls sind Sie für mögliche Auswirkungen auf
EMV oder Fehlfunktionen des Produktes voll verantwortlich.
Überprüfen Sie die gesamte aufgenomme Leistung aller eingebauten Komponenten
(siehe die technischen Daten der entsprechenden Komponente). Stellen Sie sicher, dass
die Stromaufnahme jedes Verbrauchers innerhalb der zulässigen Grenzwerte liegt
(siehe die technischen Daten des entsprechenden Verbrauchers).
RJ−45 Stecker
Batterie
Der RJ−45 Stecker auf der Frontblende darf nur für Twisted−Pair−Ethernet (TPE)
Verbindungen verwendet werden. Beachten Sie, dass ein versehentliches Anschließen
einer Telefonleitung an einen solchen TPE Stecker sowohl das Telefon als auch das
Board zerstören kann. Beachten Sie deshalb die folgenden Hinweise:
SKennzeichnen Sie TPE−Anschlüsse in der Nähe Ihres Arbeitsplatzes deutlich als
Netzwerkanschlüsse.
SSchließen Sie an TPE−Buchsen ausschließlich SELV−Kreise
(Sicherheitskleinspannungsstromkreise) an.
SDie Länge des mit dem Board verbundenen Twisted−Pair Ethernet−Kabels darf 100
m nicht überschreiten.
Falls Sie Fragen haben, wenden Sie sich bitte an Ihren Systemadministrator.
Muss eine Lithium−Batterie auf dem Board ausgetauscht werden (siehe Appendix
Battery Exchange), beachten Sie die folgenden Sicherheitshinweise:
SFehlerhafter Austausch von Lithium−Batterien kann zu lebensgefährlichen
Explosionen führen. Verwenden Sie deshalb nur den Batterietyp, der auch bereits
eingesetzt wurde und befolgen Sie die Installationsanleitung.
SPARC/CPU−56T25
SVerwenden Sie die Batterien länger als sieben Jahre, kann dies zu Datenverlusten
führen. Tauschen Sie deshalb die Batterie aus, bevor sieben Jahre reiner Betrieb
vorüber sind.
SDer Austausch der Batterie bringt immer einen Datenverlust bei den Komponenten
mit sich, die sich durch die Batterie die Stromversorgung sichern. Sichern Sie
deshalb vor dem Batterieaustausch Ihre Daten.
Umweltschutz
Entsorgen Sie alte Batterien und/oder Boards stets gemäß der in Ihrem Land gültigen
Gesetzgebung, wenn möglich immer umweltfreundlich.
The SPARC/CPU56 is a high−performance VME single−board computer based on the 650
Mhz UltraSPARC IIi+ processor. It provides 512 MByte on−board SDRAM memory.
Important features are:
STwo Wide Ultra3 SCSI interfaces via front panel and one via I/O board′s IOBP
STwo 10/100/1000 BaseT Ethernet interfaces via front panel
SOne 10/100 BaseT interface via front panel or CPU board′s IOBP
STwo serial RS−232 interfaces via front panel
STwo RS−232/RS−454 interfaces via CPU board′s IOBP
SThree USB interfaces via CPU board′s IOBP
SOptional on−board hard disk
SKeyboard/Mouse interface via front panel or CPU board′s IOBP
SFloppy disk and parallel interface via CPU board′s IOBP
SThree PMC slots on I/O board
SSolaris 8/9 and VxWorks support
a
28SPARC/CPU−56T
FeaturesIntroduction
Figure 1: Function Blocks
SPARC/CPU−56T29
IntroductionStandard Compliances
Standard Compliances
The CPU board was designed to comply with the standards listed below.
EN 609 50/UL 1950 (predefined Force system);
UL 94V−0/1
EN 55022,a
EN 55024,
FCC Part 15 Class A
ANSI/IPC_A−610 Rev. B Class 2
ANSI/IPC−R−700B
ANSI−J−001...003
ISO 8601
Description
Legal safety requirements
EMC requirements on system level
Manufacturing requirements
Y2K compliance
30SPARC/CPU−56T
Ordering InformationIntroduction
Ordering Information
When ordering board variants, hard− and software upgrades use the order numbers
given below.
Product Nomenclature
In the following table you find the key for the product name extensions used for board
variants.
Table 2: Product Nomenclature
SPARC/CPU−56T/xxx−ccc−Lyyy−zz
xxxSDRAM capacity in MByte
cccCPU speed in MHz
LyyyL2−cache in KByte
a
zz
Order Numbers
The table below is an excerpt from the board’s ordering information. Ask your local Force
Computers representative for the current ordering information.
Table 3: Board Ordering Information
Order No.
111328512−650−L512−16512 MByte SDRAM, 650 MHz CPU
The table below is an excerpt from the board’s accessories ordering information. Ask your
local Force Computers representative for the current ordering information.
Table 4: Board Accessories Ordering Information
Order No.AccessoryDescription
111330SPARC/IOBP−CPU−56/3Three−row variant of CPU board′s
111331SPARC/IOBP−CPU−56/5Five−row variant of CPU board′s
Flash memory size in MByte
SPARC/CPU−56T/...Description
frequency, 512 KByte L2 cache and 16
MByte flash memory
IOBP
IOBP
120455
SPARC/CPU−56T31
SPARC/IOBP−IO−56/5Five−row variant of I/O board′s
IOBP
IntroductionOrdering Information
Order No.DescriptionAccessory
120456SPARC/IOBP−IO−56/3Three−row variant of I/O board′s
In order to install the board, the following steps are necessary and will be described in
further detail in the sections of this chapter.
SPARC/CPU−56T35
InstallationRequirements
Requirements
In order to meet the environmental requirements, the CPU board has to be tested in the
system in which it is to be installed.
Before you power up the board, calculate the power needed according to your
combination of board upgrades and accessories.
Environmental Requirements
The environmental conditions must be tested and proven in the used system
configuration. The conditions refer to the surrounding of the board within the user
environment.
Note:aOperating temperatures refer to the temperature of the air circulating around the
board and not to the actual component temperature.
a
SBoard damage
Operating the board in a chassis without forced air cooling may lead to board
damage.
When operating the board, make sure that forced air cooling is available.
SBoard damage
High humidity and condensation on the board surface causes short circuits.
Do not operate the board outside the specified environmental limits. Make sure the
board is completely dry and there is no moisture on any surface before applying
power. Do not operate the board below 0°C.
Table 5: Environmental Requirements
FeatureOperatingNon−Operating
Temperature
Forced airflow300 LFM (linear feet per minute)−
Temp. change
Rel. humidity
Altitude−300 m to + 3,000 m−300 m to + 13,000 m
Vibrationaaaa
0°C to +50°C−40°C to +85°C
+/− 0.5°C/min+/− 1.0°C/min
5% to 95% non−condensating at +40°C
5% to 95% non−condensating at
+40°C
10 to 15 Hz
15 to 150 Hz
36SPARC/CPU−56T
2 mm amplitude
2 g
5 mm amplitude
5 g
RequirementsInstallation
FeatureNon−OperatingOperating
Shock5g/11 ms halfsine15g/11 ms halfsine
Free fall100 mm / 3 axes1,200 mm / all edges and corners
(packed state)
Power Requirements
The board power requirements depend on the installed hardware accessories. In the
following table you will find typical examples of power requirements without any
accessories installed. If you want to install accessories on the board, the load of the
respective accessory has to be added to that of the board. For information on the
accessories’ power requirements, refer to the documentation delivered together with the
respective accessory or consult your local Force Computers representative for further
details.
The power supply has to meet the requirements given in the tables below.
Table 6: Power Requirements
Requirement
Minimum Voltage4.88V11.64V
Typical Voltage5V12V
Maximum Voltage5.25V12.6V
Typical Current6A1.5A
Maximum Current7A1.63A
Typical Power Requirement30W18W
Maximum Power Requirement
5V12V
35W20W
Note:aThe CPU board only powers up if the 5V and 12V supply voltages are stable and
within their limits. This complies to the VMEbus specification. However, there are
systems which are not fully VMEbus−compliant. The power supplies of these systems
do not turn on the 12V supply if the 5V supply has not been loaded before. Use a
VMEbus board which loads the 5V in these systems to avoid a power−up deadlock
situation.
a
SPARC/CPU−56T37
InstallationHardware Accessories
Hardware Accessories
The following upgrades and accessories are available:
SIOBPs for CPU and I/O Board
SPMC modules
SMemory modules
SHard Disk
SSCSI−U160 cable
SRS−422 serial cable
SPS2 splitter cable
IOBPs for CPU and I/O Board
As separate price list items two IOBPs are available for the SPARC/CPU−56T. One is
called SPARC/IOBP−IO−56 and is connected to the I/O board. It is available in two
variants which differ in the number of VME connector rows: the three−row variant
SPARC/IOBP−IO−56−3 and the five−row variant SPARC/IOBP−IO−56−5. Both IOBPs
provide the following interfaces:
SSCSI (on SPARC/IOBP−IO−56−3 only single−ended SCSI)
SAudio
SPMC user I/O
For details about this IOBP and its installation refer to the
Guide.
The second IOBP is called SPARC/IOBP−CPU−56 and is connected to the CPU board. It is
available in two variants which also differ in the number of VMEconnector rows: the
three−row variant SPARC/IOBP−CPU−56−3 and the five−row variant
SPARC/IOBP−CPU−56−5. The interfaces available via both IOBP variants are:
SIDE
S10/100Base−TX
SParallel
aSPARC/IOBP−IO−56 Installation
STwo USB
STwo serial (RS−232 and RS−422)
38SPARC/CPU−56T
Hardware AccessoriesInstallation
Note:aOn the IOBP−CPU−56−3 the RS−232 signals are limited to RXD, TXD, RTS and
CTS.
a
On the IOBP−CPU−56−5 the additional signals DTR, DSR, DCD and RI are available.a
In addition to these interfaces, the five−row variant IOBP−CPU−56−5 provides:
SKeyboard/mouse interface (SUN or PS/2 style)
SThird USB interface
SFloppy interface
S10/100/1000 Base−TX Ethernet
For details about this IOBP and its installation refer to the
Installation Guide.
Board Damage
Using the board together with IOBPs for which it is not designed, may destroy the
board.
a
Only use the board together with the IOBP−CPU−56 or IOBP−IO−56.
PMC Modules
The I/O board allows to install three PMC modules compliant to IEEE P1386.a
Note:aThe used PMC modules must be compliant with the safety regulations of the
country where the equipment is installed.
The corresponding PMC slots are PMC slots 2, 3 and 4. The following figure shows which
PMC connectors are assigned to each PMC slot.
aSPARC/IOBP−CPU−56
a
SPARC/CPU−56T39
InstallationHardware Accessories
PMC#4PMC#3PMC#2
PMC slot 2 supports a 64−bit data bus width with a maximum frequency of 33 MHz and
is attached to PCI bus B. PMC slots 3 and 4 support a 64−bit data bus width with a
maximum frequency of 66 MHz and are attached to PCI bus C.
a
If a 32−bit PMC module is mounted into PMC slots 3 and 4, the Sentinel64 PCI−to−PCI
bridge dynamically detects the 32−bit bus and changes its transfer size to 32−bit for this
PMC module. If a 64−bit PMC module is mounted into PMC slots 3 and 4, burst transfers
between all 64−bit PCI devices on PCI bus B and C will be 64−bit PCI transfers.
Note:aIf a 33−MHz PMC module is mounted into PMC slots 3 and 4, the whole PCI bus
C will run with 33 MHz only. This may result in performance degradation.
The signaling level of each PMC slot is determined via a voltage key which has to be
installed into one of two holes that belong to each PMC slot. One hole corresponds to a
signalling level of 5V, the other to a signaling level of 3.3V. Depending on the hole the
voltage key is installed into, the signaling level is set accordingly. This is illustrated in the
figure below.
Figure 2: Location of PMC Voltage Keys
a
5V
3.3V
By default, PMC slots 3 and 4 have a signaling level of 3.3V and PMC slot 2 has a
signaling level of 5V. A description of how to change the signalling level for a PMC slot is
given in the following installation procedure.
a
Note:aA 66−MHz PCI bus configuration requires that the signaling level and therefore
the VI/O voltage is 3.3 V.
40SPARC/CPU−56T
Hardware AccessoriesInstallation
Installation Procedure
Note:a
STo ensure proper EMC shielding, either operate each PMC slot with a blind panel
or with a PMC module installed.
SIf the SPARC/CPU−56T is upgraded with PMC modules, ensure that the blind
panels are stored in a safe place in order to be used again when removing the
respective PMC module.a
SProcessor PMC modules are only supported in non−monarch mode.a
Removing I/O Board
Start
1. Remove the 14 screws from I/O board which fix it to CPU board
SPARC/CPU−56T41
InstallationHardware Accessories
2. Carefully remove I/O board from CPU board by unplugging it from PMC
connectors
Finish
Changing Signaling Level
Start
1. Remove screw which fixes the voltage key to IO board
Voltage Key
Screw
2. Remove voltage key
3. Place voltage key into hole which corresponds to desired signalling level
5V
3.3V
Note:aThe signaling levels of PMC slots 3 and 4 must be equal. Otherwise they are
automatically set to 3.3V.
42SPARC/CPU−56T
a
Hardware AccessoriesInstallation
4. Fix voltage key to I/O board by fastening screw
Voltage Key
Screw
Finish
Installing the PMC Module
Start
1. Plug PMC module into desired PMC connectors of I/O board
PMC#4PMC#3PMC#2
PMC Module Damage
If the power consumption of the PMC module exceeds 7.5W, the board and the PMC
module are damaged.
Make sure that the total power consumption at +/−12V, 5V and 3.3V level does not
exceed 7.5W.
2. Make sure standoffs of PMC module cover mounting holes of I/O board
3. Place screws delivered with PMC into mounting holes
SPARC/CPU−56T43
InstallationHardware Accessories
4. Fasten screws
Finish
Reinstalling I/O Board
Start
1. Plug I/O board onto PMC connectors of CPU board
2. Fix it by fastening the 14 screws which you previously have removed
Finish
Memory Modules
The main memory capacity is adjustable via installation of a Force Computers memory
module. Currently the SPARC/MEM−550 is available for the CPU−56T. It provides 1
GByte memory .
Before installing the memory module you have to remove the I/O board and afterwards
you have to reinstall it. How this is done is described in the previous section "PMC
Modules".
The memory module has to be installed into the connectors P8 and P9.a
a
P8
P9
44SPARC/CPU−56T
Hardware AccessoriesInstallation
The actual memory module installation procedure is described in theaSPARC/MEM−550
Installation Guide
a which is delivered together with the memory module.a
Hard Disk
A hard disk is available for the CPU board on request. It can be connected to the IDE1
interface which is accessible via an on−board connector.
a
Before installing the hard disk you have to remove the I/O board and afterwards you
have to reinstall it. How this is done is described in the previous section "PMC Modules".
The actual installation of the hard disk is described in the Installation Guide delivered
together with the hard disk.
a
SCSI−U160 Cable
The SCSI−U160 cable is available as accessory kit called ACC/CABLE*SCSI*U160. It
provides a SCSI U160 cable with a length of three meters which has one SCSI*3 and one
SCSI*4 connector at its ends. It can be used to connect SCSI devices to the CPU board.
For details, refer to the
together with the accessory kit.
aACC/CABLE/SCSI−U160 Installation Guidea which is delivered
a
RS−422 Cable
The RS−422 cable is available as accessory kit called ACC/CABLE*RS*422 and
provides a serial cable with a length of 2.6 meters that has one male DSub9 RS*422 and
one female mini DSub9 RS*232 connector at its ends. It allows to connect RS*422
devices to the serial B interface of the CPU board. For details, refer to
the
aACC/CABLE/RS−422 Installation Guideawhich is delivered together with the accessory
a
kit.
PS/2 Splitter Cable
The PS/2 splitter cable can be connected to the SUN−type keyboard/mouse connecter of
the CPU board or its IOBP. It allows to operate a PS/2−style keyboard and mouse.
a
SPARC/CPU−56T45
InstallationSwitch Settings
Switch Settings
Board Damage
Setting/resetting the switches during operation causes board damage.
Therefore, check and change switch settings before you install the board.
The CPU board provides four configuration switches: SW1, SW2, SW3 and SW4.
8G
O
N
1
234
8G
SW4
O
N
1
234
8G
O
N
1
234
8G
O
N
1
234
Figure 3: Location of Switches on Board’s Top Side
Table 7: Switch Settings
SwitchNo.Description
SW11Flash memory write protection
OFF (default): Flash memory writing disabled
ON: Flash memory writing enabled
2Boot device selection
OFF (default): Boot from PLCC PROM
ON: Boot from flash memory device
3Enable watchdog
OFF (default): Watchdog disabled
ON: Watchdog enabled
4Enable reset/abort key
OFF (default): reset/abort key enabled
ON: reset/abort key disabled
SW21..4User defined switches. For detailed information refer to section
"Switch 1 and 2 Status Register".
SW3
1Enable Termination for SCSI 1
OFF (default): Termination enabled
ON: Termination disabled
46SPARC/CPU−56T
Switch SettingsInstallation
SwitchDescriptionNo.
2Enable termination for SCSI 2
OFF (default): Termination enabled
ON: Termination disabled
3Enable termination for SCSI 3 (on I/O−board, if applicable)
OFF (default): Termination enabled
ON: Termination disabled
4Reserved
SW41..2VME Slot 1 Detection
SW4−1 OFF (default): Automatic VMEbus slot 1 detection enabled
SW4−1 ON and SW4−2 OFF: VME slot 1 function enabled
SW4−1 ON and SW4−2 ON: VME slot 1 function disabled
3External VMEbus SYSRESET function
OFF (default): VMEbus SYSRESET generates on−board RESET
ON: VMEbus SYSRESET does not generate on−board RESET
4VMEbus SYSRESET generation
OFF (default): On−board reset is driven to VMEbus SYSRESET
ON: On−board reset is not driven to VMEbus SYSRESET
SPARC/CPU−56T47
InstallationBoard Installation
Board Installation
Board Damage
Installing the board into a powered system may damage this and other boards in the
system.
Only install the board into a non−powered system.a
Backplane Configuration
If the CPU board is plugged into slot 1 and configured accordingly with switch SW4 (refer
to Switch Settings" table), the board acts as IACK daisy−chain driver. Plugged in any
other slot, the board closes the IACKIN−IACKOUT path.
If one board is missing in this daisy chain, an active backplane will be able to
automatically transfer the signals to the next board in the chain. If the board is not
plugged into an active backplane, jumpers on the backplane will transmit the signals. The
jumpers have to be set manually.
a
a
Configuration Procedure
Start
1. Remove jumpers connecting BG3IN# and BG3OUT# signals from empty slot
on backplane where the CPU board is to be plugged into backplanea
2. Assemble jumpers for BG3IN# and BG3OUT# signals on lower and higher
slots on backplane where no board is plugged to ensure that daisy chain is not
interrupted
Finish
If configured accordingly, the CPU board recognizes automatically whether it is plugged
into slot 1 of the VMEbus backplane or in any other slot. This auto−configuration feature
requires SW4−2 to be set to the OFF position. The VMEbus system controller is enabled
via auto−configuration if the CPU board is plugged into slot 1. Otherwise, it is disabled.
Damage of the Board or Other VMEbus Participants
If more than one system controller is active in the VMEbus system, the board or other
VMEbus participants can be damaged.
Therefore, always ensure that only one CPU board is configured to be system controller
in the VMEbus system.
a
48SPARC/CPU−56T
Board InstallationInstallation
Installing the CPU Board
Procedure
Start
1. Check system documentation for all important steps to be taken before
switching off power
2. Take those steps
3. Switch off power
4. Plug board into system slot on left−hand side
Note:aMake sure all other boards which are plugged into the system are to the right of
the system board.
5. Fasten board with screws
6. Plug interface cables into front panel connectors, if applicable
7. Switch on power
Finish
Removing the CPU Board
Procedure
Start
a
1. Check system documentation for all important steps to be taken before
switching off power
2. Take those steps
3. Switch off power
SPARC/CPU−56T49
InstallationBoard Installation
4. Remove interface cables, if applicable
5. Unfasten screws
6. Remove board
Finish
Powering Up
We recommend to use a terminal when powering up the CPU board. The advantage of
using a terminal is that you do not need any frame buffer, monitor, or keyboard for initial
power up.
Note:aSBefore powering up, check the "Requirements" section for installation
prerequisites and requirements.
SIf an unformatted floppy disk resides in a floppy drive connected to the CPU board
during power up, the CPU board does not boot and the OpenBoot prompt does not
appear.
SCheck the consistency of the switch settings ("Switch Settings" table).
a
a
Power Up Procedure
Start
1. Connect a terminal to front panel serial I/O interface A marked as "SER A"
2. Switch on system
The monitor will display information about the OpenBoot booting process.a
3. Enter OpenBoot commands, if applicable
Finish
PLCC PROM and Flash Memory Device
By default, the CPU board boots from the 1 MByte PLCC PROM which is not writeable
and contains the OpenBoot firmware. Alternatively, a 16 MByte flash memory device can
be enabled with SW1−2 to store user applications and to boot from it.
a
50SPARC/CPU−56T
Board InstallationInstallation
Installing Solaris
The CPU board is designed to run with Solaris 8 2/02 or higher with the 64−bit kernel and
with Solaris 9. Pay attention to the guidelines in this section before and during Solaris
installation.
Note:aSolaris versions prior to version 8 2/2 are not supported. The CPU board runs
with 64−bit kernel only.
The following devices of the CPU board are not supported by the Solaris operating
system:
SUniverse II PCI−to−VMEbus bridge
SOn−board flash memory
STemperature sensors, LEDs, timers and watchdog
SIntel 82540EM Ethernet device
SIDE device error handling
If you wish to use one of these devices, you need to install the Force Computers Solaris
Driver Package. Details will be given in the following sections.
a
a
a
If you want to use PS/2 keyboard and mouse, you have to customize the following
software groups during the Solaris installation:
SDeveloper system support
SEnd user system support
SCore system support
The customization consists of selecting "PS/2 keyboard and mouse device drivers (Root,
64 Bit) under "drivers for SME support (64 Bit)".
a
The remaining software groups do not require customization.a
Note:aDuring installation, make sure that the 64−bit support is enabled.a
If Solaris is already installed and you want to have PS/2 support afterwards, you have to
install the SUNWkmp2x for 64−bit package.
a
Note:aDuring the Solaris installation you may get the following Solaris error message:
"Could not reset the IDE core of SouthBridge". If this happens, try to install Solaris
from another CD−ROM drive or from a SCSI CDROM drive.
a
After the Solaris installation has finished, this Solaris error message can be avoided by
installing the Solaris Driver Package FRCcpu56pm.
SPARC/CPU−56T51
InstallationBoard Installation
For audio I/O and IDE ATA 100 support, you have to install Solaris patches. The
following table provides details.
Table 8: Solaris Patches
a
Supported Device
Audio I/O (if applicable)8109896−17 or newer
IDE ATA 1008108974−31 or newer
Solaris Driver Package
Force Computers provides a Solaris driver package which supports the following devices
and features of the CPU board:
SUniverse II PCI−to−VMEbus bridge
SOn−board flash memory
STemperature sensors, LEDs and watchdog
SIntel 82540EM GBit Ethernet device
SCPU−56 platform mode friver for IDE device error handling
If you wish to use one of these devices you need to install the Force Computers Solaris
Driver Package Version 2.20.
Solaris VersionPatch
9Currently not supported. A patch will be
available in the near future.a
9112954−03 or newer
a
For a detailled description of how to install and use it, refer to theaSolaris Driver Package
Rel. 2.20 Installation and Reference Guide
Computers S.M.A.R.T. server.
a
a which can be downloaded from the Force
The following table shows which driver has to be installed for a particular device.
Table 9: Devices and Their Appropriate Drivers
DeviceDriver Name
Intel 8254xEM GBit Ethernet controllerFRCgei
Universe II PCI−to−VMEbus bridgeFRCvme
On−board flash memoryaFRCflash
Temperature sensors, LEDs and watchdogFRCctrl
IDE device (error handling)
52SPARC/CPU−56T
FRCplatmod
Board InstallationInstallation
Further information on these drivers is given in the following sections.a
FRCgei
The assignment of the driver’s instance number to an Intel 8254xEM GBit Ethernet device
can be viewed by booting with the OpenBoot command boot −v. Each device is shown
with the driver name and instance number during the Solaris boot up.
The other way to obtain the instance number of the Ethernet devices is to look into the file
/etc/path_to_inst. In order to do so, type the following:agrep fciprb /etc/path_to_inst
A typical output could be:
”/pci@1f,0/ethernet@2” 1 ”frcgei”
”/pci@1f,0/pci@/ethernet@1” 0 ”frcgei”
The first part in quotation marks specifies the hardware node name in the device tree. The
number specifies the instance number and the third part also in quotation marks specifies
the driver name.
a
FRCvme
The following table shows how the hardware node names are assigned to a label on the
front panel and the IOBP−CPU−56.
LabelLocationHardware Node
ETHERNET1/3CPU front panel or
IOBP−CPU−56
ETHERNET2CPU front panel/pci@1f,0/pci@4/ethernet@1
ETHERNET4
IOBP−CPU−56/pci@1f,0 ethernet@2
a
Standard Solaris eri Ethernet device
The following table shows how the driver instance numbers are typically assigned to
Ethernet devices on the CPU board.
LabelLocationDriver/Instance Number
ETHERNET1/3CPU front panel or IOBP−CPU−56eri0
ETHERNET2CPU front panelfrcgei1
ETHERNET4
IOBP−CPU−56frcgei0
a
The FRCvme is a set of drivers which handles the Universe II device. The following
functions are supported:
SMaster windows
SPARC/CPU−56T53
InstallationBoard Installation
SSlave windows
SInterrupts
SDMA controller
SVME arbiter
SMailboxes
Additionally, the FRCvme package provides a common programming interface for
application and driver development.
FRCflash
For more detailed information and board−specific notes, refer to the
Installation and Reference Guide
a and theaSolaris VMEbus Driver Programmer’s Guide.a
aSolaris Driver Package
The Solaris 2.x flash memory driver provides access to the flash memory device.
Depending on the CPU board′s switch settings, the flash memory is accessible as one user
flash or is divided into a boot and a user section.
a
The following table shows the effects the different CPU board switch settings have on the
flash segmentation and the flash write protection.
Table 10: Flash Segmentation and Write Protection
SW1−1 Setting
OFFOFF16 MByte user flash, write−protectedPLCC PROM
ONOFF16 MByte user flash, not
OFFON1 MByte boot flash + 15 MByte user
ONON1 MByte boot flash + 15 MByte user
SW1−2 SettingFlash Segmentation/Write−ProtectionBoot from
write−protected
flash, write−protected
flash, not write−protected
a
PLCC PROM
Flash memory device
Flash memory device
FRCctrl
The FRCctrl driver contains the sysconfig device driver which offers the following
features:
SSets all user LEDs
SAccesses the temperature sensor devices
To enable the temperature sensors, set the OpenBoot environment variable
env−monitor before booting. To do so, enter at the prompt:
setenv env−monitor enabled
54SPARC/CPU−56T
Board InstallationInstallation
SEnables and triggers watchdog functions
To enable the watchdog, set switch SW1−3 to ON
SIncreases the volume of a headphone (if applicable)
FRCplatmod
This driver ensures proper error handling for IDE devices. It should be installed
immediately after the Solaris installation has been completed.
a
If this driver is not installed, the system may send error messages or can panic in case of
IDE error handling.
The following figure shows the connectors, keys and LEDs available on the front panel of
the CPU board.
R
S
T
123
4
S
E
R
A
B
K
B
D
M
S
E
E
T
H
1
E
T
H
2
a
P
M
C
4
P
S
C
S
I
1
S
C
S
I
2
M
C
3
P
M
C
2
Figure 4: CPU Board’s Front Panel
SPARC/CPU−56T57
Controls, Indicators, and ConnectorsFront Panel
LEDs
All four LEDs available at the front panel are multi−purpose LEDs. Depending on the
values contained in the LED control registers 1 to 4, they indicate either the board status
or different network activities. Furthermore, all LEDs can be operated in user LED
mode.
Registers".
Table 11: Description of Front Panel LEDs
aa For details about the LED control registers, refer to chapter Maps and
a
LED
1Board Status (default)
2User−LED Mode (default)
Description
Red: Board reset
Weak red (on pressing the RST key): Board abort
Weak red (during operation): 12V power supply on VME backplane not within its
limits
Green: Board running
Blinking red/weak red: No PCI activity within last two seconds
Blinking green: No boot code found
Blinking weak red: 5V power supply on VME backplane not within its limit
IDE Activity
Depending on LED control register 1 settings, the LED indicates the activity of IDE 1
or IDE 2.a
Ethernet Activity
Depending on LED control register 1 settings, the LED indicates activity of Ethernet
interfaces 1 to 4 or a combination of these
User−LED Mode
Via LED control register 1, the LED can be programmed to be OFF, green or red.
Via LED control register 2 the LED can be programmed to be red, green or OFF.
Furthermore it can be programmed to be blinking green or blinking red with
different blinking frequencies. By default, the LED is OFF.a
Ethernet Activity
Depending on LED control register 2 settings, the LED indicates activity of Ethernet
interfaces 1 to 4 or a combination of these
58SPARC/CPU−56T
Front PanelControls, Indicators, and Connectors
LEDDescription
3VME Bus Activity (default)
Red: Universe II asserted VME SYSFAIL signal to the VMEbus
Green: Universe II accesses the VMEbus as master
OFF: No SYSFAIL signal asserted and no Universe PCI−to−VME bridge activity
Ethernet Activity
Depending on LED control register 3 settings, the LED indicates activity of Ethernet
interfaces 1 to 4 or a combination of these
User−LED Mode
Via LED control register 3, the LED can be programmed to be OFF, green or red.
4User−LED Mode (default)
Via LED control register 4, the LED can be programmed to be red, green or OFF.
Furthermore, it can be programmed to be blinking green or blinking red with
different blinking frequencies. By default, the LED is OFF.a
Ethernet Activity
Depending on LED control register 4 settings, the LED indicates activity of Ethernet
interfaces 1 to 4 or a combination of these.
Key
The front panel of the CPU board provides one key.a
R
S
T
123
This key has two functions. When pressed longer than 0.5 s, a reset is generated which is
indicated by the LED 1 shining red. When the key is pressed for a period shorther than 0.5
s, an abort is generated which is indicated by the LED 1 shining weak red.
Note:aAn abort should only be triggered if an application under Solaris or OpenBoot
hangs. Do not trigger an abort to enter OpenBoot or to bypass the diagnostic routine
during power up. After triggering an abort , the board is in diagnostic mode and the
OpenBoot ok prompt appears. In this mode, you can diagnose what caused the
program to hang. However, the board is not fully initialized and therefore is not fully
functional. To regain the full functionality, you need to trigger a reset.
Connectors
4
a
The board provides the following connectors at its front panel:
SSerial
SPARC/CPU−56T59
Controls, Indicators, and ConnectorsFront Panel
SKeyboard/Mouse
SEthernet
SSCSI
Serial I/O
Two serial RS−232 interfaces A and B are available via two Mini D−Sub 9 connectors.
Their pinouts are given below.
a
SERA_DSR
6
SERA_RTS
7
SERA_CTS
8
SERA_RI
9
Figure 5: Serial A Connector Pinout
SERB_DSR
6
SERB_RTS
7
SERB_CTS
8
SERB_RI/5V
9
Figure 6: Serial B Connector Pinout
The signal provided by pin 9 of serial interface B depends on the value of the OpenBoot
variable tty−rs422−enable?. If it is set to true, pin 9 holds 5V and serves as power feed for
the ACC/CABLE/RS−422 cable connected to this interface. If the OpenBoot variable
tty−rs422−enable? is set to false, pin 9 holds the signal SERB_RI and the serial interface B
is a standard RS−232 interface.
Keyboard/Mouse
A SUN−type keyboard/mouse can be connected via an 8−pin Mini DIN connector. Its
pinout is given below.a
If you use an PS/2 splitter adapter cable, two PS/2 interfaces are available. One PS/2
interface can be used for connecting a keyboard, the second for connecting a mouse. Their
respective pinouts are given below.
2
1
Keyboard Data
1
GND
3
Keyboard Clock
5
3
5
Figure 8: PS/2 Keyboard Connector Pinout
60SPARC/CPU−56T
4
6
a
n.c.
2
Vcc
4
n.c.
6
Front PanelControls, Indicators, and Connectors
2
1
Mouse Data
1
GND
3
Mouse Clock
5
3
5
4
6
n.c.
Vcc
n.c.
2
4
6
Figure 9: PS/2 Mouse Connector Pinout
Ethernet
Ethernet 1 and 2 are available via two RJ−45 connectors. Ethernet 1 is of type 10/100BaseT
and Ethernet 2 of type 10/100/1000BaseT. The respective pinouts are given below.
ETH1_TX+
1
ETH1_TX−
2
ETH1_RX+
3
NC
4
NC
5
ETH1_RX−
6
NC
7
NC
8
Figure 10: Ethernet 1 Connector Pinout
ETH2_MDI0+
1
ETH2_MDI0−
2
ETH2_MDI1+
3
ETH2_MDI2+
4
ETH2_MDI2−
5
ETH2_MDI1−
6
ETH2_MDI3+
7
ETH2_MDI3−
8
Figure 11: Ethernet 2 Connector Pinout
1
8
1
8
a
Note:aThe Ethernet 1 interface is also accessible as Ethernet 3 via the IOBP−CPU−56 .
Both interfaces can not be accessed at the same time. The selection is made
automatically by OpenBoot when booting the board and cannot be reversed anymore
until the board is rebooted.
a
SCSI
Two SCSI interfaces 1 and 2 are available via two mini 68−pole SCSI4 connectors. Their
pinout is given below.
Note:aBy default the SCSI termination is switched ON for SCSI interface 1 and 2. It
can be switched OFF via switches. For details, see section Switch Settings".
62SPARC/CPU−56T
On−Board ConnectorsControls, Indicators, and Connectors
On−Board Connectors
The following connectors are on−board:
SPMC
SMemory module
SIDE
SVME
PMC
The I/O board provides the following PMC connectors:
PMC ConnectorsCorresponding PMC Slot
Pn31 − Pn33PMC #4
Pn21 − Pn24PMC #3
Pn11 − Pn13
PMC#4PMC#3PMC#2
Figure 13: Location of PMC Connectors
PMC #2
The connectors corresponding to PMC slots 2 and 4 are standard and are therefore not
described in this guide.
a
The PMC connectors corresponding to PMC slot 3 provide the additional connector
Pn24.
a
SPARC/CPU−56T63
Controls, Indicators, and ConnectorsOn−Board Connectors
Pn24
642
1
63
PMC#3
It carries user I/O signals that are routed to the I/O board′ s IOBP. There they are
available via an on−board PMC connector. For details, refer to the
Installation Guide.
UltraSPARC IIi+ ProcessorDevices’ Features and Data Paths
UltraSPARC IIi+ Processor
The UltraSPARC IIi+ processor is based on the SPARC V9 architecture with VIS
instruction set and supports up to 4 GByte of memory. Important features are:
S650 MHz frequency
SFour−way superscalar processor
S64−bit data paths
S64−bit address arithmetic
S41−bit virtual addressing
S16 KByte instruction cache
S16 KByte non−blocking primary data cache
S512 KByte second level cache
SSensors for observing CPU on−die temperature
SPARC/CPU−56T75
Devices’ Features and Data PathsInterrupt Controller
Interrupt Controller
The UltraSPARC−IIi+ provides a 6−bit wide interrupt vector for 63 interrupt sources.a
The UPA interrupt concentrator (UIC) provides the inputs for all necessary interrupts. It
monitors all interrupts using a round−robin scheme with 33 MHz, converts them to a
device−own vector and transmits this vector to the processor. The PCI interrupts engine
(PIE) reflects every vector in one state bit. From the state bit a new vector is generated and
transmitted to the processor′s execution unit. If more than one interrupt state bit is active,
the transmitting sequence of the new interrupt vector is priority controlled.a
Every interrupt routed to the interrupt controller can be enabled or disabled separately in
the interrupt source and in the processor.
a
76SPARC/CPU−56T
PCI Bus ADevices’ Features and Data Paths
PCI Bus A
PCI bus A is the primary PCI bus. It runs at 33 MHz and is 32 bit wide. The following
devices are connected to it:
SEthernet controller
SSCSI controller
SSENTINEL64 PCI−to−PCI bridge
SUniverse
Ethernet Controller
The used Ethernet controller is an Intel 82540. It corresponds to Ethernet interface 2
available via the front panel and supports 10/100/1000BaseT Ethernet. Further important
features are:
SIntegrated PHY in a small package (uBGA196)
SCompatibility with IEEE 802.3/Ethernet
SDMA capability
SInterrupt generation
SCSI Controller
The used SCSI controller is a LSI53C1010. It supports two dual U2W LVD SCSI buses with
a SCSI data transfer rate of up to 160 MByte/s for each channel. Both SCSI interfaces are
available via the front panel.
Two interrupts are generated by the SCSI controller for interrupting the main processor.a
Both SCSI interfaces have an on−board termination which can be enabled and disabled
via on−board switches. By default, the SCSI termination is enabled.
a
SENTINEL64 PCI−to−PCI Bridge
The SENTINEL64 PCI−To−PCI bridge is used to connect the primary PCI bus A to the
secondary PCI bus B. For details about the SENTINEL64 device refer to the SENTINEL64
Reference Guide available via the Force Computers S.M.A.R.T. server.
PCI−to−VME Bridge
a
a
The used PCI−To−VME bridge is a Tundra Universe II device. Its main features are:
SFully compliant to VME64 bus standard
SPARC/CPU−56T77
Devices’ Features and Data PathsPCI Bus A
SIntegral FIFOs for write posting to maximize bandwidth utilization
SProgrammable DMA controller with linked−list mode
SCPU or peripheral boards functioning as both master and slave in the
SSustained transfer rates up to 60−70 Mbytes/s
Note:aWhen operating the board in system slot 1, the system clock is disabled while
the board is in reset. This is a limitation of the Universe II device.
a
78SPARC/CPU−56T
PCI Bus BDevices’ Features and Data Paths
PCI Bus B
PCI bus B runs at 33 MHz and is 64 bit wide. It is the secondary PCI bus of the CPU board
and has the following devices attached to it:
SEthernet controller
SSouthbridge
SPCIO−2 controller
SPMC module
Ethernet Controller
The Ethernet controller used at PCI bus B is the same as is used at PCI bus A.a
Southbridge
The used Southbridge is an ALI M1535D+. It provides the following interfaces:
STwo IDE channels with ATA−100
SParallel interface
SFloppy disk interface
SPS/2 keyboard/mouse interface
a
SSUN keyboard/mouse interface via two serial interfaces
PCIO−2 Controller
The used PCIO−2 controller is a SUN SME2300. It is a single−chip I/O subsystem using a
single PCI load and providing the following interfaces:
SExpansion bus (EBus) interface
SFour USB interfaces
SMedia Independent Interface (MII)
EBus Interface
The PCIO−2 controller acts as EBus controller of the attached EBus. A description of all
devices attached to the EBus is given below.
SPARC/CPU−56T79
a
Devices’ Features and Data PathsPCI Bus B
Media Independent Interface
Two on−board Intel LXT971 PHY devices are connected to the MII. They transform the
MII into a 10/100BaseT Ethernet interface which is available either via front panel or via
IOBP.
a
Important features of the PHY device are:
SSupport for ISO/IEC 8802−3 Ethernet
SSupport for Shielded Twisted Pair (STP) and Unshielded Twisted Pair (UTP)
category−5 cables of up to 100 meters length
SOperation in half−duplex and full−duplex mode possible
SSpeed adjustion either manually or via auto−negotiation
USB Interfaces
Four USB channels are provided with each channel supporting 1.5 MBit/s and 12 MBit/s.
All USB interfaces provide auto resume from power managed (suspended) state.
a
The USB interfaces 1, 2 and 3 are routed to the CPU board′s IOBP where they are available
via three front connectors. USB interface 4 is unused.
a
The USB interfaces provide the host controllers for USB transfers and a four−port
integrated hub. The host controller manages the control and data flow. It also provides
connection management and provides status information. The hub enables tiered star
topology to provide multiple connections.
a
80SPARC/CPU−56T
EBusDevices’ Features and Data Paths
EBus
The EBus is a generic slave 8−bit wide Direct Memory Access (DMA) bus (pseudo ISA
bus) to which the following devices are connected:
SField−Programmable Gate Array (FPGA)
SPLCC PROM and flash memory device
SReal time clock and NVRAM
SQuad serial controller
FPGA
The used FPGA is a Spartan XCS20XL device made by XILINX. It provides the following
main features:
Watchdog
SWatchdog
STimer
STemperature sensor control
2
STwo local I
C interfaces
SEthernet interface 1/3 switching
SLED and switch control
SReset control
The CPU board′s watchdog is implemented inside the FPGA. It is used to reset the board
after a configured time, if no software trigger occurred. If enabled in the Interrupt Enable
Control register, an interrupt will be generated before the watchdog timer runs out.
a
The watchdog can be enabled by setting SW1−3 to ON. It starts with the first trigger of the
watchdog trigger bit in the Watchdog Trigger register. After the watchdog was started, it
is not possible to stop it anymore.
a
The Watchdog Timer Control Register allows to specify the time after which an interrupt
is generated and after which a reset is issued. For both, values between 125 ms up to 1
hour in 15 steps are possible. The value of each following step is increased by a factor of
between 1.5 and 3. To be compatible to the predecessor board SPARC/CPU−54, the time
after which a reset is issued after a reset is set to 2.5 s and the time after which an
SPARC/CPU−56T81
Devices’ Features and Data PathsEBus
interrupt is generated is set to 1.25s. Once the watchdog timer is running, it is only
possible to reduce the watchdog run out time.
a
Timer
The FPGA contains two timers which can be used as two independent 16−bit count−down
timers with a timer interval of 10 µs and a maximum run−out time of 655.35 ms. Two
independent interrupts are possible which can be enabled or disabled with the Interrupt
Enable Control register. One counter read−back register set is also available which shows
the correct timer values.
a
Both timers can be combined to run as one 32−bit count−down timer with a timer interval
of 10 µs and a total run−out time of 42949.67295 s (or 11 h, 55 min, 49 s and 672.95 ms). In
this mode only one interrupt is possible.
a
The timer counts down from its initial value to zero in steps of 10 µs. The initial value can
be set by software from 1 to 65535 in 16−bit mode or from 1 to 4294967295 in the 32−bit
mode, which results in a timer period of 10 µs to 655.35 ms in the 16−bit mode or of 10 µs
to 42949.67295s in the 32−bit mode. If the timer has reached zero, an interrupt is
generated, if enabled, and the timer loads its initial value to count down again.
A detailed description of all registers related to the timers is given in the chapter "Maps
and Registers".
a
Temperature Sensor Control
The on−board temperature sensor device MAX1617 measures the temperatures of the
CPU board and the CPU. If the measured temperatures is not within a pre−defined range
between lower and upper temperature, bit 2 is set in the External Failure Register and, if
enabled, an interrupt is generated.
Local I2C Interface
2
Two separate I
C buses are available on the CPU board. Both are implemented in the
Xilinx FPGA and have the following devices attached to them:
SSerial Presence Detects (SPDs)
SOn−board temperature sensor
SBoard Information Blocks (BIBs)
BIBs are used for internal purposes only and are therefore not further described in this
guide. All other devices are I2C bus slaves and are identified by unique addresses which
are given in the table below.
DeviceI2C BusI2C Bus Slave Address
Temperature sensor MAX161720011.000
SPD CPU−56 PROM Bank 1−4 24C04 Serial E2PROM21010.00x
SPD MEM−550 PROM Bank 1−4 24C04 Serial E2PROM21010.01x
a
a
2
2
2
82SPARC/CPU−56T
EBusDevices’ Features and Data Paths
Ethernet Interface 1/3 Switching
As mentioned earlier in this guide, Ethernet interface 1 is available via front panel and
Ethernet interface 3 via the CPU board′s IOBP. Only one of both interfaces can be active at
the same time.
a
The selection which interface is active is made at board reset by the FPGA′s internal logic.
It depends on the Miscellaneous Control Register bits 5 to 7 and on which Ethernet
interface provides a link. The Miscellaneous Control Register is set by OpenBoot while
booting the board. For information on how to change the default setting, refer to
aSPARC/CPU−56(T) OpenBoot Enhancements Programmer4s Guidea which is available via
the
the Force Computers S.M.A.R.T. service.
By default, the selection is made as described in the following table.
Link at Interface 1aLink at Interface 3Activated Ethernet Interface
Ye sYe s1
Ye sN o1
NoYes3
No
LED and Switch Control
The FPGA internal logic is responsible for:
SControl of front panel LEDs
SReadback of switches SW1−4
Reset Control
The FPGA handles all resets and distributes them to the CPU. Possible reset sources are
listed in the following table.
Table 12: Reset Sources
a
No1
a
Reset Source
Watchdog resetOn expiry, the watchdog timer can generate a
Front panel keyDepending on the time the key is pressed, either a
Two−pin connector on CPU board′s IOBPBy shortcutting this connector a reset is issued
VMEbus
SPARC/CPU−56T83
Description
reset.a
reset or a board abort is issued
Two directions are possible: the VMEbus resets the
CPU board or the CPU board resets the VME bus
Devices’ Features and Data PathsEBus
Reset SourceDescription
Power−up resetIf one or more on−board voltages are not within
their thresholds, a reset is issued
PMC resetA PMC module in non−monarch mode can reset
the CPU board
PLCC PROM and Flash Memory Device
The following memory devices are connected to the EBus:
SOne PLCC PROM with 1 MByte address space
SOne flash memory device with 16 MByte address space
The PLCC PROM is the device from which the CPU board boots by default.
The 16 MByte flash memory device can be used as:
SUser flash memory of 16 MBytes
SBoot flash memory of 1 MByte with the remaining 15 MBytes used as user flash
memory
The selection between both operation modes is made via on−board switches.
Whether to boot from the PLCC PROM or the flash memory device, is determined by
switch SW1−2. After booting, the whole PLCC PROM is switched off, regardless of the
position of switch SW 1−2. Switch SW1−1 is used to enable write−protection of the flash
memory device. If this switch is OFF (default), the flash memory device is
write−protected. In order to copy the PLCC PROM content to the flash memory device,
switch SW1−1 must be switched ON and switch SW1−2 must be set to OFF.
Real−Time Clock and NVRAM
The CPU board provides the M48T35AV with an real−time clock (RTC) and a non−volatile
RAM (NVRAM) which offers the following features:
a
a
a
S32 KByte ultra−low power CMOS SRAM
SByte−wide accessible real−time clock
a
SLong−life lithium carbon mono fluoride battery
SYear−2000 compliant RTC with own crystal
Serial Controller
The CPU board provides four independent full−duplex serial I/O interfaces. They are
implemented via the Quad Enhanced Serial Communication Controller 16C554 by Texas
Instruments.
84SPARC/CPU−56T
EBusDevices’ Features and Data Paths
The device offers the following features:
SFour independent full−duplex serial channels
SFour independent baud rate generators
SHardware handshake support (RTS/CTS/DTR/DTS/RI/DCD)
SInterrupt controlled
Interface 1 and 2 are available on the front panel via two micro DSub connectors. The
interfaces 3 and 4 are routed to the SPARC/IOBP−CPU−56 via the P2 connector.
a
SPARC/CPU−56T85
Devices’ Features and Data PathsPCI Bus C
PCI Bus C
PCI Bus C has the following devices attached to it:
The data width provided by PCI bus C is 64 bit. The bus speed depends on the PMC
modules installed into slot 3 and 4. If no PMC modules are installed or only PMC
modules which support 66 MHz, the bus speed is 66 MHz. In all other cases the bus speed
is 33 MHz.
The OpenBoot firmware consists of the Common Operations and Reset Environment
(CORE), the power−on selftest (POST), the OpenBoot Diagnostics (OBDIAG), and the
OpenBoot itself as well as support for the VxWorks real−time operating system (RTOS).
The OpenBoot firmware is subject to changes. For the newest version and how to
upgrade, refer to the SMART service accessible via the Force Computers World Wide Web
site (www.forcecomputers.com).
Note:aThe appearance of the on−screen output shown in the examples can differ from
the appearance of the output on your monitor according to your device tree (CPU
architecture).
For more information on the OpenBoot firmware, see theaOpenBoot 4.x Manual Set.
CORE
CORE is responsible for setting up proper environments for booting purposes. It first
initializes the system to a status where different firmware can be loaded from.
a
CORE automatically transfers control to its clients (such as OpenBoot, VxWorks, Chorus
Booter...) during power up.
a
Furthermore, it provides a unified interface for using public CORE functions. Thus, the
CORE unifies system initialization and minimizes modifications within the upper level
firmware.
a
The following figure gives a system overview of which systems are initialized by CORE.
Running from
PROM
Running from
Memory
Operating
System
FVM
Solaris
Basic System Initialization
CORE with bPOST
Basic
Loader
Basic OS
BSP
VxWorks
RTOS
cPOST
Figure 24: OpenBoot CORE Overview
88SPARC/CPU−56T
IntroductionOpenBoot Firmware
Additionally, CORE is designed to reach the following goals:
SAbility to use I/O devices including serial port, flash, floppy, and net early on the cold
boot sequence of a firmware client.a
SBasic system tests that can replace existing POST in min. mode.
SSystem testing may be done using the POST drop−in in max. mode.
SError recovery from exceptions which currently do not exist in OpenBoot and from
any fatal conditions during flash update
SDeveloping standard validation test suites that could prevent major bugs in CORE
and clients
SSample client codes that could facilitate any client porting
CORE Workflow
The following figure describes the workflow of CORE.
YES
FALSE
MIN
Power−On Switch
Control+P
NO
<diag−switch?>
TRUE
bPOST
<diag−level>
MAX
Control+U
NO
user−interface
FALSE
cPOST
(Client)
Control+U
NO
Client
YES
TRUE
YES
CORE
User Interface
NO
If no activity
detected for 10 sec.
YES
SPARC/CPU−56T89
OpenBoot FirmwareIntroduction
CORE Commands
In order to change or interrupt the boot process in CORE, the following commands can be
executed:
SSkip POST: <Control>+<P>
SEnter user interface: <Control>+<U>
SUser default NVRAM variables for this run: <Control>+<N>a
STurn−on messages (if <diag−switch> is set to true): <Control>+<M>a
POST
At hardware power−on or button power−on, the CORE firmware executes POST if the
NVRAM configuration parameter <diag−switch?> was set to true beforehand. The extents
of certain tests executed within in the POST depend on the state of the configuration
parameter <diag−level>.
You choose between minimal or maximal testing by setting this configuration parameter
to min or max. If the NVRAM configuration parameter <diag−switch?> is true for each
test, a message is displayed on a terminal connected to the serial I/O interface A.
If the system does not work correctly, error messages will be displayed which indicate the
problem. After POST, the OpenBoot firmware boots an operating system or enters the
Forth monitor, if the NVRAM configuration parameter <auto−boot?> is false.
OpenBoot
a
a
a
Booting the system is the most important function of the OpenBoot firmware.
Booting is the process of loading and executing a stand−alone program such as the
operating system. After the system is powered on, it usually boots automatically after it
has passed POST which occurs without user intervention.
a
If necessary, you can explicitly initiate the boot process from the OpenBoot command
prompt. Automatic booting uses the default boot device specified in the nonvolatile RAM
(NVRAM). User−initiated booting either uses the default boot device or one specified by
the user.
a
In order to boot the system from the default boot device with default settings, enter the
following command at the Forth monitor prompt ok:
okaboot
The boot command has the following format:
90SPARC/CPU−56T
IntroductionOpenBoot Firmware
boot <device−specifier> <filename> <−bootoption>
Optional Boot Parameters
Table 13: Boot Parameters
ParameterDescription
<device−specifier>Name (full path or alias) of the boot device. Typical values are
cdrom, disk, floppy, net or tape.
<filename>Name of program to be booted
The filename parameter is relative to the root of the selected
device. If no filename is specified, the boot command uses the
value of the boot file NVRAM parameter. The NVRAM
parameters used for booting are described in the following
section.a
<−bootoption>
Boot Devices
To explicitly boot from the internal disks using the Forth Monitor, enter:
okaboot disk
or
okaboot disk−2
To retrieve a list of all device alias definitions, enter at the Forth Monitor command
prompt:
devalias
The following table lists device aliases available for SCSI devices.a
Table 14: OpenBoot Aliases for SCSI Devices
Alias
Bootoption may be one of the following:a
−a: Prompts interactively for device and name of boot file
−h: Halts after loading program
−r: Reconfigures Solaris device drivers after changing
hardware configuration
−v: Prints verbose information during boot procedure
The following table lists device aliases available for other devices.a
Table 15: OpenBoot Aliases for Miscellaneous Devices
Alias
cdrom−3CD−ROM partition f, on−board IDE secondary master
disk−3Disk, on−board IDE primary master
disk33Disk, on−board IDE secondary slave
disk32Disk, on−board IDE secondary master
disk31Disk, on−board IDE primary slave
disk30Disk, on−board IDE primary master
ideon−board IDE
ebusEBus
flashFlash EPROM
flash−progaFlash EPROM programming mode
Device
floppyFloppy disk
keyboardaKeyboard
mouseMouse
netEthernet 1 interface via front panel
net2Ethernet interface 2
net3Ethernet 3 interface via IOBP
pciPrimary PCI bus
ttya
SPARC/CPU−56T93
Serial interface A
OpenBoot FirmwareIntroduction
AliasDevice
ttybSerial interface B
tyycSerial interface C
tyydSerial interface D
vme
OBDIAG
OBDIAG stands for OpenBoot Diagnostics and is an additional diagnostics drop−in driver
program which serves as an NVRAM configuration feature.
It allows to test the hardware by calling OBDIAG when the OpenBoot firmware is present
and the <ok> prompt has appeared. During the start−up sequence of the CPU, OpenBoot
searches for the presence of devices on all expansion buses and evaluates their
characteristics such as device ID, device type, vendor ID, and revision ID. In order to test
the hardware, OBDIAG requires selftest methods for the discovered devices. If OBDIAG
does not find any selftest methods in the device nodes, it looks for its own selftest
methods.
Executing OBDIAG
There are two different methods to execute OBDIAG:
a) Via Script
b) Manually
VME
a
a
Via Script
In order to execute OBDIAG via script, set two configuration variables by enterring:
setenv mfg−mode chamber
setenv diag−switch? true
Now a script of additional diagnostic tests is executed automatically after each POST from
OBDIAG provided that POST has been running without failure during hardware power
on.
Manually
In order to execute OBDIAG manually, enter the following command at the ok prompt:
obdiag
94SPARC/CPU−56T
IntroductionOpenBoot Firmware
When OBDIAG is called, the <obdiag> test prompt appears and you can now choose the
required test. You can run single tests, a number of tests, all tests, or all tests with
exceptions. If the test has passed successfully, a short test comment will appear on screen.
In order to return to the main menu, hit the enter key.
Terminating OBDIAG
In order to terminate OBDIAG and return to OpenBoot, enter
exit
a
The OpenBoot prompt will then reappear.a
OBDIAG Commands
Apart from testing the hardware, you can also call several commands which can be seen
in the ODBIAG main menu. The following table provides an overview of these
commands.
a
Table 16: OBDIAG Commands
CommandaDescriptiona
exitExits obdiag tool
helpPrints this help information
setenvSets diagnostic configuration variable to new value
printenvsPrints values for diagnostic configuration variables
versionsPrints selftests, library, and obdiag tool versions
test−allTests all devices displayed in the main menu
test 1,2,5Tests devices 1, 2, and 5
except 2,5Tests all devices except for devices 2 and 5
what 1,2,5
Prints some selected properties for devices 1, 2, and 5
OBDIAG provides a brief excerpt of the OpenBoot configuration variables. The values of
the variables are displayed after entering the following command:
printenvs
You can decide whether the chosen test will either stop at the occurrence of the first error
or continue to test the hardware. It is also possible to run the test more than once or
produce a detailed print−out of the test.
The example below shows the detailed print out of an OBDIAG test.
Selftest at /pci@1f,0/ebus@1 .................................... passed
aa
Hit any key to return to the main menuaa<cr>
obdiag>aexit <cr>
ok
VxWorks Support
ThePLCC PROM delivered together with the CPU board contains support for the
real−time operating system VxWorks 5.4 from WindRiver Systems. A VxWorks booter,
bootrom.hex" image, is provided as dropin named bootrom". In order to execute it,
enter at the CORE command prompt;
execute bootrom
To automatically start the VxWorks booter at power up, enter:
set kernel bootrom
96SPARC/CPU−56T
NVRAM Boot ParametersOpenBoot Firmware
NVRAM Boot Parameters
The OpenBoot firmware holds its configuration parameters in NVRAM. To see a list of all
available configuration parameters, enter at the Forth Monitor prompt:
As you can see in the list, the default setting is for the CPU board to boot the operating
system automatically. If this is not the case, ensure that the <auto−boot?> parameter is set
to true.
aprintenv
To set specific parameters, use the setenv command as follows:
<configuration_parameter> <value>
asetenv
The configuration parameters in the following table are involved in the boot process.
Table 17: OpenBoot Configuration Parameters
ParameterDefault ValueDescription
auto−boot?trueIf true, automatic booting after power on or reset
boot−devicediskDevice from which to boot
boot−fileempty stringFile to boot
diag−switch?falseIf true, run in diagnostic mode, test results are
shown, boot up takes longer
If false, normal mode, short boot up
diag−devicenetDevice from which to boot in diagnostic mode
diag−file
empty stringFile to boot in diagnostic mode
When booting an operating system or another stand−alone program, and neither a boot
device nor a filename is supplied, the boot command of the Forth monitor takes the
omitted values from the NVRAM configuration parameters. If the parameter
<diag−switch?> is false, the parameters <boot−device> and <boot−file> are used.
Otherwise, the OpenBoot firmware uses the parameters <diag−device> and <diag−file>
for booting.
SPARC/CPU−56T97
OpenBoot FirmwareDiagnostics
Diagnostics
The Forth Monitor includes several diagnostic routines. These on−board tests let you
check devices such as network controller, SCSI devices, floppy disk system, memory,
clock, keyboard and audio. User−installed devices can be tested if their firmware includes
a self−test routine.
The table below lists several diagnostic routines.
Table 18: Diagnostic Routines
Command
probe−scsiIdentifies devices connected to the on−board SCSI controller
probe−scsi−all [<device−path>]Performs probe−SCSI on all SCSI controllers installed in the
test [<device−specifier>]Executes the specified device’s self−test method.
test−all [<device−specifier>]Tests all devices that have a built−in self−test method and
watch−clockMonitors the clock function.
watch−netMonitors network connection via primary Ethernet
probe−ideIdentifies devices connected to IDE bus
probe−ide−all [<device−path>]
SCSI Bus
Description
system below the specified device tree node. If
<device−path> is omitted, the root node is used.
<device−specifier> may be a device path name or a device
alias.
Example:
test net − test network connection
that reside below the specified device tree node. If
<device−specifier> is omitted, the root node is used.
Performs probe−ide on all IDE buses installed in the system
below the specified device tree. If <device path> is omitted,
the root node is used.a
To check the on−board SCSI#1 or SCSI#2 for connected devices, enter:a
okaprobe−scsi
Primary UltraSCSI bus:
Target 1
aaaUnit 0aaaDiskaaaaaWDIGTLaaWDE9100 ULTRA2aa1.21
−
Secondary UltraSCSI bus:
−
ok
All SCSI Buses
To check all SCSI buses installed in the system, enter the following:a
98SPARC/CPU−56T
DiagnosticsOpenBoot Firmware
probe−scsi−all
The actual response depends on the devices on the SCSI buses.
Note:aA terminal message as answer to the command probe−scsi−all can take up to two
minutes.
okaprobe−scsi−all
/pci@1f,0/scsi@2
aa
Target 6
Unit 0 Disk Removable Read Only Device SONY CD−ROM CDU−8012 3.1a
aa
/pci@1f/pci@4,1/scsi@2
aa
Target 3
Unit 0 Disk FUJITSU M2952ESP SUN2.1G2545
ok
Single Device
To test a single installed device, enter:
test <device−specifier>
This executes the self−test device method of the specified device node.
Group of Devices
To test a group of installed devices, enter:
test−all
All devices below the root node of the device tree are tested. The response depends on the
devices having a self−test method. If a device specifier option is supplied at the command
line, all devices below the specified device tree node are tested.
Clock
To test the clock function enter:
okawatch−clock
Watching the ‘seconds’ register of the real time clock chip.
It should be ‘ticking’ once a second.
Type any key to stop.
22
ok
SPARC/CPU−56T99
OpenBoot FirmwareDiagnostics
The system responds by incrementing a number every second. Press any key to stop the
test.
Network
To monitor the network connection enter:
okawatch−net
Internal loopback test −− succeeded.
Transceiver check −− Using Onboard transceiver −− Link Up.
passed
Using Onboard transceiver −− Link Up.
Looking for Ethernet packets.
‘.’ is a good packet. ‘X’ is a bad packet.
Type any key to stop.
The system monitors the network traffic. It displays a dot (.) each time it receives a valid
packet and displays an X each time it receives a packet with an error which can be
detected by the network hardware interface.
a
IDE Devices
The following is an example output obtained after enterring probe−ide.a
okaprobe−ide
aaaDevice 0aa( Primary Master )
aaaaaaaaaaNot Present
aa
aaaDevice 1aa( Primary Slave )
aaaaaaaaaaNot Present
aa
aaaDevice 2aa( Secondary Master )
aaaaaaaaaaRemovable ATAPI Model: TOSHIBA CD−ROM XM−6702B
aa
aaaDevice 3aa( Secondary Slave )
aaaaaaaaaaNot Present
aa
ok
100SPARC/CPU−56T
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