ON Semiconductor NCV81599, NCP81599 User manual

USB Power Delivery 4-Switch Buck Boost Controller

NCV81599, NCP81599

The NCV81599 USB Power Delivery (PD) Controller is a synchronous buck boost that is optimized for converting battery voltage or adaptor voltage into power supply rails required in notebook, tablet, and desktop systems, as well as many other consumer devices using USB PD standard and C−Type cables. The NCV81599 is fully compliant to the USB Power Delivery Specification when used in conjunction with a USB PD or C−Type Interface Controller. NCV81599 is designed for applications requiring dynamically controlled slew rate limited output voltage that require either voltage higher or lower than the input voltage. The NCV81599 drives 4 NMOSFET switches, allowing it to buck or boost and support the functions specified in the USB Power Delivery Specification which is suitable for all USB PD applications. The USB PD Buck Boost Controller operates with a supply and load range of 4.5 V to 32 V.

Features

• Wide Input Voltage Range:

from 4.5 V to 32 V for NCV81599 from 4.5 V to 28 V for NCP81599

• Dynamically Programmed Frequency from 150 kHz to 1.2 MHz

• I

C Interface

• Real Time Power Good Indication

• Controlled Slew Rate Voltage Transitioning

• Feedback Pin with Internally Programmed Reference

• Support USBPD/QC2.0/QC3.0 Profile

• 2 Independent Current Sensing Inputs

• Over Temperature Protection

• Adaptive Non−Overlap Gate Drivers

• Over−Voltage and Over−Current Protection

• AEC−Q100 Qualified (NCV81599)

• 5 x 5 mm QFN32 Package

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QFN32 5x5, 0.5P

CASE 485CE

(NCP81599)

MARKING DIAGRAM

NCx81599

AWLYYWWG

NCx81599 = Specific Device Code x = V or P A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G = Pb−Free Package

(Note: Microdot may be in either location)

Typical Application

QFNW32 5x5, 0.5P

CASE 484AB

(NCV81599)

• Automotive USB Charging Ports

• Wireless Charging

• Consumer Electronics

ORDERING INFORMATION

Device Package Shipping

NCV81599MWTXG QFN32

(Pb−Free)

NCP81599MNTXG QFN32

(Pb−Free)

†For information on tape and reel specifications, including part orientation

and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.

March, 2021 − Rev. 3

5000 / Tape & Reel

2500 / Tape & Reel

†

1 Publication Order Number:

NCV81599/D

VCCD

Current Sense 1

Current Sense 2

Curret Limit Indicator

ADDR

VCCD

DRV

Interrupt

Enable

I2C

NCV81599, NCP81599

RS2

CB2

VBUS

RPU

CO1

RPD

VCCD

VDRV

VCC

CS1

CS2

CLIND

INT

SDA

SCL

ADDR

COMP

AGND

THPAD

CSP1

CSN1

CSN2

CSP2

BST2

BST1

HSG1 VSW1 HSG2 VSW2

LSG1

PGND1

LSG2

PGND2

PDRV

RS1

CB1

HSG1

LSG1

PGND1

CSN1

CSP1

CS1

CLIND

Figure 1. Typical Application Circuit

VSW1

BST1

VCC

VDRV

31 30 29 28 27 26 2532

Exposed Thermal Pad

(THPAD)

INT

SCL

SDA

ADDR

VCCD

AGND

VSW2

1514131211109 16

COMP

BST2

HSG2

LSG2

PGND2

CSP2

CSN2

CS2

PDRV

Figure 2. Pinout

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NCV81599, NCP81599

ADDR

VCC

VDRV

CS1

CS2

CLIND

VCCD

SDA

SCL

INT

COMP

CONFIG

VDRV

CS1

CLIMP1

CLIMP2

CS2

CLIND

0.8V

CONFIG

4.0V

VCC

−

I2C ADDR

SETTING

4.0V

−

I2C

Interface

AGND

−

Startup

INPUT

UVLO

−

EN_MASK

EN_INT

LOGIC

INT

Vcc_rdy

OV2_th

CLINDP1

CLINDP2

Value

Configuration

Registers

VDRV_rdy

−

CLIND

ADC

Digital

Status

THPAD

PDRV

V2_OVLO

Analog

Mux

Registers

Master OSC

Oscillator

Reference

VFB

CONFIG

V1 CS1 CS2

Limit

0_Ramp

OCP

logic

VFB

PG_High

VFB

Ramp_0

Ramp_180

Error OTA

500μS/100μS

SW1 SW2 SW3 SW4

PG TS

CLIND

PG_Low

OV_REF

CS2_INT

CS1_INT

−

∑

Shutdown

Boot1 _UVLO

Control

Logic

LOGIC

0_Ramp

CS1_INT

CS2_INT

CS1_INT

180_Ramp

−

v1_OVLO

Thermal

OV_MSK

PG_MSK

PG/ OV/

CONFIG

CSP1

CS1

CS1_INT

Logic_1

Drive

Logic_2

Boot2 _UVLO

CS2

CS2_INT CSN2

Boot1V

NOL

Drive

NOL

Buck Logic Boost Logic Buck Boost

Logic

VFB

VDRV

SW1

SW4

OV1_th

CSP1

CSN1

BST1

HSG1

VSW1

LSG1

PGND1

PGND2

LSG2

VSW2

HSG2

BST2

Boot2 V

CSP2

CSN2

PDRV

SW2

SW3

Figure 3. Block Diagram

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NCV81599, NCP81599

Table 1. PIN FUNCTION DESCRIPTION

Pin Pin Name Description

1 HSG1 S1 gate drive. Drives the S1 N−channel MOSFET with a voltage equal to VDRV superimposed on the switch

2 LSG1 Drives the gate of the S2 N−channel MOSFET between ground and VDRV.

3, 22 PGND Power ground for the low side MOSFET drivers. Connect these pins closely to the source of the bottom

4 CSN1 Negative terminal of the current sense amplifier.

5 CSP1 Positive terminal of the current sense amplifier.

6 V1 Input voltage of the converter

7 CS1 Current sense amplifier output. CS1 will source a current that is proportional to the voltage across RS1 to an

8 CLIND Open drain output, high voltage on CLIND pin indicates that the CS1 or CS2 voltage has exceeded the I2C

9 SDA I2C interface data line.

10 SCL I2C interface clock line.

11 INT Interrupt is an open drain output that indicates the state of the output power, the internal thermal trip, and oth-

12 ADDR

13−14 AGND The ground pin for the analog circuitry.

15 COMP Output of the transconductance amplifier used for stability in closed loop operation.

16 EN Logic high enables the switching and logic low shuts down and reset the device. Middle level makes the de-

17 PDRV The open drain output used to control a PMOSFET.

18 CS2 Current sense amplifier output. CS2 will source a current that is proportional to the voltage across RS2 to an

19 FB Feedback voltage of the output, negative terminal of the gm amplifier.

20 CSN2 Negative terminal of the current sense amplifier.

21 CSP2 Positive terminal of the current sense amplifier.

23 LSG2 Drives the gate of the S3 N−channel MOSFET between ground and VDRV.

24 HSG2 S4 gate drive. Drives the S4 N−channel MOSFET with a voltage equal to VDRV superimposed on the switch

25 BST2 Bootstrapped Driver Supply. The BST2 pin swings from a forward voltage drop below VDRV up to a forward

26 VSW2 Switch Node. VSW2 pin swings from a diode voltage drop below ground up to output voltage.

27 V2 Output voltage of the converter. Connect to the output externally for OVLO sense.

28 VCCD

29 VDRV

30 VCC The VCC pin supplies power to the internal circuitry. The VCC is the output of a linear regulator which is pow-

31 VSW1 Switch Node. VSW1 pin swings from a diode voltage drop below ground up to V1.

32 BST1 Bootstrapped Driver Supply. The BST1 pin swings from a forward voltage drop below VDRV up to a forward

33 THPAD Center Thermal Pad. Connect to AGND externally.

node voltage VSW1.

N−channel MOSFETs.

external resistor. CS1 voltage can be monitored with a high impedance input. Ground this pin if not used.

programmed limit.

er I

C programmable functions.

I2C address pin, placing a less than 200 kW resistor to the ground to set the I2C address.

vice to stop switching and keep the VCC alive.

external resistor. CS2 voltage can be monitored with a high impedance input. Ground this pin if not used.

node voltage VSW2.

voltage drop below VOUT + VDRV. Place a 0.1 mF capacitor from this pin to VSW2.

Internal digital power supply input. Always connect VCCD to VCC. A 1 mF capacitor should be placed close to the part to decouple this line.

Internal voltage supply to the driver circuits. A 1 mF capacitor should be placed close to the part to decouple this line.

ered from V1. Pin should be decoupled with a 1 mF capacitor for stable operation.

voltage drop below V1 + VDRV. Place a 0.1 mF capacitor from this pin to VSW1.

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NCV81599, NCP81599

Table 2. MAXIMUM RATINGS

Over operating free−air temperature range unless otherwise noted

Rating

VCCD Input Voltage VCCD −0.3 5.5 V

Address Pin Output Voltage ADDR −0.3 5.5 V

Driver Input Voltage VDRV −0.3 5.5 V

Internal Regulator Output VCC −0.3 5.5 V

Output of Current Sense Amplifiers CS1, CS2 −0.3 5.5 V

Current Limit Indicator CLIND −0.3 VCC + 0.3 V

Interrupt Indicator INT −0.3 VCC + 0.3 V

Enable Input EN −0.3 5.5 V

I2C Communication Lines SDA, SCL −0.3 VCC + 0.3 V

Compensation Output COMP −0.3 VCC + 0.3 V

V1 Power Stage Input Voltage V1 −0.3 35 V, 40 V (20 ns) V

Positive Current Sense CSP1 −0.3 35 V, 40 V (20 ns) V

Negative Current Sense CSN1 −0.3 35 V, 40 V (20 ns) V

Positive Current Sense CSP2 −0.3 35 V, 40 V (20 ns) V

Negative Current Sense CSN2 −0.3 35 V, 40 V (20 ns) V

Feedback Voltage FB −0.3 5.5 V

Driver 1 and Driver 2 Positive Rails BST1,

High Side Driver 1 and Driver 2 HSG1,

Switching Nodes and Return Path of Driver 1 and Driver 2 VSW1, VSW2 −2.0 V,

Low Side Driver 1 and Driver 2 LSG1, LSG2 −0.3 V 5.5 V

PMOSFET Driver PDRV −0.3 35 V, 40 V (20 ns) V

Voltage Differential AGND to PGND −0.3 0.3 V

CSP1−CSN1, CSP2−CSN2 Differential Voltage CS1DIF, CS2DIF −0.5 0.5 V

PDRV Maximum Current PDRVI 0 10 mA

PDRV Maximum Pulse Current (100 ms on time, with > 1 s interval)

Maximum VCC Current VCCI 0 mA

Operating Junction Temperature Range (Note 1) TJ −40 150 °C

Operating Ambient Temperature Range TA −40 125 °C

Storage Temperature Range TSTG −55 150 °C

Thermal Characteristics (Note 2) QFN 32 5mm x 5mm Maximum Power Dissipation @ TA = 25°C Maximum Power Dissipation @ TA = 85°C Thermal Resistance Junction−to−Air with Solder Thermal Resistance Junction−to−Case Top with Solder Thermal Resistance Junction−to−Case Bottom with Solder

Lead Temperature Soldering (10 sec): Reflow (SMD styles only) Pb−Free (Note 3)

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.

1. The maximum package power dissipation limit must not be exceeded.

2. The value of QJA is measured with the device mounted on a 3in x 3in, 4 layer, 0.062 inch FR−4 board with 1.5 oz. copper on the top and bottom layers and 0.5 ounce copper on the inner layers, in a still air environment with T

3. 60−180 seconds minimum above 237°C.

Symbol Min Max Unit

−0.3 V wrt/PGND

BST2

HSG2

PDRVIPUL 0 200 mA

PD PD RQJA RQJCT RQJCB

RF 260 Peak °C

−0.3 V wrt/VSW

−0.3 V wrt/PGND

−0.3 V wrt/VSW

−5 V (100 ns)

4.1

2.1 30

1.7

2.0

A = 25°C.

40 V

5.5 V wrt/VSW

40 V

5.5 V wrt/VSW

35 V, 40 V (20 ns) V

°C/W °C/W °C/W

W W

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NCV81599, NCP81599

Table 3. ELECTRICAL CHARACTERISTICS

= 12 V, V

(V1

= 5 V , T

out

Parameter

POWER SUPPLY

V1 Operating Input Voltage V1

VDRV Operating Input Voltage VDRV 4.5 5 5.5 V

VCCD Operating Input Voltage VCCD 4.5 5.5 V

VCC UVLO Rising Threshold VCC

VCC UVLO Falling Threshold VCC

UVLO Hysteresis for VCC VCCV

VDRV UVLO Rising Threshold VDRV

VDRV UVLO Falling Threshold VDRV

VDRV UVLO Hysteresis VDRV

VCC Output Voltage VCC With no external load 4.5 5 V

VCC Drop Out Voltage VCCDROOP 30 mA load 100 mV

VCC Output Current Limit IOUT

VCC Short Current Limit IVCC_SHORT VCC short 14.6 mA

V1 Shutdown Supply Current IVCC_SD EN < 0.4 V, V1 = 12 V 8.0 15

V1 Normal Current IV1 0.8 V < EN < 1.88 V, 4.5 V ≤ V1 ≤

VCCD Standby Current IVCCD 0.8 V < EN < 1.88 V 4 mA

VCCD Switching Current IVCCD_SW EN > 2.2 V 4.1 mA

VDRIVE Switching Current Buck IV1_SW EN = 5 V, Cgate = 2.2 nF,

VDRIVE Switching Current Boost IV1_SW EN = 5 V, Cgate = 2.2 nF,

VOLTAGE OUTPUT

Voltage Output Accuracy

Voltage Accuracy Over Temperature

TRANSCONDUCTANCE AMPLIFIER

Gain Bandwidth Product

Transconductance GM1 Default 500

Max Output Source Current limit GMSOC 60 80

Max Output Sink Current limit GMSIC 60 80

Voltage Ramp Vramp 1.2 V

INTERNAL BST SWITCH

Pass FET Rds(on)

Reverse Leakage Current from BST pin to VDRV pin

BST−VSW UVLO BST

4. Ensured by design. Not production tested.

5. Typical value only. Not production tested.

= +25°C for typical value; −40°C < T

Symbol Test Conditions Min Typ Max Units

RISE

FALL

HYS

RISE

FALL

HYS

VCC

FB DAC_TARGET = 00110010

VOUTERT VFB ≥ 0.5 V

VOUTER T

GBW (Note 4) 5.2 MHz

RBST IF = 1 mA 60

DIL BST = 32 V, T

_UVLO

= TJ < 125°C for min/max values unless noted otherwise)

NCV81599 4.5 32

NCP81599 4.5 28

4.21 4.27 4.35 V

3.90 3.96 4.06 V

Falling Hysteresis 300 mV

4.21 4.31 4.35 V

3.90 4.01 4.06 V

300 mV

VCC Loaded to 4.3 V, EN > 0.8 V 80 97 mA

7.3 mA

32 V, (No Switching)

16 mA

VSW = 0 V, FSW = 600 kHz

15 mA

VSW = 0 V, FSW = 600 kHz

DAC_TARGET = 01111000 DAC_TARGET = 11001000

1.188

1.98

−1.0

0.495

VFB < 0.5 V

= 25°C

VFB ≥ 0.5 V −0.45 0.45

−5

0.5

1.2

2.0

0.505

1.212

2.02

1.0 5

= 25°C 0.05 1

Falling 3.2 3.5 3.8 V

Rising 3.4 3.7 4.1 V

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NCV81599, NCP81599

Table 3. ELECTRICAL CHARACTERISTICS (continued)

= 12 V, V

(V1

= 5 V , T

out

Parameter UnitsMaxTypMinTest ConditionsSymbol

INTERNAL BST SWITCH

BST−VSW Hysteresis

OSCILLATOR

Oscillator Frequency

Oscillator Frequency Accuracy FSWE −12 12 %

Minimum On Time MOT Measured at 10% to 90% of VCC (Note 4) 100 ns

Minimum Off Time MOFT Measured at 90% to 10% of VCC (Note 4) 100 ns

INT THRESHOLDS

Interrupt Low Voltage

Interrupt High Leakage Current INII 5 V 3 100 nA

Interrupt Startup Delay INTPG Soft Start end to PG positive edge 2.1 ms

Interrupt Propagation Delay

Power Good Threshold

FB Overvoltage Threshold FB_OV 115 %

Overvoltage Propagation Delay VFB_OVDL 1 Cycle

EXTERNAL CURRENT SENSE (CS1,CS2)

Positive Current Measurement High

Transconductance Gain Factor CSGT Current Sense Transconductance

Transconductance Deviation CSGE

Input Current Sense Common Mode Range

Output Current Sense Common Mode Range

Input Sense Voltage Full Scale ISVFS (Note 4) 100 mV

CS Output Voltage Range CSOR VSENSE = 100 mV Rset = 6k (Note 4) 0 3 V

EXTERNAL CURRENT LIMIT (CLIND)

Current Limit Indicator Output Low

Current Limit Indicator Output High Leakage Current

INTERNAL CURRENT SENSE

Internal Current Sense Gain for PWM

4. Ensured by design. Not production tested.

5. Typical value only. Not production tested.

= +25°C for typical value; −40°C < T

BST

_HYS

FSW_0

VINTI IINT(sink) = 2 mA 0.2 V

PGI Delay for power good in 3.3 ms

PGO Delay for power good out 100 ns

PGTH Power Good in from falling

PGTH Power Good out from rising

CS10 CSP1−CSN1 or CSP2−CSN2 = 25 mV 125

CSCMMR_I CSP1 is tied to V1 4.5 32 V

CSCMMR_O 4 25.5 V

CLINDL

ICLINDH Pull up to 5 V 65 100 nA

ICG CSPx−CSNx = 25 mV 9.4 10 10.5 V/V

= TJ < 125°C for min/max values unless noted otherwise)

(Note 4) 200 mV

FSW = 001 (Note 5) 150

FSW = 000, default 552 600 648

FSW = 010 300

FSW = 011 450

FSW = 100 740

FSW = 101 880

FSW = 110 1145

104

Power Good out from falling

106

Power Good in from rising

5 mS

Vsense = 10 mV to 100 mV

CSPx−CSNx = 10 mV −30 30

CSPx−CSNx = 25 mV to 100 mV −20 20

Input current = 500 mA

7.0 100 mV

kHz

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NCV81599, NCP81599

Table 3. ELECTRICAL CHARACTERISTICS (continued)

= 12 V, V

(V1

= 5 V , T

out

Parameter UnitsMaxTypMinTest ConditionsSymbol

INTERNAL CURRENT SENSE

Positive Peak Current Limit Trip

Positive Peak Current Limit Latch−off OCP_L CLIP = 00 (default)

Negative Valley Current Limit Trip NVCLT CLIN = 00 (default)

SWITCHING MOSFET DRIVERS

HSG1 Pullup Resistance

HSG1 Pulldown Resistance HSG1_PD BST−VSW = 5 V 0.8

LSG1 Pullup Resistance LSG1_PU LSG −PGND = 5 V 2.4

LSG1 Pulldown Resistance LSG1_PD LSG −PGND = 5 V 0.7

HSG2 Pullup Resistance HSG2_PU BST−VSW = 5 V 2.7

HSG2 Pulldown Resistance HSG2_PD BST−VSW = 5 V 0.9

LSG2 Pullup Resistance LSG2_PU LSG −PGND = 5 V 2.0

LSG2 Pulldown Resistance LSG2_PD LSG −PGND = 5 V 0.7

HSG1 Falling to LSG1 Rising Delay HSLSD1 16 ns

LSG1 Falling to HSG1 Rising Delay LSHSD1 36 ns

HSG2 Falling to LSG2 Rising Delay HSLSD2 35 ns

LSG2 Falling to HSG2 Rising Delay LSHSD2 56 ns

SLEW RATE/SOFT START

Charge Slew Rate (VOUT measured at V2 pin)

Discharge Slew Rate (VOUT measured at V2 pin)

ENABLE

EN LDO High Threshold Voltage

EN LDO Low Threshold Voltage ENLDOLT 530 570 mV

EN Switching High Threshold Voltage ENHT 2.15 V

EN Switching Low Threshold Voltage ENLT 1.65 1.87 V

EN Pull Up Current (Default on) IEN_UP EN = 0.8 V 3.0

ADDR

Internal Current Source

ADDR0 ADDR = 74 H 110 mV

ADDR1 ADDR = 75 H 220 260 300 mV

ADDR2 ADDR = 76 H 380 440 500 mV

ADDR3 ADDR = 77 H 600 715 830 mV

4. Ensured by design. Not production tested.

5. Typical value only. Not production tested.

= +25°C for typical value; −40°C < T

PPCLT CLIP = 00 (default)

HSG1_PU BST−VSW = 5 V 2

SLEWP Slew = 00, FB = 0.1 VOUT

SLEWN Slew = 00, FB = 0.1 VOUT

ENLDOHT 770 810 mV

IADDR 9 10 11

= TJ < 125°C for min/max values unless noted otherwise)

34 39 CLIP = 01 CLIP = 10 CLIP = 11

CLIP = 01 CLIP = 10 CLIP = 11

34 40 CLIN = 01 CLIN = 10 CLIN = 11

Slew = 01, FB = 0.1 VOUT Slew = 10, FB = 0.1 VOUT Slew = 11, FB = 0.1 VOUT

44 mV

11 70

70 39 23

106

45 mV 25 15

0.6

1.2

2.4

4.8

−0.6

−1.2

−2.4

−4.8

mV/ms

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NCV81599, NCP81599

Table 3. ELECTRICAL CHARACTERISTICS (continued)

= 12 V, V

(V1

= 5 V , T

out

Parameter UnitsMaxTypMinTest ConditionsSymbol

I2C INTERFACE

Voltage Threshold Rising

Voltage Threshold Falling I2CVTH_F 0.9 V

Communication Speed I2CSP 1 MHz

THERMAL SHUTDOWN

Thermal Shutdown Threshold

Thermal Shutdown Hysteresis TSDHYS (Note 4) 28 °C

PDRV

PDRV Operating Range

PDRV Leakage Current PDRV_IDS FET OFF, VPDRV = 32 V 180 nA

PDRV Drain−Source Voltage PDRV_VDS ISNK = 10 mA 0.20 V

INTERNAL ADC

Range

LSB Value ADCLSB (Note 4) 20 mV

Error ADCFE (Note 4) 1 LSB

INPUT OVLO

Input OVLO Rising Threshold

Input OVLO Falling Threshold V

Input OVLO Debounce Time (Note 4) 2

Input OVLO Recover Debounce Time (Note 4) 1 ms

OUTPUT OVLO

Output OVLO Threshold (Register 06h, bit [5:4])

Output OVLO Debounce Time (Note 4) 1

4. Ensured by design. Not production tested.

5. Typical value only. Not production tested.

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions.

= +25°C for typical value; −40°C < T

I2CVTH_R 1.2 V

TSD (Note 4) 151 °C

ADCRN (Note 4) 0 2.55 V

OVLOIN_R

OVLOIN_F

OVLO_O

= TJ < 125°C for min/max values unless noted otherwise)

0 32 V

sel_v2th = 00 sel_v2th = 01 sel_v2th = 10 (Default) sel_v2th = 11

34 V

28.5 V

22.5 30 36

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NCV81599, NCP81599

TYPICAL CHARACTERISTICS

Figure 1. Switching Frequency vs.

Temperature

Figure 3. VCC Load Regulation Figure 4. VCC Line Regulation (20 mA Load)

Figure 2. VCC vs. Temperature

Figure 5. Shutdown Supply Current vs.

Temperature

Figure 6. V1 Normal Current vs. Temperature

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