ON Semiconductor NCV81071 User Manual
Dual 5 A High Speed
Low-Side MOSFET Drivers
with Enable
NCV81071
NCV81071 is a high speed dual low−side MOSFETs driver. It is
capable of providing large peak currents into capacitive loads. This
driver can deliver 5 A peak current at the Miller plateau region to help
reduce the Miller effect during MOSFETs switching transition. This
driver also provides enable functions to give users better control
capability in different applications. ENA and ENB are implemented
on pin 1 and pin 8 which were previously unused in the industry
standard pin−out. They are internally pulled up to driver’s input
voltage for active high logic and can be left open for standard
operations.
Features
• High Current Drive Capability ±5 A
• TTL/CMOS Compatible Inputs Independent of Supply Voltage
• Industry Standard Pin−out
• Enable Functions for Each Driver
• 8 ns Typical Rise and 8 ns Typical Fall Times with 1.8 nF Load
• Typical Propagation Delay Times of 20 ns with Input Falling and
20ns with Input Rising
• Input Voltage from 4.5 V to 20 V
• Dual Outputs can be Paralleled for Higher Drive Current
• Fully Specified from −40°C to +140°C
• AEC−Q100 Qualified and PPAP Capable
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Applications
• Server Power
• Telecommunication, Datacenter Power
• Synchronous Rectifier
• Switch Mode Power Supply
• DC/DC Converter
• Power Factor Correction
• Motor Drive
• Renewable Energy, Solar Inverter
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MARKING
DIAGRAM
V71x
8
AYW
G
ENB
OUTA
VDD
OUTB
MSOP−8
Z SUFFIX
CASE 846AM
V71x = Specific Device Code
x = A, B or C
A = Assembly Location
Y = Year
W = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
PIN CONNECTIONS
1
ENA
INA
GND
INB
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
© Semiconductor Components Industries, LLC, 2016
March, 2021 − Rev. 1
1 Publication Order Number:
NCV81071/D
NCV81071
ENA
INA
ENB
INB
Ref
Ref
Ref
Ref
VDD
VDD
Ref
Ref
Ref
Ref
VDD
VDD
VDD
VDD
VDD
OUTA
OUTB
GND
UVLO
ENA
INA
ENB
INB
Logic
A Channel
VDD
Logic
B Channel
VDD
Ref
Ref
VDD
Ref
Ref
VDD
VDD
VDD
OUTA
VDD
OUTB
GND
VDD
VDD
VDD
VDD
NCV81071A NCV81071B
A Channel
VDD
UVLO
B Channel
Logic
Logic
ENA
INA
ENB
INB
A Channel
VDD
UVLO
B Channel
Logic
Logic
VDD
VDD
VDD
OUTA
VDD
OUTB
GND
NCV81071C
Figure 1. NCV81071 Block Diagram
Table 1. PIN DESCRIPTION
Pin No. Symbol Description
1 ENA Enable input for the driver channel A with logic compatible threshold and hysteresis. This pin is used to en-
2 INA Input of driver channel A which has logic compatible threshold and hysteresis. If not used, this pin should be
3 GND Common ground. This ground should be connected very closely to the source of the power MOSFET.
4 INB Input of driver channel B which has logic compatible threshold and hysteresis. If not used, this pin should be
5 OUTB Output of driver channel B. The driver is able to provide 5 A drive current to the gate of the power MOSFET.
6 VDD Supply voltage. Use this pin to connect the input power for the driver device.
7 OUTA Output of driver channel A. The driver is able to provide 5 A drive current to the gate of the power MOSFET.
8 ENB Enable input for the driver channel B with logic compatible threshold and hysteresis. This pin is used to en-
able and disable the driver output. It is internally pulled up to VDD with a 200 kW resistor for active high operation. The output of the pin when the device is disabled will be always low.
connected to either VDD or GND. It should not be left unconnected.
connected to either VDD or GND. It should not be left unconnected.
able and disable the driver output. It is internally pulled up to VDD with a 200 kW resistor for active high operation. The output of the pin when the device is disabled will be always low.
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NCV81071
TYPICAL APPLICATION CIRCUIT
ENA
INA
GND
INB
NCV81071
1
2
3
4
8
7
6
5
ENB
OUTA
VDD
OUTB
Table 2. ABSOLUTE MAXIMUM RATINGS
Value
Min Max
Supply Voltage VDD −0.3 24 V
Output Current (DC) Iout_dc 0.3 A
Output Current (Pulse < 0.5 ms)
Input Voltage INA, INB −6.0 VDD+0.3
Enable Voltage ENA, ENB −0.3 VDD+0.3
Output Voltage OUTA, OUTB −0.3 VDD+0.3 V
Junction Operation Temperature T
Storage Temperature T
Electrostatic Discharge
OUTA OUTB Latch−up Protection 500 mA
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
Iout_pulse 6.0 A
J
stg
Human body model, HBM 5500
Charge device model, CDM 2500
−40 150
−65 160
Unit
V
°C
V
Table 3. RECOMMENDED OPERATING CONDITIONS
Parameter Rating Unit
VDD supply Voltage 4.5 to 20 V
INA, INB input voltage −5.0 to VDD V
ENA, ENB input voltage 0 to VDD V
Junction Temperature Range −40 to +140 °C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
Table 4. THERMAL INFORMATION
Package
MSOP−8 EP 39 4.7 11
1. YJT: approximate thermal impedance, junction−to−case top.
qJA (5C/W) qJC (5C/W) YJT (5C/W) (Note 1)
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NCV81071
Table 5. INPUT/OUTPUT TABLE
NCV81071A NCV81071B NCV81071C
ENA ENB INA INB
H H L L H H L L H L
H H L H H L L H H H
H H H L L H H L L L
H H H H L L H H L H
L L Any Any L L L L L L
Any Any x (Note 2) x (Note 2) L L L L L L
x (Note 2) x (Note 2) L L H H L L H L
x (Note 2) x (Note 2) L H H L L H H H
x (Note 2) x (Note 2) H L L H H L L L
x (Note 2) x (Note 2) H H L L H H L H
2. Floating condition, internal resistive pull up or pull down configures output condition
OUTA OUTB OUTA OUTB OUTA OUTB
PRODUCT MATRIX
NCV81071A NCV81071B NCV81071C
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