ON Semiconductor NCV78825 User Manual

NCV78825

High Efficiency 3 A Synchronous Buck Dual LED Driver with Integrated High Side Switch and Current Sensing for

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Automotive Front Lighting

Description

The NCV78825 is a single−chip and high efficient Synchronous Buck Dual LED Driver designed for automotive front lighting applications like high beam, low beam, DRL (daytime running light), turn indicator, fog light, static cornering, etc. The NCV78825 is in particular designed for high current LEDs and provides a complete solution to drive 2 LED strings of up−to 60 V. It includes 2 independent current regulators for the LED strings and required diagnostic features for automotive front lighting with a minimum of external components – the chip doesn’t need any external sense resistor for the buck current regulation. The available output current and voltages can be customized per individual LED string. When more than 2 LED channels are required on 1 module, then 2, 3 or more devices NCV78825 can be combined; also with NCV787x3 devices – the predecessor of the NCV78825. Thanks to the SPI programmability, one single hardware configuration can support various application platforms.

Features

A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G = Pb−Free Package

• Single Chip

• Buck Topology

• 2 LED Strings up−to 60 V

• High Current Capability up to 3 A DC per Output

See detailed ordering and shipping information on page 2 o this data sheet.

ORDERING INFORMATION

• Integrated High Side Switch

• Low Side Pre−driver for External NMOS Device

• High Overall Efficiency

• Minimum of External Components

• Integrated High Accuracy Current Sensing

• Integrated Switched Mode Buck Current Regulator

• Average Current Regulation Through the LEDs

• High Operating Frequencies to Reduce Inductor Sizes

• Low EMC Emission for LED Switching and Dimming

ypical Applications

• High Beam

• Low Beam

• DRL

• Position or Park Light

• Turn Indicator

• Fog

• Static Cornering

• SPI Interface for Dynamic Control of System Parameters

• Fail Safe Operating (FSO) Mode, Stand−Alone Mode

• Master−Slave Synchronization Mode of the Buck Channels

• NCV Prefix for Automotive and Other Applications Requiring

Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable

• This is a Pb−Free Device

SSOP36 EP

CASE 940AB

MARKING DIAGRAM

NV78825−0

AWLYYWWG

February, 2018 − Rev. 1

1 Publication Order Number:

NCV78825/D

NCV78825

ORDERING INFORMATION

Table 1. AVAILABLE PART NUMBERS

Device Marking Package* Shipping

NCV78825DQ0R2G NV78825−0 SSOP36 EP

1500 / Tape & Reel

(PbFree)

*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting

Techniques Reference Manual, SOLDERRM/D.

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specification Brochure, BRD8011/D.

TYPICAL APPLICATION SCHEMATIC

VBOOST

C_M3V

†

μC

VIO of MCU

R_SDO

VDRIVE

C_DRV

C_DD

VINBCK1

VBOOST

LBCKSW1

VDRIVE

VDD_C

RSTB LEDCTRL1

LEDCTRL2 SCLK SDI SDO

CSB

TEST

NCV78825

TEST1

TEST2

VBOOSTM3V

GND

LSFET1

GNDS1

VLED1

VINBCK2

LBCKSW2

LSFET2 GNDS2

VLED2

EXPOSED

PAD

R_LED_1

R_LED_2

Figure 1. Typical Application Schematic

L_BCK_1

T_LS 1

C_LED_1

L_BCK_2

T_LS 2

C_LED_2

LED−string 1

C_BCK_1

LED−string 2

C_BCK_2

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Table 2. EXTERNAL COMPONENTS

Component

L_BCK_x Buck regulator coil (see BUCK REGULATOR chapter for details) 47 (22) μH

C_BCK_x

C_M3V

C_DD

C_DRV C_LED_x R_LED_x

R_SDO

T_LSx

1. Pin TEST has to be connected to ground. TEST1 and TEST2 pins can be connected to ground or left floating.

2. C_LED_x is optional. If used, time constant of the C_LED_x and R_LED_x filter has to be lower than minimal LEDCTRLx PWM time for proper VLED measurement.

3. R_LED_x is necessary to ensure Absolute maximum ratings of IVLEDx current (see Table 4).

4. GNDSx pins have to be star connections to the corresponding S of the external LS FET.

Buck regulator output capacitor (see BUCK REGULATOR chapter for details) 220 nF Capacitor for M3V regulator 470 (see Table 8) nF VDD decoupling capacitor 470 (see Table 7) nF V

decoupling capacitor 470 nF

DRIVE

Optional VLEDx pin filter capacitor (Note 2) 1 nF VLEDx pin serial resistor (Notes 2 and 3) 1 kΩ SPI pull−up resistor 1 kΩ Buck regulator low side switch (LS FET) NVTFS5C680NL,

Function Typ. Value Unit

NVMFS5C673NL

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NCV78825

VDRIVE

(4.5 V – 10 V)

VDD_C

LEDCTRL1 LEDCTRL2

RSTB

SDI

SCLK

CSB SDO

TEST

TEST1 TEST2

VGATE

LDO

Bandgap

POR

Bias

OSC

5 V input

5 V input/

OD output

LV IOs

2−Channel Buck

Vref

Digital control

ADC

MUX

Dividers

Temp

OTP

CTRL

VBOOSTM3V

regulator

Current

sense CMP

Predriver

VGATE

Current

sense CMP

Predriver

VGATE

VBOOST

VBOOSTM3V

VINBCK11

VINBCK12

LBCKSW11

LBCKSW12

LSFET1

GNDS1

VLED1

VINBCK21

VINBCK22

LBCKSW21

LBCKSW22

LSFET2

GNDS2 VLED2

EXPOSED PAD

VDD,

VLEDx

VBOOST,

GND

Figure 2. Block Diagram

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NCV78825

RSTB

SDO

SCLK

SDI

CSB

LSFET1

GNDS1

VBOOST

VBOOSTM3V

LEDCTRL1

LEDCTRL2

TEST

TEST1

VDRIVE

LSFET2

GNDS2

GND

TEST2

VDD_C

LBCKSW11

LBCKSW12

VLED1

VINBCK11

VINBCK12

SELF PROT PDMOS

Figure 3. ESD Schematic

SELF PROT PDMOS

LBCKSW21

LBCKSW22

VLED2

VINBCK21

VINBCK22

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RSTB

SDO

2 3

SCLK

SDI

CSB LSFET1

GNDS1

8 9

VBOOST

VBOOSTM3V NC

11 12

LBCKSW11

LBCKSW12

VLED1

VINBCK11

VINBCK12

NCV78825

LEDCTRL1 LEDCTRL2

TEST

TEST1 VDRIVE LSFET2

GNDS2

GND

TEST2

VDD_C

NC LBCKSW21 LBCKSW22

VLED2

VINBCK21 VINBCK22

36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19

Figure 4. Pin Connections − SSOP36−EP (Top View)

Table 3. PIN DESCRIPTION

Pin No.

SSOP36−EP

VBOOST Supply

Voltage

1 2 SDO SPI data output MV open−drain 3 SCLK SPI clock MV in 4 SDI SPI data input MV in 5 CSB SPI chip select (chip select bar) MV in 6 LSFET1 Buck 1 driver output for ext. low side switch MV out 7 GNDS1 Buck 1 ground sense for ext. low side switch MV out

8, 11, 14, 16, 21, 23, 26 GND/NC GND/NC connection in application NC

9 VBOOST Booster input voltage pin HV supply 10 VBOOSTM3V VBOOSTM3V regulator output pin HV out (supply) 12 LBCKSW11 Buck 1 switch output HV out 13 LBCKSW12 Buck 1 switch output HV out 15 VLED1 LED String 1 Forward Voltage Sense Input HV in 17 VINBCK11 Buck 1 high voltage supply HV supply 18 VINBCK12 Buck 1 high voltage supply HV supply 19 VINBCK22 Buck 2 high voltage supply HV supply 20 VINBCK21 Buck 2 high voltage supply HV supply 22 VLED2 LED String 2 Forward Voltage Sense Input HV in 24 LBCKSW22 Buck 2 switch output HV out

Pin Name Description I/O Type

RSTB External reset signal MV in

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NCV78825

Table 3. PIN DESCRIPTION (continued)

Pin No.

SSOP36−EP

25 LBCKSW21 Buck 2 switch output HV out 27 VDD_C 3.3 V logic supply LV supply 28 TEST2 Internal function. To be tied to GND or left open LV in/out 29 GND Ground Ground 30 GNDS2 Buck 2 ground sense for ext. low side switch MV out 31 LSFET2 Buck 2 driver output for ext. low side switch MV out 32 VDRIVE Pre−driver supply MV supply 33 TEST1 Internal function. To be tied to GND or left open LV in/out 34 TEST Internal function. To be tied to GND LV in 35 LEDCTRL2 LED string 2 enable MV in 36 LEDCTRL1 LED string 1 enable MV in

EP EXPOSED PAD To be tied to GND

Table 4. ABSOLUTE MAXIMUM RATINGS

Characteristic

VBOOST Supply Voltage V VINBCKx Supply Voltage (Note 1) VINBCKx Max of

VBOOSTM3V Supply Voltage (Note 2) VBOOSTM3V Max of V VDRIVE Supply Voltage VDRIVE −0.3 12 V LSFETx Voltage (Note 3) LSFETx −0.3 Min of VDRIVE + 0.3, 12 V VLED Sense Voltage VLEDx −0.3 Min of V Logic Supply Voltage (Note 4) V Medium Voltage IO Pins IOMV −0.3 7.0 V Test Pins (Note 5) TESTx −0.3 Min of V Buck Switch Low Side (Note 1) LBCKSWx −2 VINBCKx + 0.3 V VLED Sink/source Current IVLEDx −30 30 mA Storage Temperature (Note 6) T The Exposed Pad (Note 7) EXPAD GND − 0.3 GND + 0.3 V The LS Pre−driver Sense GND Voltage GNDSx GND − 0.3 GND + 0.3 V Electrostatic Discharge on Component

Level Human Body Model (Note 8) Electrostatic Discharge on Component

Level Charge Device Model (Note 8)

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.

1. V(VINBCKx − LBCKSWx) < 70 V, the driver in off state.

2. The VBOOSTM3V regulator in off state.

3. The LSFETx driver in HiZ state.

4. Absolute maximum rating for pins: VDD, TEST. Also valid for relative difference VBOOST − VBOOSTM3V.

5. Absolute maximum rating for pins: TEST1, TEST2.

6. For limited time up to 100 hours. Otherwise the max storage temperature is 85°C.

7. The exposed pad must be hard wired to GND pin in the application to ensure both electrical and thermal connection.

8. This device series incorporates ESD protection and is tested by the following methods: ESD Human Body Model tested per AECQ100002 (EIA−JESD22A114−B) ESD Charge Device Model tested per EIA−JESD22C101 Latchup Current Maximum Rating: 100 mA per JEDEC standard: JESD78

Symbol Min Max Unit

BOOST

STRG

ESD_HBM

ESD_CDM

VBOOSTM3V − 0.3, −0.3

−0.3 68 V Min of V

BOOST

− 3.6, −0.3 Min of V

BOOST

−0.3 3.6 V

−50 150 °C

−2 +2 kV

−500 +500 V

I/O TypeDescriptionPin Name

+ 0.3, 68 V

+ 0.3, 3.6 V

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NCV78825

Operating ranges define the limits for functional operation and parametric characteristics of the device. A mission profile (Note 1) is a substantial part of the operation

conditions; hence the Customer must contact ON Semiconductor in order to mutually agree in writing on the allowed missions profile(s) in the application.

Table 5. RECOMMENDED OPERATING RANGES

Characteristic

Boost Supply Voltage V VINBCKx Supply Voltage (Note 2) VINBCKx V VDRIVE Voltage Supply VDRIVE 4.5 10 V Buck Switch Peak Output Current I_LBCKSW 3.8 A Functional Operating Junction

Temperature Range (Note 3) Parametric Operating Junction

Temperature Range (Note 4) The Exposed Pad Connection (Note 5) EXPOSED_PAD GND − 0.1 GND GND + 0.1 V The LS Pre−driver Sense GND Voltage

(Note 6)

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability.

1. A mission profile describes the application specific conditions such as, but not limited to, the cumulative operating conditions over life time,

the system power dissipation, the system’s environmental conditions, the thermal design of the customer’s system, the modes, in which the device is operated by the customer, etc. No more than 100 cumulated hours in life time above T

2. Hard connection of VINBCKx to VBOOST on PCB.

3. The circuit functionality is not guaranteed outside the functional operating junction temperature range. Also please note that the device is

verified on bench for operation up to 170°C but that the production test guarantees 155°C only.

4. The parametric characteristics of the circuit are not guaranteed outside the Parametric operating junction temperature range.

5. The exposed pad must be hard wired to GND pin in an application to ensure both electrical and thermal connection.

6. The hard connection of the GNDSx pins on the PCB, mainly to the S of the LS NMOS device

corresponding S of the LS NMOS max +/− 0.2 mV.

Symbol Min Typ Max Unit

BOOST

GNDSx GND − 0.1 GND GND + 0.1 mV

6 67 V

− 0.1 V

BOOST

−40 155 °C

−40 150 °C

BOOST

+ 0.1 V

BOOST

the voltage difference between the pin and

Table 6. THERMAL RESISTANCE

Characteristic

Thermal Resistance Junction to Exposed Pad (Note 1) SSOP36−EP Rthjp − 3.5 − °C/W

1. Includes also typical solder thickness under the Exposed Pad (EP).

Package Symbol Min Typ Max Unit

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ELECTRICAL CHARACTERISTICS

Table 7. VDD: 3.3 V LOW VOLTAGE ANALOG AND DIGITAL SUPPLY

Characteristic Symbol Conditions Min Typ Max Unit

The Regulator Output Voltage VDD 3.05 3.45 3.6 V VDD External Decoupling Cap C_DD 0.3 0.47 2.2 μF The VDRIVE Current Consumption (Note 2) I_VDRIVE 8 15 mA Output Current Limitation VDD_ILIM 15 160 mA POR Toggle Level on VDD Rising POR POR Toggle Level on VDD Falling POR POR Hysteresis POR OTP UV Toggle Level on VBOOST OTP_UV 13 15 V OTP UV Toggle Level Hysteresis OTP_UV_HYST 0.01 0.2 0.75 V

1. All Min and Max parameters are guaranteed over full junction temperature (TJP) range (−40 °C; 150 °C), unless otherwise specified.

2. Only internal consumption, Excluding LS NMOS gate charge current.

3V_H 3V_L

3V_HYST

Table 8. VBOOSTM3V: HIGH SIDE AUXILIARY SUPPLY

Characteristic

VBOOSTM3V Regulator Output Voltage V DC Output Current Capability (Note 1) M3V_IOUT 7.5 42 mA Output Current Limitation M3V_ILIM 300 mA VBOOSTM3V External Decoupling Cap C_M3V Referenced to VBOOST 0.1 0.47 2.2 VBOOSTM3V Ext. Decoupling Cap. ESR C_M3V_ESR Referenced to VBOOST 200 VBSTM3V POR Level, Falling Edge M3V_PORL Referenced to VBOOST −2.7 −1.8 V VBSTM3V POR Level, Rising Edge M3V_PORH Referenced to VBOOST −2.4 −1.8 V VBSTM3V POR Level Hysteresis M3V_PORHYST 0.05 V VBOOST POR Level M3V_VBSTPOR VBOOST goes down 3.5 5.5 V

1. VBOOST = 68 V, f

= 2 MHz, maximum total gate charge for both activated BUCK channels Qgate = 20 nC

BUCK

Symbol Conditions Min Typ Max Unit

BSTM3V

Referenced to VBOOST −3.6 −3.3 −3.0 V

2.7 3.05 V

2.45 2.8 V

0.01 0.2 0.75 V

Table 9. OSC10M: SYSTEM OSCILLATOR CLOCK

Characteristic Symbol Conditions Min Typ Max Unit

System Oscillator Frequency FOSC10M 8 10 12 MHz

Table 10. ADC FOR MEASURING VBOOST, VDD, VLED1, VLED2, TEMP

Characteristic

ADC Resolution ADC_RES 8 Bits Integral Nonlinearity (INL) ADC_INL Best fitting straight line method −1.5 1.5 LSB Differential Nonlinearity (DNL) ADC_DNL Best fitting straight line method −2 2 LSB Full Path Gain Error for

Measurements of VLEDx, VBOOST

Offset at Output of ADC ADC_OFFS −2 2 LSB Time for 1 SAR Conversion ADC_CONV Full conversion of 8 bits 6.67 8 10 ADC Full Scale for VDD

Measurement ADC Full Scale for VLEDx

Measurement

Symbol Conditions Min Typ Max Unit

ADC_GE −3.25 3.25 %

ADCFS_VDD 3.87 4 4.13 V

ADCFS_VLED00 The VLED range code is “00” 67.725 70 72.275 V

ADCFS_VLED01 The VLED range code is “01” 48.375 50 51.625 V

ADCFS_VLED10 The VLED range code is “10” 38.700 40 41.300 V

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Table 10. ADC FOR MEASURING VBOOST, VDD, VLED1, VLED2, TEMP (continued)

Characteristic UnitMaxTypMinConditionsSymbol

ADC Full Scale for VLEDx Measurement

ADC Full Scale for VBOOST Measurement

TSD Threshold Level ADC_TSD ADC measurement of junction

Temperature measurement accuracy at hot

Temperature measurement accuracy at cold

VLED Input Impedance VLED_RES 280 790

Table 11. BUCK REGULATOR – SWITCH

Characteristic Symbol Conditions Min Typ Max Unit

On Resistance, Range 1 RON1 At room−temperature, I(VINBCKx) = 0.18 A,

On Resistance at Hot, Range 1 RON1_H At Tj = 160 °C, I(VINBCKx) = 0.18 A,

On Resistance, Range 2 RON2 At room−temperature, I(VINBCKx) = 0.375 A,

On Resistance at Hot, Range 2 RON2_H At Tj = 160 °C, I(VINBCKx) = 0.375 A,

On Resistance, Range 3 RON3 At room−temperature, I(VINBCKx) = 0.75 A,

On Resistance at Hot, Range 3 RON3_H At Tj = 160 °C, I(VINBCKx) = 0.75 A,

On Resistance, Range 4 RON4 At room−temperature, I(VINBCKx) = 1.5 A,

On Resistance at Hot, Range 4 RON4_H At Tj = 160 °C, I(VINBCKx) = 1.5 A,

On Resistance, Range 5 RON5 At room−temperature, I(VINBCKx) = 3 A,

On Resistance at Hot, Range 5 RON5_H At Tj = 160 °C, I(VINBCKx) = 3 A,

Switching Slope – ON Phase TRISE Normal mode (DRV_SLOW_EN = “0”) 3 V/ns Switching Slope – OFF Phase

(Note 22) Switching Slope – ON Phase TRISE_SL Slow mode (DRV_SLOW_EN = “1”) 1.5 V/ns Switching Slope – OFF Phase

(Note 22)

1. Falling switching slope depends on used current (range, current sense threshold level) and LBCKSWx node capacitance.

ADCFS_VLED11 The VLED range code is “11” 29.025 30 30.975 V

ADCFS_VBST 67.725 70 72.275 V

163 169 175 °C

temperature

ADC_TEMP_H T = 155°C −7 7 °C

ADC_TEMP_C T = −40°C −15 15 °C

7.36

V(BOOST − VINBCKx)  0.2 V

6.3 10.2

V(BOOST − VINBCKx)  0.2 V

3.68

V(BOOST − VINBCKx) 0.2 V

3.2 5.12

V(BOOST − VINBCKx) 0.2 V

1.84

V(BOOST − VINBCKx) 0.2 V

1.7 2.56

V(BOOST − VINBCKx) 0.2 V

0.92

V(BOOST − VINBCKx) 0.2 V

0.9 1.28

V(BOOST − VINBCKx) 0.2 V

0.46

V(BOOST − VINBCKx) 0.2 V

0.5 0.64

V(BOOST − VINBCKx) 0.2 V

TFALL Normal mode (DRV_SLOW_EN = “0”) 3 V/ns

TFALL_SL Slow mode (DRV_SLOW_EN = “1”) 1.5 V/ns

Table 12. BUCK REGULATOR – CURRENT REGULATION

Characteristic Symbol Conditions Min Typ Max Unit

Current Sense Threshold Level, Range 1, Min Value

Current Sense Threshold Level, Range 1, Spec. Value

Current Sense Threshold Level, Range 1, Max Value

Current Sense Threshold Level, Range 2, Min Value

ITHR1_000 [BUCKx_VTHR = 000000000]

end of the BUCK ON−phase

ITHR1_219 [BUCKx_VTHR = 011011011]

end of the BUCK ON−phase

Min. value for specified precision

ITHR1_511 [BUCKx_VTHR = 111111111]

end of the BUCK ON−phase

ITHR2_000 [BUCKx_VTHR = 000000000]

end of the BUCK ON−phase

23.40 29.30 35.20 mA

117.19 mA

234.38 mA

46.90 58.59 70.30 mA

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Table 12. BUCK REGULATOR – CURRENT REGULATION (continued)

Characteristic UnitMaxTypMinConditionsSymbol

Current Sense Threshold Level, Range 2, Spec. Value

Current Sense Threshold Level, Range 2, Max Value

Current Sense Threshold Level, Range 3, Min Value

Current Sense Threshold Level, Range 3, Spec. Value

Current Sense Threshold Level, Range 3, Max Value

Current Sense Threshold Level, Range 4, Min Value

Current Sense Threshold Level, Range 4, Spec. Value

Current Sense Threshold Level, Range 4, Max Value

Current Sense Threshold Level, Range 5, Min Value

Current Sense Threshold Level, Range 5, Spec. Value

Current Sense Threshold Level, Range 5, Max Value

Current Sense Threshold Increase per Code, Range 1

Current Sense Threshold Increase per Code, Range 2

Current Sense Threshold Increase per Code, Range 3

Current Sense Threshold Increase per Code, Range 4

Current Sense Threshold Increase per Code, Range 5

Current Threshold Accuracy Only with Trimming Constant for Range 5 (Note 23)

Current Threshold Accuracy without Temperature Compensation (Note 23)

Current Threshold Accuracy (Note 23)

Offset of Peak Current Comparator

Over−current Detection Level, Range1

Over−current Detection Level, Range2

Over−current Detection Level, Range3

ITHR2_219

ITHR2_511 [BUCKx_VTHR = 111111111]

ITHR3_000 [BUCKx_VTHR = 000000000]

ITHR3_219 [BUCKx_VTHR = 011011011]

ITHR3_511 [BUCKx_VTHR = 111111111]

ITHR4_000 [BUCKx_VTHR = 000000000]

ITHR4_219 [BUCKx_VTHR = 011011011]

ITHR4_511 [BUCKx_VTHR = 111111111]

ITHR5_000 [BUCKx_VTHR = 000000000]

ITHR5_219

ITHR5_511 [BUCKx_VTHR = 111111111]

dITHR1

dITHR2

dITHR3

dITHR4

dITHR5

ITHR_ERR_DD Specified for BUCKx_VTHR 

ITHR_ERR_D Specified for BUCKx_VTHR 

ITHR_ERR

CMP_OFFSET BUCKx_OFF_CMP_DIS = 1 −10 +10 mV

OCDR1 305 mA

OCDR2 609 mA

OCDR3 1219 mA

[BUCKx_VTHR = 011011011]

end of the BUCK ON−phase.

Min. value for specified precision

end of the BUCK ON−phase

Min. value for specified precision

end of the BUCK ON−phase

Min. value for specified precision

end of the BUCK ON−phase

[BUCKx_VTHR = 011011011]

end of the BUCK ON−phase

Min. value for specified precision

end of the BUCK ON−phase

9 bit, linear increase 0.40 mA

9 bit, linear increase 0.80 mA

9 bit, linear increase 1.61 mA

9 bit, linear increase 3.21 mA

9 bit, linear increase 6.42 mA

011011011, without the delta of

the trimming code and without

temp. compensation

011011011, with the delta of the

trimming code and without temp.

compensation

Specified for BUCKx_VTHR 

011011011, the delta of the

trimming code and temp.

compensation

234.38 mA

468.75 mA

93.80 117.19 140.60 mA

468.75 mA

937.5 mA

187.50 234.38 281.30 mA

937.5 mA

1875 mA

375.00 468.75 562.50 mA

1875 mA

3750 mA

−9 +9 %

−7 +7 %

−4 +4 %

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Table 12. BUCK REGULATOR – CURRENT REGULATION (continued)

Characteristic UnitMaxTypMinConditionsSymbol

Over−current Detection Level, Range4

Over−current Detection Level, Range5

Time Constant for Longest Off Time

Time Constant for Shortest Off Time

TOFF Time Relative Error with Temperature Compensation

TOFF Time Relative Error TOFF_ERR TC = Toff × VCOIL @ VLED > 2

TOFF Time Absolute Error TOFF_ERR_ABS TC = Toff × VCOIL @ VLED > 2

Time Constant Decrease per Code

Detection Level of VLED to be too Low

Zero−cross−detection Threshold Level

Zero−cross−detection Filter Time

HS Overvoltage Detection Threshold Level

HS Overvoltage Detection Filter Time

HS Gate Voltage Detection Threshold Level

HS Gate Voltage Detection Filter Time

OpenLEDx Detection Time TON_OPEN 40 50 60 Buck Minimum TON Time TON_MIN For

Delay from BUCKx ISENS Comparator Input Voltage Balance to BUCKx Switch Going OFF

1. Measured as comparator DC threshold value, without comparator delay and switch falling slope.

OCDR4 2437 mA

OCDR5 4875 mA

TC_00 [BUCKx_TOFF = 00000] 50

TC_31 [BUCKx_TOFF = 11111] 5

TOFF_ERRW TC = Toff × VCOIL @ VLED > 2

Toff > 350 ns, Toff temperature

dependency relative to Thot =

155°C, see Figure 8

dTC

VLED_LMT 1.62 1.8 1.98 V

TC_ZCD −2.8 −1.2 −0.2 mV

TC_ZCD_FT 20 80 ns

OVD_THR LBCKSWx−VINBCKx, rising

OVD_FT 100 ns

HSVT_THR 0.6 V

HSVT_FT 45 ns

ISENSCMP_DEL ISENS cmp. over−drive ramp >

5 bits, exponential decrease 7.16 %

VINBCKx – LBCKSWx < 2.4 V,

no failure at LBCKSWx pin

for Slope = 1.25 A/μs, @125°C

Toff > 350 ns

Toff 350 ns

edge

1 mV/10 ns,

−10 +10 %

−15 +15 %

−35 +35 ns

100 200 mV

50 250 ns

45 ns

ms × V

Table 13. BUCK REGULATOR – LS SWITCH PRE−DRIVER

Characteristic

Top Switch Ron Ront 40 Bottom Switch Ron Ronb 8 The Pull Down Resistor LS_PUD 10 LS FET Gate Voltage Threshold Level LS_VT Comparator level for non−overlap

LS FET Gate Voltage Comparator Propagation Delay

The Maximum Reverse Polarity Current LS_IREV LSx_IREV_NOCTRL = 1 300 mA

Symbol Conditions Min Typ Max Unit

0.4 V

control when LS−>off, HS−>on

LS_DEL 10 ns

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Table 13. BUCK REGULATOR – LS SWITCH PRE−DRIVER (continued)

Characteristic UnitMaxTypMinConditionsSymbol

The non−overlap Time LS−off to HS−on

1. The time from detection of the LS switch in off state (pre−driver voltage at LS_VT threshold), to start of switching HS on.

Table 14. 5 V TOLERANT DIGITAL INPUTS (SCLK, CSB, SDI, LEDCTRL1, LEDCTRL2, RSTB)

Characteristic

High−level Input Voltage VINHI 2 V Low−level Input Voltage VINLO 0.8 V Pull Resistance (Note 1) Rpull 40 160 LED PWM Propagation Delay (Note 2) BUCKx_SW_DEL Activation time of the BUCKx

Sampling Resolution LEDCTRL_SR 100 125 ns RSTB Debouncer Time RSTB_DEB 100 200 ns

1. Pull down resistor (Rpd) for RSTB, LEDCTRLx, SDI and SCLK, pull up resistor (Rpu) for CSB to VDD.

2. Jitter is present due to the internal resynchronization.

LS_DT Adaptive: LSx_NO_MD[1:0] = 00

30 ns

(Note 1) LS_FNO1 Adaptive: LSx_NO_MD[1:0] = 01 1 6.5 LS_FNO2 Fixed: LSx_NO_MD[1:0] = 10 2.5 LS_FNO3 Fixed: LSx_NO_MD[1:0] = 11 5

Symbol Conditions Min Typ Max Unit

4.4 5.5 6.95

switch from the LEDCTRLx pin

% of

Toff

Table 15. 5 V TOLERANT OPEN−DRAIN DIGITAL OUTPUT (SDO)

Characteristic

Low−voltage Output Voltage VOUTLO Iout = −10 mA (current flows into the pin) 0.4 V Equivalent Output Resistance RDSON Lowside switch 10 40 SDO Pin Leakage Current SDO_ILEAK 2 SDO Pin Capacitance SDO_C 10 pF CLK to SDO Propagation

Delay

Symbol Conditions Min Typ Max Unit

SDO_DL Low−side switch activation/deactivation time;

60 ns

@1 kΩ to 5 V, 100 pF to GND, for falling edge V(SDO) goes below 0.5 V

Table 16. 3V DIGITAL INPUTS (TEST, TEST1, TEST2)

Characteristic

High−level Input Voltage VIN3HI 2.3 V Low−level Input Voltage VIN3LO 0.8 V Pull Resistance Rpd3 Pull−down resistance 60

Symbol Conditions Min Typ Max Unit

Table 17. SPI INTERFACE

Characteristic

CSB Setup Time t CSB Hold Time t SCLK Low Time t SCLK High Time t Data−in (DIN) Setup Time, Valid Data

before Rising Edge of CLK Data−in (DIN) Hold Time, Hold Data after

Rising Edge of CLK Output (DOUT) Disable Time (Note1) t Output (DOUT) Valid (Note 1) Output (DOUT) Valid (Note 2)

Symbol Conditions Min Typ Max Unit

CSS CSH

WL WH

DIS

V1→0

V0→1

0.5 μs

0.25 μs

0.5 μs

0.25 μs

0.275 μs

0.08 0.32 μs

0.32 μs

0.32 + t(RC) μs

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Table 17. SPI INTERFACE (continued)

Characteristic UnitMaxTypMinConditionsSymbol

Output (DOUT) Hold Time t CSB High Time t

1. SDO low–side switch activation time

2. Time depends on the SDO load and pull–up resistor

NCV78825

0.01 μs 1 μs

CSB

SCLK

DIN

DOUT

HI−Z

Initial state of SCLK after CSB falling edge is don’t care, it can be low or high

CSS

tHt

DIN15

DIN14

DIN13

CSB

DIN1

DOUT15 DOUT14 DOUT13 DOUT1 DOUT0

Figure 5. SPI Communication Timing

DIN0

CSH

DIS

HI−Z

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TYPICAL CHARACTERISTICS

NCV78825

Accuracy (±4% / ±7% / ±9%) guaranteed from VTHR code 219 [dec]

219

Figure 6. Buck Peak Current vs. Ranges and VTHR Code

120

[%]

100

79,2

72,9

41,0

Buck Switch Rdson relative to value at 1605C

−40 −20 0 20 40 60 80 100 120 140 160

45,6

50,6

55,7

61,1

66,8

Temperature [5C]

85,9

100,0

92,7

Figure 7. Typical Temperature Behavior of Buck HS Switch Rdson Relative to the V alue at 160ºC

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